COE4OI5 Engineering Design Chapter 2: UP2/UP3 board

COE4OI5Engineering Design

Chapter 2: UP2/UP3 board

2Copyright S. Shirani

UP3• UP3 board contains a Cyclone FPGA, several memory

devices and a wide range of I/O features• Two versions of the board are available one based on C6 and

the other one based on C12 FPGA.• The FPGA and memory devices can be programmed using a

JTAG ByteBlaster II cable attached to the PC printer (parallel) port

• The printer port mode of the PC should be set in the PC’s BIOS to ECP or EPP.


UP3• An on-board clock oscillator and clock chip provides several

clock signals that are selectable with the board’s jumpers


Figure 2.1 The Altera UP 3 board.

5Copyright S. ShiraniFigure 2.2 The Altera UP 3 board’s features.

Parallel PortVGAPort

B B B

Santa Cruz Expansion Long Connector



JP6

On/OffSwitch

PowerConnector

MountingHole

HeatSink

HeatSink

+5 VoltSupplyLED

+3.3 VoltSupplyLED

HeatSink B B

Flash

BReset

GlobalReset

4 User Definable DIP Switches (JP3)

4 Push Buttons

SRAM4 User

DefinableLEDs

Input ClockSetting Headers

Oscillator Chip

Cyclone FPGAEP1C6Q240C8

I2C PROMChip .....

Headersfor I2C

Bus SignalsUSB PHYChip

PS-2Port

USBPort

Invalid Volt. LED

JTAG & ASDownload

Connectors

“B”- Buffer Chips

Liquid Crystal Display

Real Time Clock

J5

J7

JP19

JP4LED

SerialChip

J3

J2 J4

J1

JP19

JP5

JP7JP3

SW7

SW6

SW5

SW4

D3

D4

D5

D6


Table 2.1 UP 3 Board’s Cyclone FPGA Features

173185 User I/O pins

2 2Phase Locked Loops (PLLs)

239,61692,160 Total Internal RAM bits

52 20 4K bit RAM blocks (M4Ks)

12,060 5,980 Logic Elements (LEs)

EP1C12Q240EP1C6Q240 Cyclone FPGA Feature


Memory• In addition to the Cyclone FPGA’s internal memory, the UP3

has several external ROM and RAM memory• Capacities of external memories are much larger than internal

memory but they have a longer access time• FPGA processor cores (e.g., Nios) use external memory for

program and data memory and the FPGA’s internal memory for registers and cache

• The serial flash chip is used to automatically load the FPGA’s serial configuration data at the power up in systems where you do not want to download the configuration data through the Byteblaster.


Table 2.2 UP 3 Board’s Memory Features

Altera EPCS11M by 1bitSerial Flash Memory

ISSI IS24C1616K by 1bitI2C EEPROM

Toshiba TC58FVB106AFT-701M by 16 bitsFlash Memory

ISSI IS42S16400B1M by 16 bitsSDRAM

ISSI IS61C641664K by 16 bitsSRAM

Part NumberSizeMemory Device


I/O• For most I/O devices, the UP3 board’s hardware provides

only an electrical interface to the FPGA’s I/O pins• Logic that provides a device interface circuit or controller

will need to be constructed using the FPGA’s internal logic (UP core functions)

• Also remember to assign pins as shown in the tutorial to avoid turning on several of the memory devices at the same time

• Do NOT connect high current devices such as motors or relay coils directly to FPGA I/O pins


Table 2.3 Overview of the UP 3 Board’s I/O Features

None or Synchronizer Circuit4 Switches (1=ON)DIP Switch

Serial Data - I2C state machineI2C clock chipReal Time Clock

State machine or Processor to send ASCII characters and LCD commands

16 Character by 2 lineASCII Characters

LCD Display

None4 User Definable (1=ON)LEDs

Depends on expansion card usedSanta Cruz Long 72 I/OExpansion Card

Most applications will need a switch debounce Circuit4 Non-debounced (0=HIT)Pushbutton Switches

Must use a reset in designUse for Global ResetReset Switch

Processor & IDE Device DriverConnectorIDE Port

State machine for sync signals & user logic to generate RGB color signals

RGB three 1-bit signals provide 8 colorsVGA Port for Video Display on Monitor

Serial Data - PS/2 state machinePC Keyboard or MousePS/2 Port

State machine or Proc. for handshakeIEEE 1284Parallel Port

UART to send and receive dataRS 232 Full ModemSerial Port

Processor & USB SIE engine coreFull Speed and Low SpeedUSB 1.1

Hardware Interface NeededDescriptionI/O Device


Table 2.4 UP 3 Board’s most commonly used FPGA I/O pin names and assignments

DIP Switch SW3 #4 ( ON = 1, OFF = 0)Input61DIPSWITCH_4

DIP Switch SW3 #3 ( ON = 1, OFF = 0)"Input60DIPSWITCH_3



Pushbutton SW6 (non-debounced, 0 = hit)Input57PBSWITCH_6

LED D6 (0 = LED ON, 1= LED OFF)Output56LED_D3




LCD Enable lineOutput50LCD_E

Pushbutton SW5 (non-debounced, 0 = button hit)

Input49PBSWITCH_5

Pushbutton SW4 (non-debounced, 0 = button hit)

Input48PBSWITCH_4

External Clock from J2 Pin 2Input38USER_CLOCK

USB 48MHz Clock - jumperInput29USB_CLK

Power on or SW8 pushbutton reset ( Reset = 0 )

Input23RESET

PS2 ConnectorBidirectional13PS2_DATA

PS2 ConnectorBidirectional12PS2_CLK

Function of PinPin I/O TypePin#Pin Name


Table 2.4 (continued) UP 3 Board’s most commonly used FPGA I/O pin names and assignments

VGA Connector Red Video SignalOutput228VGA_RED

VGA Connector Horiz Sync SignalOutput227VGA_HSYNC

VGA Connector Vert Sync SignalOutput226VGA_VSYNC

VGA Connector Blue Video SignalOutput170VGA_BLUE

CPU Clock 100 or 66MHz - jumperInput153CPU_CLOCK

VGA Connector Green Video SignalOutput122VGA_GREEN

Memory/LCD Data BusBidirectional113MEM_DQ[7]

LCD Register Select LineOutput108LCD_RS



Memory/LCD Data BusBidirectional102(128)MEM_DQ[4]



Memory/LCD Data BusBidirectional96(133)MEM_DQ[1]


LCD R/W control lineOutput73LCD_RW

Pushbutton SW7 (non-debounced, 0 = hit)Input62PBSWITCH_7

Function of PinPin I/O TypePin#Pin Name


UP2/MAX• UP2 board supports both a MAX and a FLEX device. • The devices can be programmed using a JTAG ByteBlaster II

cable attached to the PC printer (parallel) port• Jumpers on the board select which device is programmed. • The MAX device is connected to two seven segment LED

displays, two eight-position DIP switches, sixteen LEDs• Two push buttons can be connected to the MAX using jumper

wires• Circuit board holes are provided for an additional 60-pin

expansion header that can be added to connect external hardware


FLEX_EXPAN_C

FLEX_10K

EPF10K20RC240-4 DAA239837

R

R

Mouse

25.175 MHzCLOCK

FLEX_EXPAN_AFLEX_PB1 FLEX_PB2

D1

D2

D3

D4

D5

D6

D7

D8

D9

D10

D11

D12

D13

D14

D15

D16

DC_IN FLEX_DIGIT

U1

JTAG_OUT

POWER TCK

MAX_SW1 MAX_SW2

EMP7128SLC84-7 BFD329837

R

R

VGAAdapter

P1

P2

P3P4

P9 P10P6P5

P7 P8

EPC

Figures 2.1 and 2.2 The Altera UP 1 board.


MAX FLEX

Table 2.1 UP 1 device selection jumpers for programming.


Pin Name Pin Type Pin Function of Pin

MSD_dp OUTPUT PIN 68 Most Significant Digit of Seven-segment Display Decimal Point Segment (0 = LED ON, 1 = LED OFF)

MSD_g OUTPUT PIN 67 MSD Display Segment G (0 = LED ON, 1 = LED OFF)

MSD_f OUTPUT PIN 65 MSD Display Segment F (0 = LED ON, 1 = LED OFF)

MSD_e OUTPUT PIN 64 MSD Display Segment E (0 = LED ON, 1 = LED OFF)

MSD_d OUTPUT PIN 63 MSD Display Segment D (0 = LED ON, 1 = LED OFF)

MSD_c OUTPUT PIN 61 MSD Display Segment C (0 = LED ON, 1 = LED OFF)

MSD_b OUTPUT PIN 60 MSD Display Segment B (0 = LED ON, 1 = LED OFF)

MSD_a OUTPUT PIN 58 MSD Display Segment A (0 = LED ON, 1 = LED OFF)

LSD_dp OUTPUT PIN 79 Least Significant Digit of Seven-segment Display Decimal Point Segment (0 = LED ON, 1 = LED OFF)

LSD_g OUTPUT PIN 77 LSD Display Segment G (0 = LED ON, 1 = LED OFF)

LSD_f OUTPUT PIN 75 LSD Display Segment F (0 = LED ON, 1 = LED OFF)

LSD_e OUTPUT PIN 76 LSD Display Segment E (0 = LED ON, 1 = LED OFF)

LSD_d OUTPUT PIN 74 LSD Display Segment D (0 = LED ON, 1 = LED OFF)

LSD_c OUTPUT PIN 73 LSD Display Segment C (0 = LED ON, 1 = LED OFF)

LSD_b OUTPUT PIN 70 LSD Display Segment B (0 = LED ON, 1 = LED OFF)

LSD_a OUTPUT PIN 69 LSD Display Segment A (0 = LED ON, 1 = LED OFF)

PB1 INPUT PIN * Push-Button 1 (non–debounced, 0 = button depressed)

PB2 INPUT PIN * Push-Button 2 (non–debounced, 0 = button depressed)

D1..D16 LEDs OUTPUT PIN *

16 Discrete LEDs - D1…D16

(0 = LED ON, 1 = LED OFF)

SW1 & SW2 INPUT PIN *

MAX DIP Switch Inputs - SWxS1...SWxS8

(1 = Open, 0 = Closed)

Clock INPUT PIN 83 25.175Mhz System Clock on low skew

Global Clock Line

Prototyping Header

Pins

INPUT, OUTPUT 1-84

Black Prototyping Headers next to MAX chip

Numbers are silk-screened on board.

Pins 12, 33, 54, 75, and 83 are not available.

* Jumper wires from the switch or LED to the MAX prototyping headers are required to use these devices.

Any available unused MAX header pin can be assigned to this device.

Note: A number of other pins are pre-assigned and required for programming, power, and ground connections.


UP2/FLEX• FLEX device is attached to a VGA connector, a PS/2 mouse

and keyboard port, two seven segment displays, an eight-position DIP switch and two push buttons.

• To generate video output, mouse or keyboard input, an interface must be designed using logic inside the FLEX device (UP core functions)

• Circuit board holes are provided for three 60-pin expansion header that can be added to connect external hardware

• Do NOT connect high current devices such as motors or relay coils directly to FPGA I/O pins


Pin Name Pin Type Pin Function of Pin

MSD_dp OUTPUT PIN 14 Most Significant Digit of Seven-segment Display - Decimal Point Segment (0 = LED ON, 1 = LED OFF)

MSD_g OUTPUT PIN 13 MSD Display Segment G (0 = LED ON, 1 = LED OFF)

MSD_f OUTPUT PIN 12 MSD Display Segment F (0 = LED ON, 1 = LED OFF)

MSD_e OUTPUT PIN 11 MSD Display Segment E (0 = LED ON, 1 = LED OFF)

MSD_d OUTPUT PIN 9 MSD Display Segment D (0 = LED ON, 1 = LED OFF)

MSD_c OUTPUT PIN 8 MSD Display Segment C (0 = LED ON, 1 = LED OFF)

MSD_b OUTPUT PIN 7 MSD Display Segment B (0 = LED ON, 1 = LED OFF)

MSD_a OUTPUT PIN 6 MSD Display Segment A (0 = LED ON, 1 = LED OFF)

LSD_dp OUTPUT PIN 25 Least Significant Digit of Seven-segment Display - Decimal Point Segment (0 = LED ON, 1 = LED OFF)

LSD_g OUTPUT PIN 24 LSD Display Segment G (0 = LED ON, 1 = LED OFF)

LSD_f OUTPUT PIN 23 LSD Display Segment F (0 = LED ON, 1 = LED OFF)

LSD_e OUTPUT PIN 21 LSD Display Segment E (0 = LED ON, 1 = LED OFF)

LSD_d OUTPUT PIN 20 LSD Display Segment D (0 = LED ON, 1 = LED OFF)

LSD_c OUTPUT PIN 19 LSD Display Segment C (0 = LED ON, 1 = LED OFF)

LSD_b OUTPUT PIN 18 LSD Display Segment B (0 = LED ON, 1 = LED OFF)

LSD_a OUTPUT PIN 17 LSD Display Segment A (0 = LED ON, 1 = LED OFF)

FLEX_switch_1 INPUT PIN 41 FLEX DIP Switch Input 1 (1 = Open, 0 = Closed)








PB1 INPUT PIN 28 Push-Button 1 (non–debounced, 0 = button depressed)

PB2 INPUT PIN 29 Push-Button 2 (non–debounced, 0 = button depressed)

Horiz_Sync OUTPUT PIN 240 VGA Video Signal - Horizontal Synchronization

Vert_Sync OUTPUT PIN 239 VGA Video Signal - Vertical Synchronization

Blue OUTPUT PIN 238 VGA Video Signal - Blue Video Data

Green OUTPUT PIN 237 VGA Video Signal - Green Video Data

Red OUTPUT PIN 236 VGA Video Signal - Red Video Data

PS2_CLK BIDIRECTIONAL 30 Clock line for PS/2 Mouse and Keyboard

PS2_DATA BIDIRECTIONAL 31 Data line for PS/2 Mouse and Keyboard

Clock INPUT PIN 91 25.175 MHz System Clock on low skew Global Clock Line

COE4OI5 Engineering Design Chapter 2: UP2/UP3 board

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