COE 202Introduction to Verilog

Computer Engineering Department

College of Computer Sciences and EngineeringKing Fahd University of Petroleum and Minerals

Outline Introduction Verilog Syntax Definition of a Module Gate Level Modeling Module Instantiation Propagation Delay Boolean Equation-Based Behavioral Models of

Combinational Logic Test Bench Example

Introduction Verilog is one of the hardware description languages

(HDL) available in the industry for hardware modeling, simulation and design.

It allows designers to describe their hardware at different levels of detail (e.g. gate-level, behavioral lavel)

Parallel not serial like programming languages. Verilog can describe everything from single gate to full

computer system.

Verilog A digital system can be described at several levels of

details (more details means more design entry time!): e.g. Gate-level Net-list similar to schematic or breadboarding Behavioral description: programming-like structures (if-then-

else, case, loops …etc) to describe what the circuit does (i.e. behavior) rather than how requires some additional (synthesis) software to actually obtain the logic design

A digital system is described as a set of modules The module is the basic unit of design

Verilog Syntax Identifiers:

composed of letters, digits, the underscore character (_), and the dollar sign ($). $ is usually used with a system task or function

The first character of an identifier must be a letter or underscore Verilog is a case-sensitive language D_BUS is different from

D_Bus

Keywords: predefined identifiers that are used to describe language constructs. E.g. module, wire …etc. Can not be used as user-defined identifiers

White space: space, tab, and newline characters are used to separate identifiers and can be used freely in the Verilog code

Comments: two forms; one-line comment starts with // and multiple-line comment is encapsulated between /* and */

Verilog Data Types Two groups of Data Types: net and variable. Net like wire; could be 1-bit or array (e.g. wire a; wire

[3:0] sum) Variable group like reg; The most commonly used data

type in this group Also integer

Module and Ports declarationmodule [module-name]

(

[mode] [ d a t a - t y p e ] [ p o r t - n a m e s ] ,

[mode] [ d a t a - t y p e ] [ p o r t - n a m e s ] ,

. . .

[mode] [ d a t a - t y p e ] [ p o r t - n a m e s ]

) ;

Data-type could be wire, reg, integer, real …etc.

Ex1.: module eq2 (input wire [1:0] a , b ,output wire aeqb

);

Ex2.: module eq1(input i0 , il , // no data type declarationoutput eq // all will be wires

);

Gate Level Modeling Net-list description

built-in primitives gates

module my_gate( output OUT1, input IN1, IN2);

wire X; // optional and (X, IN1, IN2);

not (OUT1, X);

endmoduleInternal Signal

XOUT1

IN2

IN1

Verilog Primitives Basic logic gates only

and or not buf xor These gates are expandable: 1st node nand is O/P node, followed by 1, 2, 3 … nor number of input nodes xnor

Primitive Pins Are Expandable

nand (y, in1, in2) ;

nand (y, in1, in2, in3) ;

nand (y, in1, in2, in3, in4) ;

A Half Adder

module Add_half (output c_out, sum, input a, b);

xor (sum, a, b);and (c_out, a, b);

endmodule

A Full Addermodule fadd (output co, s, input a, b, c);

wire n1, n2, n3; // optionalxor (n1, a, b) ;

xor (s, n1, c) ;

nand (n2, a, b) ;

nand (n3,n1, c) ;

nand (co, n3,n2) ;

endmodule

Module Instantiation Two ways to connect the ports of the instantiated module

to the signals in the instantiating module: 1. By name:

[module-name] [instance-name]

(

. [port-name] ( [signal-name] ) ,

.[port-name] ([signal-name]),

);

2. By order:

Add_half M1 (.c_out(Cout), .sum(Sum), .a(A), .b(B));

Add_half M2 (Cout, Sum, A, B);

module Add_half (output c_out, sum, input a, b);

xor (sum, a, b);and (c_out, a, b);

endmodule

Module Instantiation

Propagation Delaymodule Add_full_unit_delay(output c_out, sum, input a, b, c_in); wire w1, w2, w3; // optional Add_half_unit_delay M1 (w2, w1, a, b); Add_half_unit_delay M2 (w3, sum, c_in, w1); or #2 (c_out, w2, w3);endmodule

module Add_half_unit_delay (output c_out, sum, input a, b); xor #3 (sum, a, b); and #2 (c_out, a, b);endmodule

Propagation Delay

Assign Statement The keyword assign declares a continuous assignment. It associates the Boolean expression on the RHS (right

hand side) with the variable on the LHS (left hand side). The assignment is sensitive to the variables in the RHS. Any time an event occurs on any of the variables on the

RHS, the RHS expression is revaluated and the result is used to update the LHS.

Boolean Equation-Based Behavioral Models of Combinational Logic A Boolean equation describes combinational logic by an

expression of operations on variables. In Verilog, this is done by continuous assignment

statement. Example:

module AOI_5_CA0 (

input x_in1, x_in2, x_in3, x_in4, x_in5,

output y_out);

assign y_out = ~( (x_in1 & x_in2) | (x_in3 & x_in4 & x_in5) );

endmodule

Full Addermodule fadd (output Cout, S, input A, B, Cin);

assign S = A ^(B ^ Cin);

assign Cout = (A & B) | (A & Cin) | (B & Cin) ;

endmodule

A

BCin

Cout

S

Propagation Delay & Continuous Assignment

Propagation delay can be associated with a continuous assignment so that its implicit logic has same functionality and timing characteristics as its gate level implementation.

module fadd (output Cout, S, input A, B, Cin); assign #6 S = A ^(B ^ Cin); assign #5 Cout = (A & B) | (A & Cin) | (B & Cin); endmodule

Testbench Examplemodule t_Add();

wire Sum, Cout;

reg a, b, cin;

Add_full_unit_delay M1 (Cout, Sum, a, b, cin);

initial begin a=0; b=0; cin=0;

#10 b=1;

#10 a=1; cin=1;

#10 b=0;

endendmodule

Testbench Example The keyword initial declares a single-pass behavior that

begins executing when the simulator is activated. Statements within begin and end block keywords are called

procedural statements. Procedural statements execute sequentially # is a delay control operator A delay control operator preceding procedural assignment

statement suspends its execution and the execution of subsequent statements for specified delay time

reg declaration ensures that variables will keep their value until the next procedural assignment statement