Coarse Radio Signal Classi er on a Hybrid FPGA/DSP/GPP ... · PSD Power Spectral Density PLL Phase...

Coarse Radio Signal Classifier on a Hybrid FPGA/DSP/GPPPlatform

Sujit Nair

Thesis submitted to the Faculty of theVirginia Polytechnic Institute and State University

in partial fulfillment of the requirements for the degree of

Master of Sciencein

Electrical Engineering

Dr. Charles W. Bostian, ChairDr. Allen MacKenzie

Dr. Cameron Patterson

Dec 07, 2009Blacksburg, Virginia

Keywords: Cognitive Radio, SDR, FPGA, DSP, GPP, Signal Classifier

Copyright 2009, Sujit Nair

Coarse Radio Signal Classifier on a Hybrid FPGA/DSP/GPP Platform

Sujit Nair

ABSTRACT

The Virginia Tech Universal Classifier Synchronizer (UCS) system can enable a cognitivereceiver to detect, classify and extract all the parameters needed from a received signal forphysical layer demodulation and configure a cognitive radio accordingly. Currently, UCScan process analog amplitude modulation (AM) and frequency modulation (FM) and digitalnarrow band M-PSK, M-QAM and wideband signal orthogonal frequency division multiplex-ing (OFDM). A fully developed prototype of UCS system was designed and implemented inour laboratory using GNU radio software platform and Universal Software Radio Peripheral(USRP) radio platform. That system introduces a lot of latency issues because of the limitedUSB data transfer speeds between the USRP and the host computer. Also, there are inherentlatencies and timing uncertainties in the General Purpose Processor (GPP) software itself.Solving the timing and latency problems requires running key parts of the software-definedradio (SDR) code on a Field Programmable Gate Array (FPGA)/Digital Signal Processor(DSP)/GPP based hybrid platform.

Our objective is to port the entire UCS system on the Lyrtech SFF SDR platform whichis a hybrid DSP/FPGA/GPP platform. Since the FPGA allows parallel processing on awideband signal, its computing speed is substantially faster than GPPs and most DSPs,which sequentially process signals. In addition, the Lyrtech Small Form Factor (SFF)-SDRdevelopment platform integrates the FPGA and the RF module on one platform; this furtherreduces the latency in moving signals from RF front end to the computing component. Alsofor UCS to be commercially viable, we need to port it to a more portable platform whichcan be transitioned to a handset radio in the future.

This thesis is a proof of concept implementation of the coarse classifier which is the first stepof classification. Both fixed point and floating point implementations are developed and nocompiler specific libraries or vendor specific libraries are used. This makes transitioning thedesign to any other hardware like GPPs and DSPs of other vendors possible without havingto change the basic framework and design.

Acknowledgments

I owe my deepest gratitude to Dr. Charles Bostian whose encouragement, guidance andsupport helped my through every step. I could not have wished for a better or friendlieradvisor.

I would also like to thank members of my committe – Dr. Cameron Patterson and Dr. AllenMackenzie for providing me insights and reviewing this thesis.

I am also indebted to my colleagues in CWT who have supported me these last two years.They have made the lab a great place to work and I have thoroughly enjoyed my time in thelab. We are very lucky to have Judy Hood who has been extremely helpful and has takenvery good care of us.

I would also like to thank my friends who have made my stay in Blacksburg very enjoyable.

Most importantly, I would like to thank my parents for their unconditional love and support.They have made a lot of sacrifices and this thesis is dedicated to them.

iii

Grant Information

This work was partially sponsored by DARPA through Air Force Research Laboratory(AFRL) Contract FA8750-07-C-0169. The views and conclusions contained in this docu-ment are those of the authors and should not be interpreted as representing the officialpolicies, either expressed or implied, of the Defense Advanced Research Projects Agency orthe U.S. Government.

iv

Contents

Acknowledgments iii

Grant Information iv

List of Figures xi

List of Tables xii

List of Acronyms xiii

1 Introduction 1

1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.2 Signal Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.3 Objectives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

1.4 Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

2 Universal Classifier Synchronization (UCS) System 4

2.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2.2 System Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2.3 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

3 OFDM Signal Classification and Synchronization 11

3.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

3.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

v

3.3 OFDM Application in DSA . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

3.4 System Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

3.4.1 System Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

3.4.2 Detection of OFDM signal and coarse carrier frequency estimation . . 15

3.4.3 Estimation of Symbol length and CP length . . . . . . . . . . . . . . 16

3.4.4 Carrier Frequency Synchronization . . . . . . . . . . . . . . . . . . . 19

3.4.5 Experiment and Simulation Results . . . . . . . . . . . . . . . . . . . 20

3.4.6 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

4 Lyrtech Small Form Factor Software Defined Radio 23

4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

4.2 Platform Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

4.2.1 Digital Processing Module . . . . . . . . . . . . . . . . . . . . . . . . 27

4.2.2 Data Conversion Module . . . . . . . . . . . . . . . . . . . . . . . . . 28

4.2.3 RF Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

4.2.4 FPGA-DSP Data Exchange . . . . . . . . . . . . . . . . . . . . . . . 30

4.3 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

5 Software 33

5.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

5.2 Model Based Design Approach . . . . . . . . . . . . . . . . . . . . . . . . . . 33

5.2.1 FPGA Software Development . . . . . . . . . . . . . . . . . . . . . . 35

5.2.2 DSP Software Development . . . . . . . . . . . . . . . . . . . . . . . 35

5.3 Observations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

5.4 Modifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

5.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

6 Broadband RF Parallel Sensor Using the Lyrtech SFF SDR 41

6.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

6.2 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

vi

6.3 Wideband Energy Detector Implementation . . . . . . . . . . . . . . . . . . 43

6.4 Simulation Using System Generator and Simulink . . . . . . . . . . . . . . . 44

6.5 Sensor Result Collection by a Host Computer . . . . . . . . . . . . . . . . . 45

6.6 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

7 Coarse Classifier Implementation 47

7.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

7.2 Features and technical requirements . . . . . . . . . . . . . . . . . . . . . . . 47

7.3 Fixed Point and Floating Point . . . . . . . . . . . . . . . . . . . . . . . . . 48

7.4 Partitioning the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

7.4.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

7.4.2 System Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

7.4.3 FPGA Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

7.4.4 DSP Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

7.5 Performance on Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

8 Results and Conclusions 60

A FPGA Resource Log 62

A.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

A.2 Resource Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

A.2.1 Resource utilization of single channel sensor . . . . . . . . . . . . . . 62

A.2.2 Resource utilization of two channel sensor . . . . . . . . . . . . . . . 63

A.2.3 Resource utilization of three channel sensor . . . . . . . . . . . . . . 63

B Source Code 65

B.1 ucsphase1.c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

B.2 ucsphase1.h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

C Permission from Lyrtech 75

vii

Bibliography 76

viii

List of Figures

2.1 UCS Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2.2 Power Spectral Density of a DQPSK signal . . . . . . . . . . . . . . . . . . . 6

2.3 Autocorrelation Plots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2.4 Phase plots comparing FM and BPSK . . . . . . . . . . . . . . . . . . . . . 7

2.5 Histogram of a DBPSK signal . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.6 Constellation Plots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

3.1 Two schemes for changing the bandwidth of an OFDM signal . . . . . . . . 14

3.2 System Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3.3 Self Correlation to detect OFDM . . . . . . . . . . . . . . . . . . . . . . . . 15

3.4 PSD of an OFDM signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.5 OFDM signal self correction . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

3.6 Estimation of CP length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

3.7 Convolution plot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3.8 Serial to Parallel processing of OFDM in transmitter side . . . . . . . . . . . 19

3.9 Comparison between the effect of frequency offset on OFDM signal and QPSKsignal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.10 Constellation plots with Occupied Subcarriers . . . . . . . . . . . . . . . . . 22

4.1 Second Generation Prototype Public Safety Cognitive Radio . . . . . . . . . 24

4.2 Lyrtech SFF SDR Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

4.3 Functional Blocks in the SFF SDR . . . . . . . . . . . . . . . . . . . . . . . 26

4.4 Digital Processing Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

ix

4.5 Data Conversion Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

4.6 RF Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

4.7 VPSS connection between the Virtex-4 and the TI DM6446 SoC . . . . . . . 30

4.8 VPSS configured as VPBE . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

4.9 VPSS configured as VPFE . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

5.1 Lyrtech Model Based Design Kit for Rapid Prototyping and deployment . . 34

5.2 SFF SDR Development Platform DSPLink library . . . . . . . . . . . . . . . 37

5.3 Development environments of the MathWorks and Texas Instruments . . . . 38

5.4 Modified Development Environment for the TI6446 . . . . . . . . . . . . . . 39

5.5 Modified Software Tool Chain for the Lyrtech SFF SDR . . . . . . . . . . . 40

6.1 System Bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

6.2 Division of System bandwidth into N sub-channels . . . . . . . . . . . . . . . 42

6.3 Carrier Sensing Block Diagram using Channelization . . . . . . . . . . . . . 43

6.4 Simulation of a single Channel using SysGen and Simulink . . . . . . . . . . 44

6.5 A Hypothetical Signal Power Spectral Density (PSD) . . . . . . . . . . . . . 45

7.1 System Level Design Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

7.2 Tasks implemented by FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . 51

7.3 Tasks implemented by DSP . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

7.4 Screenshot showing IF filtering after downconversion . . . . . . . . . . . . . 53

7.5 Digital Down Conversion Block . . . . . . . . . . . . . . . . . . . . . . . . . 53

7.6 FDATool to calculate filter coefficients . . . . . . . . . . . . . . . . . . . . . 54

7.7 PSD of a BPSK signal – Fixed Point . . . . . . . . . . . . . . . . . . . . . . 55

7.8 OFDM Autocorrelation Plot - Fixed Point . . . . . . . . . . . . . . . . . . . 56

7.9 BPSK Autocorrelation Plot - Fixed Point . . . . . . . . . . . . . . . . . . . . 56

7.10 OFDM Autocorrelation Plot - Floating Point . . . . . . . . . . . . . . . . . . 57

7.11 Phase Unwrap Plot for BPSK – Fixed Point . . . . . . . . . . . . . . . . . . 57

7.12 Phase Unwrap Plot for BPSK – Floating Point . . . . . . . . . . . . . . . . . 58

x

7.13 Phase Unwrap Plot for FM – Fixed Point . . . . . . . . . . . . . . . . . . . . 58

xi

List of Tables

2.1 Classification of single carrier signals . . . . . . . . . . . . . . . . . . . . . . 7

3.1 Parameter Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

6.1 Table showing measured values on screen . . . . . . . . . . . . . . . . . . . . 46

7.1 Performance Chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

xii

List of Acronyms

PHY Physical

SFF SDR Small Form Factor Software Defined Radio

AMR Automatic Modulation Recognition

LR Likelihood Ratio

UCS Universal Classifier Synchronizer

OFDM Orthogonal Frequency Division Multiplexing

OFDMA Orthogonal Frequency Division Multiplexing Access

FPGA Field Programmable Gate Array

DSP Digital Signal Processor

GPP General Purpose Processor

RF Radio Frequency

CR Cognitive Radio

DSA Dynamic Spectrum Access

M-PSK M-ary Phase Shift Keying

QAM Quadrature Amplitude Modulation

FSK Frequency Shift Keying

AM Amplitude Modulation

FM Frequency Modulation

DBPSK Differential Binary Shift Keying

DQPSK Differential Quadrature Shift Keying

OTA Over the Air

xiii

CP Cyclic Prefix

CPSK Continuous Phase Shift Keying

CPFSK Continuous Phase Frequency Shift Keying

PSD Power Spectral Density

PLL Phase Lock Loop

USRP Universal Software Radio Peripheral

IF Intermediate Frequency

FFT Fast Fourier Transform

BSDK Board Software Development Kit

MBDK Model-Based Development Kit

VPSS Video Processing Subsystem

ADC Analog to Digital Converter

DAC Digital to Analog Converter

VPFE Video Processing Front End

VPBE Video Processing Back End

FPU Floating Point Unit

xiv

Chapter 1

Introduction

1.1 Overview

One of the fundamentals that make a radio cognitive is its ability to know the RF environmentand optimize performance keeping in mind this environment. In a cognitive receiver, keyPHY layer signal parameters, including carrier frequency, baseband bandwidth, modulation,symbol rate and pulse shape, need to be recognized rather than assumed as in a conventionalstandards-based radio [1]. This thesis is about implementing a signal classification systemon the Lyrtech SFF SDR. This introduction takes a closer look at modulation classification,at the objectives of the work, and the organization of the remaining chapters.

1.2 Signal Classification

There has been a lot of analytical work done in the area of automatic modulation recognition(AMR). Properties of a desirable classifier include high probability of correct classificationin a short observation time for a large range of signal to noise (SNR) ratios. It should alsobe able to recognize different modulation schemes in diverse environments with differentpropagation characteristics while retaining robustness to model mismatches, real time func-tionality, and low computational complexity [2]. Most automatic modulation recognitiontechniques fall into one of two major categories - likelihood based techniques and featurebased approaches.

In general, likelihood ratio (LR) theory assumes a perfect knowledge of the symbol pulseshape at the receiver so that perfect matched filtering and sampling can be performed. Mostof the signal classification algorithms rely on simplified assumptions, which in real worldscenarios in the presence of multipath, fading environments etc. are unlikely to stand. Forinstance, if signal classifiers are used in scenarios where the receiver has no a priori knowledge

1

Sujit Nair Chapter 1. Introduction 2

of the transmitter, then it is unlikely that the receiver will be synchronized to the carrierfrequency and symbol rate of the transmitted signal which are essential for modulationclassification. In such cases, synchronization is the most challenging aspect of designing thereceiver (both symbol timing synchronization and carrier synchronization) and this aspectis not emphasized. Also since most of previous works’ results are based on ideal computersimulation environments, their validity and robustness when implemented in actual radiohardware remains questionable [1]. Additionally they are sensitive to pre-processing tasksthat include noise reduction, estimation of carrier frequency, symbol timing, equalizationetc.

Although there has been significant research in the area of signal classification, very littlework has been attempted to transition it to the hardware domain; especially embeddedsoftware defined radio platforms. Real time functionality and low complexity are two keyfeatures needed to make the implementation of signal classification algorithms on embeddedhardware devices a reality. The Universal Classifier Synchronizer (UCS) system, which iscovered in the next chapter, can demodulate the transmitted waveform having minimal priorinformation about the transmitter.

1.3 Objectives

This work has three main objectives:

1. Extending UCS to classify OFDM signals

2. Implement the coarse classifier on a hybrid SDR platform

3. Develop the framework and make the implementation flexible

Our main goal here is to transition the UCS algorithm which currently runs on a laptopcomputer, to an embedded radio platform so it can be more used in public safety andmilitary applications.

Along with the implementation, we modify the software development tool chain to suit ourneeds. The process is detailed in subsequent chapters. Along the roadmap for developinga coarse classifier, we exploit the Virtex-4 FPGA in the Lyrtech SFF SDR by using it toimplement a multichannel sensor.

One important thing for the reader to note is that even though the implementation targetsthe Lyrtech SFF SDR, the concepts and the design extend much more broadly. For example,code developed for the TI C64x DSP can run even in a microprocessor without a floatingpoint unit.

Sujit Nair Chapter 1. Introduction 3

1.4 Organization

The thesis is organized into five major sections:

Chapter 2 UCS System: What is the Universal Classifier Synchronization (UCS) system?reviews the UCS system and related work

Chapter 3 OFDM Signal Classification: How does UCS handle multi-carrier signals?explains the algorithm for classifying OFDM signals

Chapter 4 Lyrtech SFF SDR: What is the Lyrtech SFF SDR platform?gives details about the platform and its hardware modules

Chapter 5 Experience using Software Tools: How do we program the Lyrtech SFF SDR?discusses software design tool chain and modifications

Chapter 6 Broadband Parallel RF sensor: How do we exploit the Virtex-4 FPGA?implementation of a wideband multichannel RF sensor on the Lyrtech SFF SDR

Chapter 7 Implementation of a Coarse Classifier: How do we implement the classifier?discuss FPGA and DSP models with performance measurements

Chapter 8 Conclusions: What are the main contributions?summarizes the main contributions of this thesis and future work

Chapter 2

Universal Classifier Synchronization(UCS) System

2.1 Overview

UCS can automatically interpret features of the received signal to accomplish physical layerclassification, synchronization and demodulation without any a priori information aboutthe waveform from the transmitter side. The previous chapter discussed the theoreticalmotivation and background for developing signal classification systems. The chapter beginswith an explanation of the UCS system design focusing our attention to parts of the systemthat are implemented on the Lyrtech SFF SDR, and then turns to the extension of thealgorithm to cover wideband OFDM signals.

The aim of this chapter is to not to dwell into the details of the UCS algorithm in greatdepth, but to provide a system overview so the reader better understands the implementationwhich follows in the subsequent chapter. This discussion gives a functional description ofeach of the blocks without focusing on the theoretical analysis and is basically a summaryof the work that is explained in great detail in [3], [4] and [5]. Readers interested in a moredetailed explanation of the UCS algorithm should refer to these and Chapter 5 of YingWang’s dissertation [6].

Extracting parameters from a received signal and automatically demodulating it based onthese parameters without any cooperation from the transmitter is extremely beneficial toCognitive Radios (CR), Dynamic Spectrum Access and many other applications [3].

4

Sujit Nair Chapter 2. UCS System 5

2.2 System Description

Figure 2.1 shows the functional block diagram of the UCS system

Figure 2.1: Functional Block Diagram of the UCS system [5]

The first block in the system is the spectrum sensing block, which provides informationabout the signal in the frequency domain. Out of the spectrum that is swept by the RFfront end, we narrow down to the signal of interest if energy is detected. This signal isthen downconverted to IF frequency and this signal is then analyzed for obtaining furtherinformation like the correct symbol timing, modulation type and carrier phase and frequency.

The method adopted for energy detection is based on the power spectral density (PSD) andwhen the PSD exceeds a predefined threshold, we consider that a signal is present and goahead with the classification. See Figure 2.2.

After the spectrum sensing block, the next stage is to classify the signal as single carrieror multi-carrier signal. Currently UCS accommodates OFDM as multicarrier modulation.To identify a signal as OFDM, we correlate the incoming signal with itself [4]. The resultsof the OTA experiments are shown for MPSK, analog FM and OFDM signal in Figure2.1. The correlated output is different in the case of narrowband modulations and OFDMmodulation. This difference is due to the cyclic prefix present in the OFDM signal, whichgives us multiple peaks as opposed to a single peak in narrowband modulations.

The primary focus of the implementation of UCS on the Lyrtech SFF SDR is the catego-rization of single carrier signals. We implement a coarse classifier that analyzes the features


Figure 2.2: Power Spectral Density of a DQPSK signal [3]

Figure 2.3: Autocorrelation Plots [4]

of the single carrier signal like instantaneous phase, frequency and amplitude. Our aim is tocategorize the incoming signal into the following major segments for subsequent processingby later parts of UCS.

Single carrier signals are first classified as phase continuous or phase discontinuous signals.The phase continuous signals are AM, FM or CPSK (P25 modulation scheme). Phasediscontinuous can be any M-PSK scheme or QAM modulation.

When the phase change between two adjacent samples is larger than a certain threshold, itcan be considered that the phase discontinuity i.e. phase jump is caused by the informationencoded in the phase. This essentially means for an equivalent number of samples collected,the phase jumps for a phase discontinuous signal are much larger than the phase jumps fora phase continuous signal. Therefore an incoming single carrier signal can be identified as


Table 2.1: Classification of single carrier signals [5]

Continuous Phase Discontinuous PhaseConstant Amplitude Varying

AmplitudeSingle-valueenvelope

Multiple-valueenvelope

Continuous freq. Discrete freq.AM MPSK QAM

FM CPFSK

Figure 2.4: Time Varying phase plots comparing FM and BPSK [3]

phase continuous or a phase discontinuous based on this.

The phase continuous family includes AM, FM and CPFSK. These modulations can beseparated from each other by looking at their envelope characteristics. FM and CPFSK havea constant envelopes, whereas an AM signal’s envelope keeps changing with the information.Consequently, the variation in the amplitude of an AM envelope is more than that of an FMor a CPFSK envelope. Thus the envelope variation is the second stage of classification.

After performing coarse classification, the next important block of the UCS system is symboltiming estimation. For the symbol timing estimation to work efficiently, we need to havea good estimate of the bandwidth of the incoming signal. The bandwidth is calculated byusing the histogram of the PSD as opposed to the traditional 3dB bandwidth approach. For


finding out the bandwidth of the signal, we look for a point in the histogram where there isa dramatic change in the PSD.

Figure 2.5: Histogram of a DBPSK signal [5]

This point will lie in between the histogram of noise and the histogram of the signal as shownby the red line in the figure. When the line shown in Figure 2.5 is mapped to the PSD plot,we get the lower and upper limits indicated by the red line in Figure 2.2 for calculating thebandwidth.

From the estimated bandwidth, the symbol rate can be calculated by using the formula

Rest =BWest

1 + r

where Rest is the estimated symbol rate and r is the roll off the transmitted raised cosinepulse.

The aim of the symbol synchronization block is to find the correct symbol rate and findthe symbol timing sampling instant from the candidate space that is derived based on theestimated bandwidth. For correct symbol synchronization to occur, based on the estimatedcandidate space we need to resample the incoming signal and then search for the correctsymbol rate and sampling instant by using the minimum variance algorithm that is explainedin detail in [3] [5]. Along with finding the symbol timing information, this stage also


differentiates MPSK and QAM based on their envelopes. If we take the samples’ envelopein each element of the candidate space, and if the cluster is centralized around one constantvalue then it is MPSK; if it not, then depending on the number of centralized values we canclassify it as 16QAM (3 values), 64QAM (9 values) etc.

When the modulation type is known along with other parameters, then a typical Phase LockLoop (PLL) can be used to accomplish carrier synchronization. But in this case, since theorder of the modulation is not known, the PLL is modified to work without needing the orderof modulation. The synchronization process is divided into five stages: information removal,frequency estimation, frequency rectification, phase estimation, and phase rectification.

Figure 2.6 shows the constellation plots for 16QAM and 8PSK at different stages.

Figure 2.6: Constellation Plots [5]

2.3 Summary

This chapter covers each block of the UCS system in terms of its functionality, without gettinginto the theoretical analysis of how this function is performed. A system level overview isgiven in terms of understanding the different modules in the complete system.

The implementation discussed in the further chapters focuses on building a coarse classifierwhich forms an important initial stage of classification that can then be further extended for


synchronization with carrier phase and symbol timing.

Chapter 3

OFDM Signal Classification andSynchronization

This chapter presents work that the author did in collaboration with Ying Wang and QinqinChen to add OFDM to the VT UCS System. While time did not permit me to implementit on the Lyrtech SFF platform, we anticipate that work being completed in the future.

3.1 Overview

Orthogonal frequency division multiplexing (OFDM) has been demonstrated as an effectivetechnique to combat multipath fading in wireless channels. This technique has gained popu-larity in a number of applications including digital subscriber loops, WiFi and WiMAX. Thegreatest benefit of OFDM is that the modulation of closely-spaced “orthogonal sub-carriers”divides the available bandwidth into a collection of narrow sub-bands, which makes efficientuse of available spectrum, especially in a dynamic spectrum access (DSA) system [7]. AnOFDM signal can fit into different bandwidth channels by changing the symbol duration andnumber of subcarriers. A cognitive receiver incorporating a designed OFDM signal classifica-tion and synchronization enables use of cognitive wideband and broadband communication.

This chapter presents an OFDM signal classification and synchronization design for a cog-nitive radio system that extracts key features from a received OFDM signal to accomplishclassification, synchronization and demodulation, all without any prior knowledge. Thisdesign is combined with our previously developed narrowband signal classification and syn-chronization system [8]. The combined system supports a variety of modulations, includingdigital OFDM, MPSK, FSK, QAM as well as analog AM and FM. This system has been im-plemented and tested using an Anritsu signal analyzer, GNU Radio and a Universal SoftwareRadio Peripheral (USRP) platform.

11

Sujit Nair Chapter 3. OFDM Signal Classification and Synchronization 12

In our system, we are able to detect the signal by spectrum scanning, and identify the signalas an OFDM signal. Next we measure the length of a complete OFDM symbol and thelength of the cyclic prefix (CP) and then resolve the number of sub-carriers and the frameinformation. After that, we extract the symbol rate and carrier synchronization informationfor a sub-carrier. From this information, we are able to detect the modulation type used ineach subcarrier. The extracted information is used to reconfigure our cognitive radio receiverand enable demodulation.

The system presented in the chapter can be used for WiFi or WiMAX standard waveform. Itcan also be used to classify and synchronize other OFDM signals with varying parameters.Combined with other functions for narrow band signal classification and synchronization,the complete universal classifier and synchronizer system enables the cognition, automationand interoperability of a cognitive radio system.

3.2 Introduction

A Cognitive Radio (CR) can be defined as “a radio that senses and is aware of its operationalenvironment and can dynamically adapt to utilize radio resources in time, frequency andspace domains on a real time basis, accordingly to maintain connectivity with its peerswhile not interfering with licensed and other CRs” [9]. The environment includes both thechannel condition and the signal condition. If a cognitive radio is the one that initializes theconnection with its peers, then it needs to observe the channel condition to find availablespectrum and determine the transmission settings for optimal utilization of the spectrum andother resources. If a cognitive radio is the one that responds to a connection set up request,then, it should follow the initiated modulation types. For cognitive radio, especially for DSA,it is very common to change the modulation types and parameters settings according to thechanged channel conditions. A cognitive signal classification and synchronization systemwhich can automatically detect signal existence, center frequency and the bandwidth, identifymodulation type and extract the information needed for demodulation. It allows one end ofthe communication channel to change the spectrum and physical layer modulation settingsfreely without having to inform the receiver. With UCS, the receiver can automaticallypick up the signal and resume communication. In [8], we investigated narrowband signalclassification and synchronization algorithm and developed a narrowband cognitive receiverwhich can accommodate FM, AM, MPSK, and QAM. In this chapter, we will explore thewideband modulation world and develop a cognitive receiver which can detect, classify andsynchronize wideband signals. The combination of narrowband and wideband receiver willserve as the heart of a cognitive receiver.

Wideband transmission is becoming more and more important in cognitive radio research.Two of the most popular current technologies are code division multiple access (CDMA)and orthogonal frequency-division multiplexing (OFDM). Because the detection and de-modulation of CDMA signal without a spreading code is almost impossible, in this chapter,


we will focus on the OFDM signal detection, classification and synchronization design. Be-sides, OFDM signal’s spectrum efficiency and flexibility fits to DSA scheme and requirement.Having the OFDM signal classification and synchronization algorithm will also benefit DSAresearch.

In this chapter, we focus on the cognitive receiver aspect, which means that our work inthis section includes tracking and detecting OFDM signal, classifying it, and extracting allparameters needed for its demodulation. These parameters include the center frequency, theduration of an OFDM symbol, the length of CP, and the number of FFT points.

The rest of the chapter is organized as follows: in Section 3.3, we briefly introduce theOFDM application in DSA and the assumptions we make in our system design; In Section3.4, we give the detail description of the system. This section includes an overview ofthe system, the coarse carrier frequency estimation, symbol duration and cyclic prefix (CP)length measurement, subcarrier scheme detection, and fine carrier frequency synchronization.In Section 3.5, we give the both the simulation results and over the air (OTA) experimentperformance. Finally, in Section 3.6, the conclusion and future work will be discussed.

3.3 OFDM Application in DSA

A cognitive radio can dynamically identify currently unused portions of spectrum to operatein the available band. The signal bandwidth needs to be changed accordingly. For OFDMmodulation, there are two schemes of changing OFDM signal length [10]. One is to turnoff certain subcarriers, which is also the scheme applied in Orthogonal Frequency-DivisionMultiple Access (OFDMA). The other is to reduce the subcarrier spacing and width whicheffectively fits the signal spectrum into the varying bandwidth while keeping the number ofsubcarriers constant. Both of them have the same effect regarding the bandwidth occupationand data throughput. For example, in Figure 3.1, if the available bandwidth is decreasedas 3/5 of the original bandwidth as show in Figure 3.1a, then, we can either using scheme1 as in Figure 3.1b, or scheme 2 as in Figure 3.1c. We adopt the second scheme becausein this case we don’t need to detect the number of the sub-carriers. We assume that thetransmitter side of cognitive radio understands and applies scheme 2 as the strategy.

3.4 System Description

3.4.1 System Overview

Figure 3.2 shows an overview of our system. The system can be seen as three main parts: Adown conversion block is used to down convert the signal to the IF band. The Classificationblock is used to classify the signal, get a complete OFDM symbol and measure the length


Figure 3.1: Two schemes for changing the bandwidth of an OFDM signal

Figure 3.2: System Overview

of CP. The Synchronization block processes data based on the complete OFDM symbol. In


the synchronization block, we estimate and compensate for the frequency offset, adjust thesymbol timing, and analyze the subcarrier modulation type and settings. The output ofthe whole system will be several key parameters: accurate carrier frequency, OFDM symbolduration, length of CP, number of points for FFT, and modulation type of a subcarrier.

3.4.2 Detection of OFDM signal and coarse carrier frequency es-timation

Our first step is to scan the spectrum for the signal, and if the signal is present, to detect andclassify it. For identifying the signal as OFDM, we correlate the incoming signal with itself.OTA experiments for MPSK, analog and OFDM signals are shown in Figure 3.3. As shownfrom this figure, the correlated output is different in the case of narrowband modulationand wideband modulation. This difference is due to the cyclic prefix present in the OFDMsignal, which gives us multiple peaks as opposed to a single peak in narrowband modulation.

Figure 3.3: Self Correlation to detect OFDM


Figure 3.4 shows the power spectral density of an OFDM signal. After we detect andidentify the OFDM signal, the center frequency and bandwidth is estimated using the methoddescribed in [8].

Figure 3.4: PSD of an OFDM signal

3.4.3 Estimation of Symbol length and CP length

For extracting the information from the incoming signal, it is necessary to separate thesymbol from the cyclic prefix. We remove the cyclic prefix and find the length of the actualsymbol by correlating the incoming signal with itself. From Figure 3.5, we observe that theplot has three distinct peaks. The two smaller peaks are due to the presence of the cyclicprefix. So the length of the actual symbol excluding the cyclic prefix is the difference betweenthe highest peak and the smaller peak. Let the number of the samples between these twopeaks be nrx. If the sampling rate at the receiver is set as Rx samples per second, then theuseful symbol length is nrx/Rx .We use this useful symbol length for carrier synchronizationand symbol timing extraction.


Figure 3.5: OFDM signal self correction

Figure 3.6: Estimation of CP length

For finding the CP length we first flip one useful symbol and convolve it with the rest of the


OFDM symbol preceding it as shown in Figure 3.6 As is evident from the Figure 3.6, theCP of the useful symbol will overlap with its copy in the rest of the OFDM symbol. Thiswill result in a peak as shown in Figure 3.7 and this is the length of the CP.

Figure 3.7: Convolution Plot

We get an OFDM symbol excluding the cyclic prefix. This OFDM symbol vector is called Vrx.In the next section, when we use an OFDM symbol for carrier synchronization and symboltiming, it is necessary to have integer numbers of samples per symbol. The symbol hererefers to the MPSK signal that outputted after the FFT and parallel-to-serial conversion.To meet this requirement, we resample the OFDM symbol vector Vrx.

Figure 3.8 shows how the serial-to-parallel (S/P) processing at the transmitter side. ttx issymbol duration before S/P, ttx = 1

Rt, and Rt is the symbol rate at the transmitter side. Fs

is the number of subcarriers, which is also the number points for iFFT and FFT. Thus, theOFDM symbol duration is ttx.Fs.

The OFDM symbol length at the transmitter side is the same as the OFDM symbol lengthas the receiver side. Thus, we have:

nrx

Rx

=Fs

Rt


Figure 3.8: Serial to Parallel processing of OFDM in transmitter side

nrx

Rxis determined by the value of Rx and Rt , and cannot be guaranteed to be an integer.

Thus, we resample vector Vrx and the number of Vrx becomes round nrx/Fs after the re-sampling. Samples per symbol of Vrx after the FFT is round(nrx/Fs). The new vector afterresampling is called Vresample.

3.4.4 Carrier Frequency Synchronization

The aforementioned processing is in the IF band and there still exists a frequency offsetfrom the coarse frequency estimation. For OFDM signal, the frequency offset has a differentinfluence to the demodulation performance compared to a narrow band signal. In Figure3.9, the effects of an OFDM signal and the effect of an MPSK signal are compared.

In Figure 3.9, the comparison is based on the assumption that the symbol timing is correct.The effect of a frequency offset is to blur the OFDM signal constellation points, and theeffect of a frequency offset on the MPSK signal is to change the angle while keeping theamplitude constant. The reason for this is because the frequency offset becomes a timingdelay after the FFT at the receiver side. This delay will leads to an incorrect symbol timing,which will blur the signal constellation. This also gives a measurement of when the frequencyoffset estimation is more accurate. The searching algorithm for frequency offset is designedas follows. The step size of the frequency offset is defined as ∆f, the range of the frequencyoffset estimated is defined as frange. As we search from 0 to frange using step size ∆f thefrequency offset is compensated and the variance of the amplitude for the constellation pointschanges. The minimal variance corresponds to the carrier frequency offset.


Figure 3.9: Comparison between the effect of frequency offset on OFDM signal and QPSKsignal

3.4.5 Experiment and Simulation Results

As we mentioned in system overview, the purpose of our system is to automatically detectthe existence of the OFDM signal and extracting the parameters so that the signal can bedemodulated without prior information from the transmitter side. In this section, we aregoing to give an example and the results, which are the outputted parameters.


Table 3.1: Parameter Settings

Transmitter Settings Receiver Classification Result

Center Frequency = 450000018Hz;

Center Frequency = 450000000Hz;

Symbol Rate = 100 K; Symbol Rate = 100 K;

Number of FFT points = 4096(known by both transmitter andreceiver);

CP length = 1/4 OFDM symbolduration;

CP length = 1/4 OFDM symbolduration;

Subcarriers occupied = 1706(known by both transmitter andreceiver);

SNR = 10dB

In Table 3.1, we give the parameters setting at the transmitter side in the second columnand give the output of our system in the third column.

Regarding the occupied subcarriers, the number doesn’t influence our classification and syn-chronization performance. In Figure 3.10, we show the final constellation plots with differentnumber of occupied subcarriers.


Figure 3.10: Constellation plots with Occupied Subcarriers

3.4.6 Conclusion

In this chapter, we put forward an OFDM classification and synchronization system for cogni-tive radio systems. The proposed scheme can successfully detect the presence of an OFDMsignal and then extract all the parameters necessary for demodulation of an OFDM sig-nal without any prior knowledge of the transmitter. This classification and synchronizationsystem when integrated with the narrowband UCS system will serve as a comprehensive cog-nitive receiver capable of detecting, classifying, and demodulating single carrier and OFDMsignals.

Chapter 4

Lyrtech Small Form Factor SoftwareDefined Radio

4.1 Introduction

A software defined radio (SDR) is a radio that can accommodate a significant range of RFbands and air interface modes through software [11]. In short, SDRs try to push the signalprocessing functions from analog circuits to the digital domain. Signal processing tasks likefiltering, mixing, modulation and demodulation can be handled by the computers.

One of the most popular SDR platforms is the Universal Software Radio Peripheral (USRP),which has a programmable RF front end, but all the signal processing is handled by the com-puter. GNU Radio is a free software development toolkit that provides the signal processingruntime and processing blocks to implement software radios using readily-available, low-costexternal RF hardware and commodity processors. The GNU radio homepage is availableat [12]. The UCS system has already been implemented using the USRP as an RF front endwith the algorithm running on the host computer. For the sake of reference, a photograph(Figure 4.1) of the Public Safety Cognitive Radio (PSCR) is provided which works on asimilar platform.

Having a form factor like the USRP and a laptop computer makes it impracticable to testUCS in field situations. Also its size and weight (shown in Figure 4.1) also makes it extremelydifficult to deploy the technology in military and public safety applications. In the USRP,all the signal processing functions are pushed to the General Purpose Processor (GPP) onthe laptop computer whereas the USRP only acts as an RF front end. This transfer of databetween the computer and the USRP incurs delays which hinders its use in modern highcapacity communication systems [13]. Also the GPP in a laptop computer is not tailoredfor SDR functions.

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Sujit Nair Chapter 4. Lyrtech SFF SDR 24

Figure 4.1: Second Generation Prototype Public Safety Cognitive Radio

The SDR community is realizing that there is no specific hardware device that addresses allthe computing issues, hence the trend is shifting to more hybrid embedded platforms thatoffer a variety of hardware devices like Field Programmable Gate Arrays (FPGAs), DigitalSignal Processors (DSPs) and GPPs. One such platform is the Lyrtech Small Form Factor(SFF) SDR, which has a DSP, FPGA and GPP on board that is integrated to an RF frontend [14].

4.2 Platform Overview

Some of the disadvantages mentioned in the overview can be overcome by using a smallform factor hybrid platform (shown in Figure 4.6), in which we can divide the tasks be-


tween the various hardware components to suit our application as well as provide ease ofimplementation.

The Lyrtech SFF SDR is designed to be used to in the development of software definedradio applications. By separating the baseband, IF and RF from one another as distinctmodules (rather than maintaining a single fixed architecture), developers can extend theirradio development capabilities and optimize costs and power consumption [15]. This givesthe designer enormous flexibility to implement an application and be able to modify itdepending on the needs of the changing wireless standards.

Figure 4.2: Lyrtech SFF SDR Board [14]

The SFF SDR is shipped with two board support packages Board Software Development Kit(BSDK) and the Model-Based Development Kit (MBDK). BSDK give users the possibilityto quickly become fully functional developing C/C++ or assembly code for the DSP or HDLcode for the FPGA through an understanding of all SFF SDR boards major interfaces likethe video processing subsystem (VPSS), the audio codec, the data conversion or RF modules.The primary goal of the MBDK is to give access to Lyrtech development board interfacesfrom within the MATLAB and Simulink model-based design environment. By targeting theDSP and FPGA with DSPLink and FPGALink, respectively, users can deploy and validatealgorithms on the hardware more rapidly using these powerful software tools [14].

Furthermore, the SDR development platform includes a unique power measurement API.This API measures the power consumption of the FPGA, DSP and ARM, and reports real-


time power data. the developer can experiment with different system partitioning betweenthe FPGA and DSP to obtain an optimal power/performance balance [15]]. Here it isimportant to note the developer can take advantage of two main design approaches to pro-gramming the board C/Verilog versus MBDK. A variety of factors influenced the decisionof choosing the correct design approach based on our application and resource constraints.We use a combination of these two design approaches for development on the board and thisis explained in detail in the next chapter.

Figure 4.3: Functional Blocks in the SFF SDR [14]

The SFF SDR is divided into three main modules as shown in the schematic block diagrambelow (Figure 4.3)

• Digital Processing Module

• Data Conversion Module

• RF Module


The data-conversion module includes two ADS5500 ADCs, offering 14-bit performance at125 Msps, and one DAC5687, a 16-bit dualchannel DAC with 500 Msps. The standard RFmodule included in the kit covers from 360 MHz to 960 MHz with a selectable 5 MHz or20 MHz bandwidth, supporting a wide range of applications. The platform also uses TIsMSP430 ultralow-power MCU and power management technology.

Each of these modules is explained is more detail in the following sections.

4.2.1 Digital Processing Module

This module is equipped with a Virtex-4 SX35 FPGA from Xilinx and DM6446 DSP SoCfrom Texas Instruments. The DM6446 contains both, a high-performance TI TMS320CC64xDSP processor and an ARM9 general purpose processor (GPP), as well as a full set ofperipherals including serial ports, USB and Ethernet connections, and DDR2 and NAND-flash.

Figure 4.4: Digital Processing Module Block Diagram [16]


Since samples from the data conversion module first come to the FPGA and then to theDSP, we can take advantage of the speed and parallelism offered by the FPGA to performIF processing. The SX family FPGA is optimized for performing digital signal processingapplications and contains dedicated multipliers to speed up calculations. After the IF pro-cessing is done in the FPGA, the samples can be passed to the DSP. The ARM9 can beused for control functions and scheduling, whereas the C64x DSP can be used for complexcalculations.

4.2.2 Data Conversion Module

The data conversion module is equipped with a DAC 5687 dual channel digital to analogconverter to output processed signals. The data conversion module is also equipped withtwo ADS5500 analog-to-digital converters used to convert analog signals from the two analoginput connectors into digital signals for processing. The ADC allows for sampling rates upto 125MSPS at 14 bit resolution.

Figure 4.5: Data Conversion Module Block Diagram [14]

The PLL provides the clock distribution for the FPGA, the ADC and the DAC. The FPGA


is a Virtex-4 LX series used to control the DAC, the two ADCs, and data acquisition. Ituses the data conversion module expansion connector to interface with the digital processingmodule. The FPGA cannot be targeted with a custom bitstream.

4.2.3 RF Module

The RF module is composed of an RX section a three-stage superheterodyne receiver witha final IF frequency of 30 MHz and a selectable bandwidths of 5 or 20 MHz depending onthe application. The TX section of the RF module is a 2-band (262438 MHz, 523876 MHz)quadrature mixer that uses a divided-by-2 prescaler for the lower-band frequencies. Thereare three local oscillators used in the receiver stages to bring the RF RX signal to IF so thatit can be processed by the data conversion module. The frequency mixers are used to mixthe signals from the local oscillators with the received signals to bring them to the desiredIF.

Figure 4.6: Detailed RF Module Block Diagram [14]

The local oscillator of the transmitter is composed of a TRF3750 PLL synthesizer, a VCO,and a “divide-by-2” prescaler that can be activated or deactivated, depending on the desiredfrequency. The quadrature modulator is a Texas Instruments TRF3701 used to produce asingle-sideband TX output, converting a low-IF signal (less than 65 MHz because of thelow-pass filter at input) to RF.


4.2.4 FPGA-DSP Data Exchange

The video processing subsystem (VPSS) on the digital processing module of the SFF SDREVM/DP is used to transfer data between the FPGA and the DSP. The block diagram ofthe VPSS connection between the FPGA and the DSP is shown in Figure 4.7.

Figure 4.7: VPSS connection between the Virtex-4 and the TI DM6446 SoC [14]

The VPSS is composed of the video processing front end (VPFE) and the video processingback end (VPBE). The VPFE is used as an input interface to the DSP and the VPBEas an output interface from the DSP. The vertical and horizontal synchronization signals(Vsync and Hsync signals, respectively) are used as the main synchronization signals. Tobetter understand the interface, the function block parameters are shown in Figure 4.8 andFigure 4.9.

Lyrtech offers a generic VPSS block that can be configured as both VPFE and VPBEdepending on the parameters used. Both VPBE and VPFE configurations are shown.

VPBE block is used in the FPGA model when data is to be sent to the DSP and the VPFE isused in the DSP model when data is to be read from the FPGA. In simple terms, VPBE actsas the transmitter block which transmits information from the FPGA whereas the VPFEacts as the receiver block which receives this information in the DSP. The sample rate ofboth these blocks should be the same, since data should be read at the same rate at whichit is received for the transmitter and receiver block to be synchronized.


Figure 4.8: VPSS configured as VPBE (Direction = Rx) [14]

Figure 4.9: VPSS configured as VPFE (Direction = Tx) [14]

4.3 Summary

The SFF SDR provides a flexible and portable platform especially in the military and publicsafety applications where handset-like form factor can be a huge advantage. The high ab-


straction level model-based approach is also essential for realizing and prototyping cognitiveradio applications.

Also, since this board is a collaborative effort by Texas Instruments, Xilinx, Lyrtech and ahost of other vendors, developers can take advantage of a number of libraries and IP coresthat are available to further accelerate the design process and drastically reduce developmentcycle time.

Chapter 5

Software

5.1 Overview

The various hardware components in the Lyrtech SFF SDR are provided by different vendors(like Texas Instruments, Xilinx) and then put together in an integrated software definedradio platform. The FPGA, DSP and GPP onboard all require different software tools fordevelopment/building applications. The development tool chain for building applicationson the Lyrtech is complex and requires a number of Integrated Development Environments(Code Composer Studio, Xilinx ISE and Lyrtech software) to be integrated into the Lyrtechtool chain, and this proved to be a huge challenge at the beginning.

This chapter discusses the software development techniques used to program the DSP andthe FPGA on-board the Lyrtech SFF SDR. The chapter begins with a overview of the ModelBased Design Kit recommended by Lyrtech. After using this tool chain, some lessons werelearned and modifications were made to better suit our application. These are discussed inthe next section.

5.2 Model Based Design Approach

The Lyrtech Model Based Design Kit (MBDK) can be used in a Matlab/Simulink environ-ment to rapidly deploy and validate algorithms on actual hardware. A brief description ofMBDK is provided in this section; more details can be found in the Lyrtech documenta-tion [17].

The Figure 5.1 illustrates the MBDK DSP and FPGA code generation flows [17].

The Virtex-4 FPGA on the Lyrtech SFF SDR is targeted through FPGALink and the DSP istargeted through DSPLink. DSPLink refers globally to Lyrtech blocksets and blocks used in

33

Sujit Nair Chapter 5. Software 34

Figure 5.1: Lyrtech Model Based Design Kit for Rapid Prototyping and deployment [17]

conjunction with MATLAB, Simulink, and Real-Time Workshop to generate code that runson Lyrtech platforms that include a DSP. FPGALink refers globally to Lyrtech blocksetsand blocks used in conjunction with MATLAB, Simulink, and System Generator for DSP togenerate HDL code for Lyrtech platforms that include an FPGA.


5.2.1 FPGA Software Development

FPGALink Software Requirements:The following MathWorks software is necessary to use FPGALink :

• MATLAB

• Simulink

• Signal Processing blockset

• Signal Processing toolbox

The following Xilinx software is necessary to use FPGALink.

• ISE Foundation

• System Generator for DSP

FPGALink allows us to use MATLAB, Simulink, and System Generator for DSP to generateHDL code for the FPGA of an SFF SDR Development Platform within a Simulink model.When we use FPGALink in parallel with Xilinx blocksets, we can automatically generateHDL code from a variety of blocks. Actually, FPGALink wraps HDL code generated bySystem Generator for DSP and the HDL logic to communicate with the SFF SDR Devel-opment Platform. This way, FPGALink gives us full access to signals from the SFF SDRDevelopment Platform I/O and hardware modules, for example the conversion module orthe RF module.

FPGALink and System Generator for DSP allow us to quickly validate algorithms througha method called hardware-in-the-loop (HIL) co-simulation. This type of simulation is theequivalent of making the FPGA of the SFF SDR Development Platform think that it isoperating with real-world inputs and outputs, in real time.

When we select the HIL co-simulation option, a block appears in the model at the end ofthe bitstream generation process allowing us to exchange data between the Simulink modeland the FPGA of the SFF SDR Development Platform.

5.2.2 DSP Software Development

DSPLink Software Requirements The following “The MathWorks” software is necessary touse DSPLink.

• MATLAB


• Simulink

• Real-Time Workshop

• Signal Processing toolbox

• Signal Processing blockset

• Fixed-point toolbox

• Simulink Fixed-point blockset

The following Texas Instruments software is necessary to use DSPLink.

• Code Composer Studio C6000

Through DSPLink, Matlab, Simulink, and Real-Time Workshop are used to generate ANSI Ccode for the DSP of the SFF SDR Development Platform within a Simulink model. DSPLinkis used in parallel with the Signal Processing blockset and toolbox and Real-Time Workshopfrom The MathWorks. With it, a user can automatically generate C code from a variety ofsignal processing blocks.

Basically, DSPLink allows access to the I/O of the board from within the Simulink environ-ment through a set of blocks that encapsulate functions to drivers i.e. through the use ofSimulink blocks we can control the various hardware accessible to the DSP. For example,when the VPBE and VPFE blocks are added to the DSPLink model (the block allows datatransfer between the DSP and the FPGA through the video processing subsystem buses),data is accessed from the FPGA in your Simulink environment, enabling The MathWorksblocks to implement processing on data from the DSP. As mentioned above, DSPLink gener-ates C code for the SFF SDR Development Platform DSP within the Simulink developmentenvironment. However, when we have successfully generated DSP programs representinga model, DSPLink also allows us to load the SFF SDR Development Platform DSP withthe programs, start their real-time run, and modify parameters on-the-fly or visualize thebehavior of our algorithm (with the help of Simulink scopes or display blocks).

Further, because most applications implemented on the SFF SDR Development Platformalso incorporate FPGA sections, making it necessary to transfer FPGA bitstreams, DSPLinkexternal mode communications allow us to load FPGA bitstreams at the same time as DSPprograms.

Figure 5.2 is a screenshot of the sample blocksets provided by DSPLink and FPGALink :

From Figure 5.2, some of the essential blocks that are frequently used in most designs are:

DSP Options - All Lyrtech-specific SFF SDR Development Platform options are accessiblefrom the DSP Options block. This block is essential to targeting the SFF SDR DP withDSPLink blocks.


Figure 5.2: SFF SDR Development Platform DSPLink library

CMD File Generator - The CMD File Generator block generates a command file uponcompilation.

Data Conversion Module - The Data Conversion Module block is used to configurethe data conversion module of the development platform.

RF Module - The RF Module block is used to configure the RF module of the platform.

VPBE -The VPBE block is used to send data from the FPGA to the DSP through theVPSS.

VPFE - The VPFE block is used to send data from the DSP to the FPGA.

In addition to these tools, we need to use Matlab, Simulink and System Generator for DSPto generate HDL code for the FPGA of the SFF SDR. Similarly we need to use MATLAB,SIMULINK and Real Time Workshop (RTW) to generate ANSI C code to target the DSP.So a substantial amount of time was spent in getting this intricate tool chain to work. Therewere a lot of version issues with the software tools since only particular versions of these toolswere compatible with the board (e.g. Matlab R2007a). Our dependence on all the softwaretools (like Code Composer Studio, Lyrtech, Xilinx ISE, Matlab etc) gave us very little controlover our design, especially for the DSP which was of particular interest to us. DSP codegeneration was carried out using Simulink blocks and, and these blocks were converted toexecutable code by the Real Time Workshop. Our main objective behind simplifying thetool chain for development was to reduce these dependencies by making the DSP design


independent of the Real Time Workshop and using Matlab only as a simulation tool forfunctional verification of algorithms. We do not use the ARM in the DaVinci processor sincewe had licensing issues with the INTEGRITY software; hence we only use the DSP. Wealso noticed in some cases that the recommended model-based design methods for buildingapplications were not necessarily the most efficient. This is explained in the next section.

5.3 Observations

Initially for targetting the DSP, we used the Real Time Workshop to produce DSP ANSIC code from Simulink blocks. At first this looked like a very attractive option to targetthe DSP, since the same functional model which is simulated and tested in SIMULINKcan be downloaded to the DSP. Figure 5.3 illustrates the model based design approach forprogramming the DSP.

Figure 5.3: Development environments of the MathWorks and Texas Instruments’ plug-inboard [18]


The Simulink model-based design fails in certain scenarios where we need low level logiccontrol, and the logic cannot be encapsulated in a SIMULINK function block. The blockdiagram approach, although suited to high level system design, does not afford us the flexi-bility required to perform some customized data manipulation/management. Also we foundthat the auto generated code has lots of redundant lines creating unnecessary overhead whichmakes the technique unsuitable for entire system implementation. Also one of our targetswas to write code that is not compiler specific, which meant we needed control of exactlywhich functions are to be used and called.

5.4 Modifications

Certain modifications were made to the software development tool chain in order to makeit more efficient and more suited to building DSP and communication system applications.For instance, we used TI Code Composer to write our own code from scratch, rather thanusing the Real Time Workshop generated code. Also for DSP development, all simulationsare performed in TI Code Composer and all dependencies on MATLAB, SIMULINK andReal Time Workshop are removed as shown in Figure 5.4.

Figure 5.4: Modified Development Environment for the TI6446 on board the Lyrtech SFFSDR

This gives us greater control and flexibility in building applications to target the DSP sincethe development chain has fewer dependencies and is greatly simplified. The overall software


development tool chain is as shown in Figure 5.5.

Figure 5.5: Modified Software Tool Chain for the Lyrtech SFF SDR

We use a generic ARM 9 simulator to test our code functionalities which means the codecan run both on the DSP as well as on the ARM 9. For the FPGA, XILINX Sysgen andSimulink are used for functional simulation, and then the same design is used to generatethe bit stream.

5.5 Summary

Different approaches to programming the hardware onboard the Lyrtech SFF SDR are dis-cussed and their merits along with demerits are evaluated. While Model Based Design Kitapproach makes it easy for users to program at a higher level of abstraction, low level controlof functionalities is sacrificed. We take a middle ground by not using model based designapproach extensively, but using it for some system level design on the FPGA. For the DSP,we prefer using low level C code to make our implementation more transparent and efficient.

Chapter 6

Broadband RF Parallel Sensor Usingthe Lyrtech SFF SDR

6.1 Overview

FPGAs are increasingly being deployed in SDR for building real time digital processingsystems [19]. SDRs provide highly reconfigurable hardware platforms to implement nextgeneration and future wireless technology infrastructure. Nowadays SDRs perform advancedsignal processing functions like channel coding, equalization, channel estimation and multi-rate signal processing. While there is a plethora of silicon options available in the markettoday, FPGAs are a very attractive option to perform the signal processing functions basedon their performance, power consumption and rapid reconfigurability [20].

The high speed functionality of FPGAs makes them ideally suited for the real-time process-ing of Fast Fourier Transforms (FFTs) and Finite Impulse Response (FIRs) filters which weuse for building our application in the next section. They are also ideal for use as DigitalDown Converters (DDCs) and Digital Up Converters (DUCs). FPGA cores are availablefrom vendors like Xilinx and Altera for SDR applications such as wideband digital downconversion, FFT, and beamforming for phased array radar [21]. Generally SDR basebandprocessing platforms require both processors and FPGAs. In such hybrid embedded plat-forms, the FPGA implements the computationally intensive signal-processing data path andcontrol, minimizing the latency in the system whereas the processor handles most of thecontrol functions.

We take advantage of the Virtex-4 FPGA on the Lyrtech SFF SDR to implement a mul-tichannel sensor, which has a development environment provided by the System Generatorfor DSP tool and the parallelism offered by the FPGA. The rest of the chapter is orga-nized as follows. The first section discusses the motivation behind implementing a sensorin the FPGA. The following sections explain our implementation in greater detail and we

41

Sujit Nair Chapter 6. Broadband RF Parallel Sensor Using the Lyrtech SFF SDR 42

summarize our results in Section 6.6.

6.2 Motivation

The basic idea of the wideband energy detector is to divide the available system bandwidthinto smaller channels and process these subchannels in parallel on the FPGA.

Figure 6.1: System Bandwidth

Under ideal conditions there is no overlap between the different subchannels and the band-width of each subchannel is much less than the system bandwidth as shown in Figure 6.1and Figure 6.2.

Figure 6.2: Division of System bandwidth into N sub-channels


In addition, the subchannels in the wideband energy detector need not be contiguous, so onlysome subchannels of interest, not all of them, could be extracted and processed. The wide-band energy detector can be implemented in multiple ways, including sequential scanning ofthe subchannels which is widely used in most GPP or DSP based systems. For example, ina GPP based system, spectrum scanning is generally implemented using a sliding windowwhere only one sub-channel can be processed at any given time. The advantage of using anFPGA for spectrum sensing is that multiple streams of data can be processed simultane-ously on different parts of the FPGA. Since the FPGA allows parallel processing of a wideband signal, its computing speed is substantially faster than both GPPs and most DSPswhich sequentially process signals. In addition, the Lyrtech SFF-SDR platform integratesthe FPGA and the RF module on one platform; this further reduces the latency in movingsignals from the RF front end to the computing component.

6.3 Wideband Energy Detector Implementation

Figure 6.3: Carrier Sensing Block Diagram using Channelization

In our wideband signal detection method, as shown in Figure 6.3, IF signals from the data


conversion module are split into different subchannels based on the down-conversion centerfrequency. In Figure 6.3, F1, F2 are the center frequencies of the channels. Data in eachsubchannel is further decimated and downsampled from the ADC sampling rate to a lowersampling rate. Depending on the filter design, the bandwidth of each of the channels can alsobe controlled. Each block of signals contains 2048 sample points and goes through an FFToperation (using a XILINX FFT block). Using a programmable threshold for signal detec-tion, active signals can be located within the sampled spectrum, along with a correspondingintermediate frequency index.

6.4 Simulation Using System Generator and Simulink

The simulation of a single subchannel energy detector using System Generator and Simulinkis shown in Figure 6.4. In this simulation, Simulink system period, Ts=10-6 sec. In theinput section, we simulate five sine waves at frequencies 30 kHz, 70 kHz, 120 kHz, 200 kHz,and 300 kHz. A DSP based simulation section is also included for verifying the streamingFFT results obtained from the FPGA section. The results from the FPGA section and theDSP section are compared and the results are found to be consistent.

Figure 6.4: Simulation of a single Channel using SysGen and Simulink

In the FPGA section, the frequency spectrum of the data is calculated using the XilinxFFT V4.1 block and the points are stored in the FPGA block RAM and then assigned to


a MATLAB variable (Subsystem1). To test our method using the System Generator, wesimulated a wide band signal in MATLAB with the Power Spectrum Density (PSD) shownin Figure 6. We feed this wide band signal into the FPGA and run our broadband sensormethod. We set the subchannel bandwidth as 500 kHz and the programmable threshold as0.03. Our sensor is able to detect five signals at 30 kHz, 70 kHz, 120 kHz, 200 kHz, and 300kHz with PSD above this threshold, as shown in Figure 6.5.

Figure 6.5: A Hypothetical Signal Power Spectral Density (PSD)

In addition, we also run an energy detector with the same threshold in MATLAB on thiswide band signal. It produces the same results. When converting this simulation to actualsynthesizable code which can be implemented on the SFF SDR, we replace the generic blockswith platform specific blocks, as for example, one to feed signals to the FPGA from the RFmodule.

6.5 Sensor Result Collection by a Host Computer

The Lyrtech board operates as independent sensor; collecting RF data and performing thenecessary signal processing locally on the SFF board. In the previous simulation, we onlydetect the signals presence. In the final running sensor, it will also indicate each detect signalscenter frequency, bandwidth, and SNR. Overall, all detected signals center frequency, signalbandwidth, and signal SNR will be stored in a table, as shown in Table 6.1.

The sensor results can be used in many ways. For example, they can be conveyed into ahost GPP and be displayed. For the Lyrtech SFF SDR board to send information to the


Table 6.1: Table showing measured values on screen

Channel Center Frequency(MHz) Bandwidth(MHz) SNR(dB)1 462.5 1 152 475 0.5 143 . . . . . . . . .

host computer, Direct Memory Access will be used between the DSP on the board and thehost computer. The host computer relies on the SMSHELL functions sm set and sm getto transfer data from the DSP through the same memory space. To ensure that variablesfor sensor results are continuously assigned with the same memory addresses, the memorysegment of the DSPs parameter setting file, the CMD file, is modified. Three variables aremanually assigned to partition SDRAM in the form of pointers. The first variable is a flagfrom the DSP to the host computer, DSP-to-Host flag, indicating that the Lyrtech boardhas added new signal information and that the host computer should read this information.The second variable contains a table for detected signals center frequency, bandwidth, andSNR. The third variable is a flag from the host computer to the DSP, Host-to-DSP flag,indicating that it has finished reading updated sensor results.

6.6 Summary

Our goal to illustrate the basic structure of a spectrum sensor that takes advantage of theVirtex-4 FPGA and Xilinx IP cores, and to prove the feasibility (in terms of resources andmapping functionality into hardware) of a multichannel design on the FPGA. A number ofIP cores are available from XILINX to perform standard signal processing tasks like filtering,upconversion, downconversion etc which enhance productivity.

The design was implemented using ISE 9.2i and System Generator for DSP along withSimulink (Matlab R2007a). The ADC sampling rate was set at 80Msps. The utilizationdata is: 11010 logic slices (71%) and 123 multipliers (64%) (see Appendix A).

Chapter 7

Coarse Classifier Implementation

7.1 Overview

Previous chapters have talked about the motivation for implementing a signal classificationsystem and described the underlying hardware and software development tool chain. Thischapter gives an overall description of the coarse classifier, focusing on the implementationdetails. The SFF SDR platform has the flexibility to target the different functionalities eitheron the DSP or the FPGA, whichever is most suitable for the task. Dividing responsibilitiesbetween the FPGA and the DSP is a good system design practice, and a developmentconvenience.

This chapter begins with an examination of the features and requirements of the system.It then moves to the steps in the design process, simulation of the designed model andhardware implementation. Before getting into the specifics of the implementation, there is ashort discussion on fixed point and floating point representations, and design considerationsthat validate the use of one over the other.

7.2 Features and technical requirements

RF/IF

• 30MHz IF frequency

• Selectable RF frequency

• 2 MHz BW

47

Sujit Nair Chapter 7. Coarse Classifier Implementation 48

• ADC running at 80MSPS

FPGA Section

• DDS for frequency downconversion

• XILINX FIR IP core for designing filters

• Use of Matlabs FDATool to computer filter coefficients

DSP section

• Fixed Point/Floating Point

• Windowing

• FFT

• Classification

Data Transfer Bandwidths

• Data transfer from FPGA to DSP through VPSS port

• ADC (80MSPS) –> FPGA (2MSPS) –> DSP (2MSPS)

7.3 Fixed Point and Floating Point

One of the design objectives right at the outset was to test the classification algorithm usingboth fixed point and floating point representations. Since fixed point design is significantlymore complex than floating point, it is first important to understand the difference betweenthe two and the motivation for choosing one over the other or both as in our case. As theterms fixed point and floating point indicate the fundamental difference between the twotypes of DSPs is in their respective numerical representations of data. In case of floatingpoint numbers the processor has all the information about the number and does all themanipulation by itself without the programmer having to keep track of the exponent and themantissa. In contrast to this, for fixed point number calculations, it is left to the user to dealwith the exponent [21]. Power consumption is a critical factor in DSPs that are embeddedin devices like cell phones. Fixed point processors use less power than their floating pointcounterparts in general because math units tend to be less complex with fewer gates andtransistors than equivalent floating point systems [22]. The much greater computational


power offered by the floating point DSPs is a key reason for considering it in the design ofany system.

When floating point DSPs were first introduced, the greater number of pins required bythe wider data bus meant a larger die and larger package that resulted in a significant costpremium for the new floating-point devices. Therefore fixed point DSPs were favored in highvolume and low cost applications like digitized voice cards. An important factor that offsetsthe cost is the ease of programming floating point devices. Because of this, floating pointDSPs were used initially in low volume applications like radar, image recognition and otherareas [23].

Cost is no longer the deciding factor when choosing between fixed point and floating pointimplementations. Software development is one of the most vital aspects of any project and wefound that floating point libraries were more readily available than fixed point. Additionallywe havent used any TI libraries for our code development, which meant having to writemany signal processing and math functions in C. Writing code for floating point operationsis easier than writing code for fixed point applications, since we dont need to worry aboutdynamic range.

Choosing between a fixed point or a floating point design should be based on the applicationrange and precision requirement, budget of the project, space and speed requirements andpower consumption. In our case, the code developed had to run on processors with no FPU,and hence we made our design to work with fixed point. Although the C64x DSP is capableof handling floating point numbers, the developed code also runs on fixed point DSPs. Thereason behind implementing the application in fixed point is that it affords us the flexibilityto run our code on dedicated fixed point DSPs as well as general purpose processors that donot have a floating point unit (FPU). Our application was first developed in floating pointand then subsequently modified to accommodate fixed point representation. The floatingpoint results and plots served as a reference for the fixed point implementation.

7.4 Partitioning the Design

7.4.1 Overview

By design, the Lyrtech SFF SDRs Virtex-4 FPGA gets raw values from the A to D converter.Therefore the samples from the RF front end come to the FPGA before they can be passedto the DSP. Software and Intellectual Property (IP) have become more challenging thansupporting hardware platforms, and this can consume substantial development cycle time.This factor had a major influence on the design and was the primary reason why we chose todo IF processing in the FPGA. Xilinx IP cores used in conjunction with System Generatorfor DSP provide access to signal processing blocks like digital down-conversion, filtering anddown-sampling. The main task of the FPGA in our application is to perform IF signal


processing and feed IQ data to the DSP.

In general, it is more difficult to program FPGAs than DSPs, since in most cases FPGAdesigners have to perform low level circuit design. Also time for synthesizing an FPGA designis much longer than the corresponding time for a DSP design. By generating a bit streamthat does IF processing, we can essentially focus our development efforts on the DSP. Weno longer need to synthesize the FPGA design every time we start building an application,unless we need to change our base IF parameters like bandwidth of interest, quasi-basebandfrequency etc. This provides a simple and standardized interface for the overall system.

The design is partitioned between the DSP and the FPGA, and both parts are designed andtested separately using the overall top-down system level design flow and tools, as shown inFigure 7.1.

Figure 7.1: System Level Design Tools

All of the DSP simulation and implementation is done through Code Composer Studiowhereas the FPGA design part uses System Generator for DSP along with Matlab/Simulink.


Xilinx ISE is used to generate the bit stream that is downloaded to the Virtex-4 FPGA.

7.4.2 System Layout

The Virginia Tech UCS system currently runs on a laptop computer connected to the USRPboard. Since the USRP is just an RF front end, there is no need for any design partition,as all the signal processing and decision making functions are done on the GPP in thelaptop computer. Such a system is not very efficient since the GPP is burdened with all theprocessing even though it is not ideally suited to perform complex computations.

In contrast to this, in the SFF SDR we can divide tasks between the DSP and the FPGA.Each device can perform tasks based on their respective strengths and ease of programmingthrough the available software development tools. Traditionally algorithms that require fastand complex calculations but can be parallelized are best fit for the FPGA, while algo-rithms that require sequential analysis and decision making are usually implemented on theDSP [24].

Figure 7.2: Tasks implemented by FPGA

Figure 7.2 represents the tasks that are carried out by the FPGA. The design implementationdetails follow in the next section, but the overall objective is to pass IQ data to the DSP afterIF processing. Since all the calculations in the FPGA are done in fixed point, normalizingvalues is essential to avoid running into overflows and underflows. Also suitable bit precisionsare to be defined for the various nodes in the circuit. Bit precisions become especiallysignificant in our design in the filtering block where the length of the filter is in the order ofa few hundreds. The main challenge is that the output 16 bit data should not overflow orunderflow even after the input passes through the filter which would perform many multiply-add operations. Also, since the I and Q branches are symmetrical, we use the same filter forboth paths and pack the two 16 bit I and Q data into one 32 bit packet and send it to theDSP.


In our system the DSP mainly deals with all of the decision making. The tasks performedby the DSP are illustrated in Figure 7.3.

Figure 7.3: Tasks implemented by DSP

In our design, the DSP performs classification of the incoming signal at different levels thatare marked as stage 1, stage 2 and stage 3. Single carrier classification is shown shaded inFigure 7.3, and stages 2 and 3 of classification are performed only for single carrier signals.

Also our framework and development support both fixed point and floating point representa-tions. Initial development and testing of the algorithm was done in floating point. The plotsand the results obtained for floating point were confirmed. Then the fixed point system wasdesigned and its correctness was determined in the context of ideal floating point realization.


7.4.3 FPGA Model

The FPGA model implements frequency translation between the IF and baseband frequency.The sampling rate from the A to D converter is 80 MSPS and the data fed to the DSP isat 2 MSPS. The RF section brings down the frequency to 30 MHz IF, which is given tothe FPGA. The data coming from the A to D converter is first downconverted to baseband,downsampled and then filtered. These blocks are shown in Figure 7.4 below.

Figure 7.4: Screenshot showing IF filtering after downconversion

The digital downconversion block is shown in more detail in Figure 7.5.

Figure 7.5: Digital Down Conversion Block


The local oscillator is implemented using a Xilinx direct digital synthesizer (DDS) core to ob-tain a sine and cosine wave as shown in Figure 7.5. The frequency is software programmableand is set as 30MHz. The overall sample rate conversion ratio is 40. This is done by takingadvantage of the highly optimized Xilinx blockset library like the FIR filter block and theDDS blocks.

A very important aspect of implementing the IF section is the filters used to isolate the signalof interest and downsample it in baseband. These filter structures are complex, divided intomultiple stages and they operate at different sampling rates. For designing such filters, weuse the FDATool in Matlab and export the coefficients from Matlab to our design. Figure 7.6shows the filter design with its parameters.

Figure 7.6: FDATool to calculate filter coefficients

After the converting the signal to baseband, the data is divided into in-phase and quadraturecomponents (IQ representation). This IQ data needs to be passed to the DSP for further


processing. Since the data transfer bus to the DSP is only 32 bits wide, the I-componentand the Q-component each can be 16 bits wide. This 32 bit packed IQ data is sent over theVPSS port to the DSP.

7.4.4 DSP Section

The data from the FPGA is in the form of a packed 32 bit IQ data stream. This datais unpacked as 16 bits I data and 16 bits of Q data in the DSP before doing any signalprocessing on it.

The DSP performs the spectrum sensing and classification algorithms. The data from theFPGA is transferred through the VPSS port to the DSP. The first step in the classificationalgorithm is spectrum sensing to determine whether a signal is present for classification.Spectrum sensing is performed by calculating the PSD of the signal. PSD is calculated byusing FFT and windowing. FFT methods are prone to leakage when a non periodic signalis at the input, and to correct this problem windowing is applied. Figure 7.7below showsthe PSD plot of BPSK signal transmitted via the USRP.

Figure 7.7: PSD of a BPSK signal - Fixed Point

The PSD information is used to calculate the center frequency of the transmitted signalalong with detecting the presence of a signal.

Once we detect whether energy is present, the first level of classification is whether thetransmitted signal is a single carrier signal or a multiple carrier signal. For differentiatingbetween the two, autocorrelation operation is performed the transmitted signal. The figuresbelow (Figure 7.8, Figure 7.9, Figure 7.10) show the difference between the autocorrelationplots for a single carrier signal and an OFDM signal.

From Figure 7.8 and Figure 7.10, we observe that the autocorrelation plots for OFDM signalsshow multiple peaks as compared to a single peak for a single carrier signal (Figure 7.9).Chapter 3 has details of OFDM classification and synchronization.


Figure 7.8: OFDM Autocorrelation Plot - Fixed Point

Figure 7.9: BPSK Autocorrelation Plot - Fixed Point

Single carrier signals have more levels of classifications. For classifying a signal as phasecontinuous or phase discontinuous, we need to analyze the unwrapped phase characteristics.Shown below is the unwrapped phase plot for a BPSK signal and an FM signal.

The number of phase jumps in a phase discontinuous signal like BPSK is much more thanthe number of phase jumps in a phase continuous signal like FM. For example, for a BPSK


Figure 7.10: OFDM Autocorrelation Plot - Floating Point

signal with SNR 20dB, the number of phase jumps was 29 compared to 0 for FM for every256 samples processed. This property is used to distinguish phase continuous and phasediscontinuous signals.

Figure 7.11: Phase Unwrap Plot for BPSK – Fixed Point


Figure 7.12: Phase Unwrap Plot for BPSK – Floating Point

Figure 7.13: Phase Unwrap Plot for FM – Fixed Point

7.5 Performance on Hardware

After testing the code on the ARM9 simulator in Code Composer studio, we download theDSP executable file on the Lyrtech SFF SDR. The Lyrtech specific startup functions andboard initialization functions are called and the parameters are set. The base RF frequency


is set at 462 MHz and the selectable bandwidth is set at 5 MHz. For testing purposes,we transmit waveforms using GNU radio and USRP. The percentages shown in Table 7.1represent the number of correct classifications per 100 trials.

Table 7.1: Performance Chart

ModulationSNR = 20db

Spectrum Sensing Phase Continuous Phase Discontinuous AM FMFM 100% 100% 0% 0% 100%

BPSK 100% 0% 100% 0% 0%QPSK 100% 0% 100% 0% 0%

AM 100% 100% 0% 100% 0%

ModulationSNR = 15db


BPSK 100% 0% 100% 0% 0%QPSK 100% 0% 100% 0% 0%

AM 100% 100% 0% 100% 0%

ModulationSNR = 8db


BPSK 100% 9% 91% 0% 9%QPSK 100% 9% 91% 0% 9%

AM 100% 100% 0% 100% 0%

The performance is measured at 3 different SNR values (20 dB, 15dB and 8dB) with 100realizations of each modulation type and summarized in Table 7.1. Since the USRP doesnot have a very reliable RF front end, the SNR values are not very accurate. The tableabove therefore uses approximate SNR values measured using the GNU Radio and USRP asa transmitter, and then using the ANRITSU spectrum analyzer to measure the SNR of thetransmitted signal. We observe from the table that classification results are accurate (¿90%)of tests with SNRs as low as 8dB. Also we havent used OFDM for OTA testing, since wecurrently do not have an OFDM transmitter.

Chapter 8

Results and Conclusions

It seems appropriate to revisit the objectives set out in Chapter 1 for this thesis. The mainobjective of this thesis was to implement the coarse classifier on the Lyrtech SFF SDR. Thesingle most important metric for this implementation is whether system actually works. Aworking system prototype was demonstrated at the Wireless@VT symposium in June 2009.

The other contributions of this thesis work are:

1. Extension of the UCS system to classify OFDM signalsThe first prototype of the UCS system was designed only to classify single carriermodulation schemes. However in recent years, new wireless technologies have emerged.Wireless industry standards have shown great interest in orthogonal frequency divisionmultiplexing (OFDM) systems due to the efficiency of OFDM in fading channels with-out the need for equalizers. Also since some OFDM schemes allow subcarrier powercontrol, such schemes have found applications in dynamic spectrum access. Combinedwith other functions for narrow band signal classification and synchronization, thecomplete universal classifier and synchronizer system fully enables key cognitive radiofunctionality, including automation, cognition, and interoperation.

2. FPGA-based multi-channel Spectrum SensorAn FPGA based broadband multichannel sensor has been designed and implemented.This was an important step in the roadmap to implementing a coarse classifier onthe Lyrtech SFF SDR. The FPGA is used to perform complex signal processing taskslike filtering, downconversion and FFT. Additionally the parallelism of the FPGA isexploited in this application where we process two streams of data in parallel.

A working prototype of this sensor was shown in the DARPA IPR in October 2008 atBoston.

3. Software development tool chain for Hybrid platformsDifferent approaches to programming the hardware on board the SFF SDR have been

60

Sujit Nair Chapter 8. Conclusions 61

discussed and analyzed. Model Based Design allows us to program the hardware usinga high level of abstraction, but in the process some low level control of functionalitiesis lost. Also some of the code generated by these tools are not efficient and contain toomuch overhead. We use the Model Based Design methodology only for generating thebit stream for the Xilinx FPGA, since we use cores in the design that are optimizedfor Xilinx FPGAs. We use conventional C language coding for programming DSPs.

4. Flexible Implementation and FrameworkOur system implementation does not use any vendor or compiler specific libraries andis programmed using basic C language. The system works for both fixed point andfloating point representations. This means that the code can run on most DSPs andGPPs, even ones which do not have a floating point unit (FPU).

The framework developed for designing this system along with Lyrtech board specificsystem calls, can be used in other applications where the final goal is to target theSFF SDR. Also the DSP code can be reused for developing applications on any otherboard that uses a DSP or a GPP.

Appendix A

FPGA Resource Log

A.1 Overview

This appendix shows the FPGA resource utilization after synthesizing the design for thefollowing cases:

1. Single Channel Sensor

2. Two Channel Sensor

3. Three Channel Sensor

The operations which take up maximum resources are the FFT operation and filtering. Aswe keep increasing the number of data paths i.e. number of channels in the FPGA, the areaoccupied by the design on the FPGA will increase since each channel needs a dedicated filterand FFT block. In order to fit three channels, the filters in each data path need to optimizedso we can reduce the number of taps of the filter and the number of bits for each coefficient.For example we sacrifice stop-band attenuation and reduce it to -40dB for a three channelsensor from -80dB for a single channel sensor. The next section is taken from the log filegenerated by the place and route tools when the design is synthesized. It basically givesan idea on the resource consumption increase, as we increase the number of channels in ourdesign.

A.2 Resource Summary

A.2.1 Resource utilization of single channel sensor

Device Utilization Summary:

62

Sujit Nair Appendix A. FPGA Resource Log 63

Number of BUFGs 7 out of 32 21%

Number of BUFGCTRLs 2 out of 32 6%

Number of DCM_ADVs 3 out of 8 37%

Number of DSP48s 123 out of 192 64%

Number of ILOGICs 63 out of 448 14%

Number of External IOBs 202 out of 448 45%

Number of LOCed IOBs 202 out of 202 100%

Number of External IOBMs 12 out of 168 7%

Number of LOCed IOBMs 12 out of 12 100%

Number of External IOBSs 12 out of 168 7%

Number of LOCed IOBSs 12 out of 12 100%

Number of OLOGICs 88 out of 448 19%

Number of RAMB16s 16 out of 192 8%

Number of Slices 10656 out of 15360 69%

Number of SLICEMs 3278 out of 7680 42%

A.2.2 Resource utilization of two channel sensor

















A.2.3 Resource utilization of three channel sensor



Sujit Nair Appendix A. FPGA Resource Log 64















Appendix B

Source Code

B.1 ucsphase1.c

#include "dsa_signal_processing.h"

#include "lyrtech_init.h"

#include <math.h>

#include "ucs_phase1.h"

void varianceelements(genericType_t *array, int size, genericType_t *variance,

genericType_t *avg)

{

int i;

float sum = 0.0, sum2 = 0.0, tavg;

for (i = 0;i < size; i++)

sum += array[i];

tavg = sum / (float)size;

for (i = 0;i < size; i++)

sum2 = (tavg - array[i]) * (tavg - array[i]);

*avg = tavg;

*variance = sum2/ (float)(size-1);

}

void sumelements(genericType_t *x, int size, genericType_t *sumarray)

65

Sujit Nair Appendix B. Source Code 66

{

int i;

*sumarray = 0.0;

for (i = 0; i < size; i++){

*sumarray = *sumarray + *x;

x++;

}

}

void countjumps(genericType_t *phasedifference,

genericType_t phase_diff_th, int size, genericType_t *reshaped_phasedifference)

{

int i;

for (i = 0; i< size; i++){

if (fabs(*phasedifference) > phase_diff_th){

*reshaped_phasedifference = 1;

}

else

*reshaped_phasedifference = 0;

phasedifference++;

reshaped_phasedifference++;

}

}

void integratephase(genericType_t *p, genericType_t *cumsum,

genericType_t *unwrapphase)

{

int i;

*unwrapphase = *p;

p++;

unwrapphase++;

for (i = 0; i < SIZEOFIQDATA-1; i++){

*unwrapphase = *p + cumsum[i];

p++;

unwrapphase++;


}

}

void cumsum(genericType_t *x, int size, genericType_t *cumsum)

{

int i;

//initialize first cumsum element to first input

*cumsum = *x;

x++;

cumsum++;

//start adding cumulative sums

for (i = 0; i < (size-1);i++){

*cumsum = *(cumsum-1) + *x;

x++;

cumsum++;

}

}

void phasecorrections(genericType_t *dp, genericType_t *dps,

genericType_t *dp_corr)

{

int i;

for (i = 0; i < SIZEOFIQDATA - 1; i++){

*dp_corr = *dps - *dp;

dp++;

dps++;

dp_corr++;

}

if (fabs(*dp_corr) < PI){

*dp_corr = 0.0;

}

}

void diffadjascentelements(genericType_t *elements,

genericType_t *difference)

{


int i;

float largest = -50;


*difference = *(elements+1) - (*elements);

if ( (fabs(*difference) > largest) )

largest = *difference;

elements++;

difference++;

}

}

void diffadjascentelements_2(genericType_t *elements,

genericType_t *difference)

{

int i;

float largest = -50;


GenericPoint_Sub(elements+1, elements, difference);

elements++;

difference++;

}

}

void modify_modfloating(genericType_t *out, genericType_t *x,

genericType_t *y)

{

if (*y == 0 )

*out = *x;

else if (*x == *y || *x == 0)

*out = 0;

else

*out = (*x) - floor((*x)/(*y))*(*y);

}

void eqphasevariation(genericType_t *dp, genericType_t *dps)

{

int i;

genericType_t temp1;




//*dps = fmod(*dp + PI, 2*PI) - PI;

temp1 = *dp + PI;

temp2 = 2*PI;

modify_modfloating(dps, &temp1, &temp2);

*dps = *dps - PI;

/*

if (*dps < 0.0){

*dps = *dps + 2*PI;

}

*/

if ((*dps == -PI) & (*dp > 0.0)){

*dps = PI;

}

dp++;

dps++;

}

}

void calculatephase(genericComplexType_t *iqdata,

genericType_t *phase_r)

{

int i;

genericType_t *realpart, *imagpart;

genericComplexType_t *iqdataTemp;

//double phaseTemp[512];

for (i = 0; i < SIZEOFIQDATA; i++) {

realpart = &(iqdata->real);

imagpart = &(iqdata->imag);

*phase_r = atan2(*realpart, *imagpart);

iqdata++;

phase_r++;

}

}


// basic phase calculation and phase unwrapping

void phaseCalcUnwrap(genericComplexType_t *src,

genericType_t *unwrapphase)

{

genericType_t phaseangle[SIZEOFIQDATA];

genericType_t diff[SIZEOFIQDATA - 1];

genericType_t dps[SIZEOFIQDATA - 1];

genericType_t dp_corr[SIZEOFIQDATA - 1];

genericType_t cumsumintegrate[SIZEOFIQDATA - 1];

genericType_t testmod;



int i;

// testmod = fmod(-6.08+PI, 2*PI) - PI;

// testmod = - floor((-6.08+PI)/(2*PI))*(2*PI) - PI;

temp1 = -6.08+PI;

temp2 = 2*PI;

modify_modfloating(&testmod, &temp1, &temp2);

testmod = testmod - PI;

calculatephase(src, phaseangle);

diffadjascentelements(phaseangle, diff);

eqphasevariation(diff, dps);

phasecorrections(diff, dps, dp_corr);

cumsum(dp_corr, SIZEOFIQDATA - 1, cumsumintegrate);

integratephase(phaseangle, cumsumintegrate, unwrapphase);

}

void PhaseJumpCounting(genericType_t *unwrapphase,

genericType_t *jumpcounts)

{

genericType_t phasediff[SIZEOFIQDATA - 1];

genericType_t reshaped_phasedifference[SIZEOFIQDATA];

//genericType_t phase_diff_th = PHASE_DIFF_TH;

genericType_t phase_diff_th = PHASE_DIFF_TH;

//int temp = 0;

//int i = 0;


// phase jump counting

diffadjascentelements_2(unwrapphase, phasediff);

//writeOutputBuffer(phasediff, 256, 1);

//writeOutputBuffer2(unwrapphase, 256, 1);

countjumps(phasediff, phase_diff_th, SIZEOFIQDATA,

reshaped_phasedifference);

sumelements(reshaped_phasedifference, SIZEOFIQDATA, jumpcounts);

}

void amFmClassification(genericComplexType_t *src, int size,

genericType_t *variance_iqdata)

{

genericType_t complex_mag[SIZEOFIQDATA];

genericType_t avg;

errorCodeEnum_t res = NO_MATH_ERROR;

// am fm classification

res = GenericPointComplex_MagnitudeSumSquared (src, complex_mag, size) | res;

varianceelements(complex_mag, SIZEOFIQDATA, variance_iqdata, &avg);

}

void ucsPhase1Main(genericComplexType_t *src, int size)

{

genericType_t jumpcounts;

genericType_t unwrapphase[SIZEOFIQDATA];

//genericType_t jmp_th = (SIZEOFIQDATA/200);

genericType_t jmp_th = JUMP_COUNT_TH;

int phasecontinuous = 0, phasediscontinuous = 0, phasecontinuous_am = 0,

phasecontinuous_fm = 0;

genericType_t variance_th = 0.005;

genericType_t variance_iqdata;

//int i = 0;

// double temp = 463.55;

phaseCalcUnwrap(src, unwrapphase);

PhaseJumpCounting(unwrapphase, &jumpcounts);

amFmClassification(src,

size,


&variance_iqdata);

//check if phasediscontinuities or phasecontinuous

//if phasecontinuous

//check am or fm

// #ifdef DEBUG

// *HostToDspFlag = jumpcounts;

// *HostToDspFlag = jmp_th;

// #endif

// main phase 1 function

//writeLyrtechHost(FREQUENCY , temp*10);

if (jumpcounts > jmp_th){

writeLyrtechHost(PHASEDISCONTINUOUS, 1);

writeLyrtechHost(PHASECONTINUOUS, 0);

writeLyrtechHost(PHASECONTINUOUS_AM, 0);

writeLyrtechHost(PHASECONTINUOUS_FM, 0);

//#ifdef DEBUG

// *HostToDspFlag = 16;

// #endif

}

else

{

phasediscontinuous = 0;

phasecontinuous = 1;

writeLyrtechHost(PHASEDISCONTINUOUS, 0);

writeLyrtechHost(PHASECONTINUOUS, 1);

#ifdef DEBUG

// *HostToDspFlag = variance_th;

#endif

if (variance_iqdata > variance_th){

//void writeLyrtechHost(int index, int value)

//phasecontinuous_am = 1;

//DataBufferLocal[0] = ((int *)1;

#ifdef DEBUG

*HostToDspFlag = 22;

#endif


//phasecontinuous_fm = 0;




}

else

{

//phasecontinuous_am = 0;



//phasecontinuous_fm = 1;



#ifdef DEBUG

*HostToDspFlag = 33;

#endif

}

}

}

B.2 ucsphase1.h

#include "dsa_signal_processing.h"

#include "lyrtech_init.h"

#include <math.h>

#ifndef _UCS_PHASE1_

#define _UCS_PHASE1_

#define SIZEOFIQDATA 256

#define PI 3.141593

//#define PHASE_DIFF_TH (2*PI/16) * 30

/* THESE THRESHOLD VALUES ARE SPECIFICALLY FOR THE LYRTECH

--------------------------- */

#define PHASE_DIFF_TH 2.9

#define JUMP_COUNT_TH 100

#define ENERGY_THRESHOLD 20

/*--------------------------- */

void phaseCalcUnwrap( genericComplexType_t *src, genericType_t *unwrapphase);

void PhaseJumpCounting(genericType_t *unwrapphase, genericType_t *jumpcounts);

void amFmClassification(genericComplexType_t *src, int size,


genericType_t *variance_iqdata);

void calculatephase(genericComplexType_t *iqdata, genericType_t *phase_r);

void eqphasevariation(genericType_t *dp, genericType_t *dps);

void diffadjascentelements(genericType_t *elements, genericType_t *difference);

void diffadjascentelements_2(genericType_t *elements, genericType_t *difference);

void phasecorrections(genericType_t *dp, genericType_t *dps,

genericType_t *dp_corr);

void cumsum(genericType_t *x, int size, genericType_t *cumsum);

void integratephase(genericType_t *p, genericType_t *cumsum,

genericType_t *unwrapphase);

void countjumps(genericType_t *phasedifference, genericType_t phase_diff_th,

int size, genericType_t *reshaped_phasedifference);

void sumelements(genericType_t *x, int size, genericType_t *sumarray);

void varianceelements(genericType_t *array, int size, genericType_t *variance,

genericType_t *avg);

void modify_modfloating(genericType_t *out, genericType_t *x, genericType_t *y);

void ucsPhase1Main(genericComplexType_t *src, int size);

#endif

Appendix C

Permission from Lyrtech

From: Jean-Benoit Larouche [mailto:[email protected]] On Behalf

Of Support

Sent: Tuesday, December 15, 2009 3:58 PM

To: Sujit Nair

Cc: Support

Subject: RE: Figures for Thesis

Hi Sir,

We agree to give you the possibility to use our figures for your thesis.

But in exchange, it would be great to have a copy of this thesis;

to see whats our clients are able to do with our products, if its possible.

Regards,

Technical Support Team

________________________________________

De : Sujit Nair [mailto:[email protected]]

Envoy : 15 dcembre 2009 13:06

: Support

Objet : Figures for Thesis

I would like to ask your permission to use some figures from the

SFF SDR EVM-DP Users guide document provided by Lyrtech with

the Lyrtech SFF SDR Platform for my thesis. These include block diagrams

of the data conversion module, RF module and the digital signal processing

module.

Sujit Nair

75

Bibliography

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[2] O. Dobre, A. Abdi, Y. Bar-Ness, and W. Su, “Survey of automatic modulation classifi-cation techniques: classical approaches and new trends,” Communications, IET, vol. 1,no. 2, pp. 137–156, April 2007.

[3] Q. Chen, Y. Wang, and C. Bostian, “Universal classifier synchronizer demodulator,” inPerformance, Computing and Communications Conference, 2008. IPCCC 2008. IEEEInternational, Dec. 2008, pp. 366–371.

[4] Y. Wang, S. Nair, A. Young, Q. Chen, and C. W. Bostian, “Ofdm signal classficationand synchronization,” in Software Defined Radio 2008 Technical Conference and ProductExposition, 2008.

[5] Y. Wang, Q. Chen, and C. W. Bostian, “Universal classifier and synchronizer,” inInternational Journal of Autonomous and Adaptive Communications Systems, 2009.

[6] Y. Wang, “Dynamic Cellular Cognitive System,” Dissertation, Virginia PolytechnicInstitute and State University, 2009.

[7] Y. Li and G. L. Stuber, Orthogonal Frequency Division Multiplexing for Wireless Com-munications. Springer, 2005.

[8] Y. Wang, Q. Chen, C. W. Bostian, and S. Nair, “Universal classification synchronizationand demodulation,” US Patent 61/131,108, June 20, 2008.

[9] R. W. Thomas, D. H. Friend, L. A. Dasilva, and A. B. Mackenzie, “Cognitive networks:adaptation and learning to achieve end-to-end performance objectives,” Communica-tions Magazine, IEEE, vol. 44, no. 12, pp. 51–57, Dec. 2006.

[10] R. Chandra, V. Bahl, R. Mahajan, T. Moscibroda, S. Narlanka, and R. Raghavendra,“Adapting channel widths to improve application performance,” in CognitiveWireless Networking Summit 2008. Microsoft, 2008. [Online]. Available: http://research.microsoft.com/conferences/cognetsummit/presentations/chandra.pptx

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[11] J. Mitola, “Cognitive Radio An Integrated Agent Architecture for Software DefinedRadio,” Dissertation, Royal Institute of Technology (KTH), 2000.

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[13] F. Ge, A. Young, T. Brisebois, Q. Chen, and C. W. Bostian, “Software defined radioexecution latency,” in Software Defined Radio 2008 Technical Conference and ProductExposition, 2008.

[14] Lyrtech, Small Form Factor SDR Evaluation Module/Development Platform User’sGuide, Lyrtech, October 2007.

[15] L. Belanger, “Advanced sdr platform eases multiprotocol radio development,” RFDesign Magazine, 2007. [Online]. Available: http://rfdesign.com/mag/0701RFDF3.pdf

[16] K. C. Ltd, “Small form factor sdr evaluation module.” [Online]. Available:http://www.kanecomputing.co.uk/pdfs/lyrtech sff sdr eval mod.pdf

[17] Lyrtech, SFF SDR Development Platform Model-Based Design Guide, Lyrtech, April2007.

[18] W.-S. Gan, Y.-K. Chong, W. Gong, and W.-T. Tan, “Rapid prototyping system forteaching real-time digital signal processing,” Education, IEEE Transactions on, vol. 43,no. 1, pp. 19–24, Feb 2000.

[19] C. Dick, “The platform fpga: Enabling the software defined radio,” in Software DefinedRadio 2002 Technical Conference and Product Exposition, 2002.

[20] J. Seely, “Fpga use in software-defined radios,” EE Times, 2004. [Online]. Available:http://www.eetimes.com/showArticle.jhtml?articleID=29100653

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[24] P. Amini, E. Azarnasab, X. Mao, and B. Farhang-Boroujeny, “Implementation of acognitive radio modem,” in Software Defined Radio 2007 Technical Conference andProduct Exposition, 2007.

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