CO-SYNTHESIS OF HARDWARE AND SOFTWARE

FOR DIGITAL EMBEDDED SYSTEMS

THE KLUWER INTERNATIONAL SERIES IN ENGINEERING AND COMPUTER SCIENCE

VLSI, COMPUTER ARCHITECTURE AND DIGITAL SIGNAL PROCESSING

Consulting Editor Jonathan Allen

Other books in the series:

LOGIC SYNTHESIS FOR FIELD-PROGRAMMABLE GATE ARRAYS, Rajeev Murgai, Robert K. Brayton ISBN: 0-7923-9596-4

CODE GENERATION FOR EMBEDDED PROCESSORS, P. Marwedel, G. Goossens ISBN: 0-7923-9577-8

DIGITAL TIMING MACROMODELING FOR VLSI DESIGN VERIFICATION, Jeong­Taek Kong, David Overhauser ISBN: 0-7923-9580-8

DIGIT-SERIAL COMPUTATION, Richard Hartley, Keshab K. Parhi ISBN: 0-7923-9573-5

FORMAL SEMANTICS FOR VHDL, Carlos Delgado Kloos, Peter T. Breuer ISBN: 0-7923-9552-2

ON OPTIMAL INTERCONNECTIONS FOR VLSI, Andrew B. Kahng, Gabriel Robins ISBN: 0-7923-9483-6

SIMULATION TECHNIQUES AND SOLUTIONS FOR MIXED-SIGNAL COUPLING IN INTEGRATED CIRCUITS, Nishath K. Verghese, Timothy J. Schmerbeck, David J. Allstot

ISBN: 0-7923-9544-1 MIXED-MODE SIMULATION AND ANALOG MULTILEVEL SIMULATION, Resve

Saleh, Shyh-Jye Jou, A. Richard Newton ISBN: 0-7923-9473-9

CAD FRAMEWORKS: Principles and Architectures, Pieter van der Wolf ISBN: 0-7923-9501-8

PIPELINED ADAPTIVE DIGITAL FILTERS, Naresh R. Shanbhag, Keshab K. Parhi ISBN: 0-7923-9463-1

TIMED BOOLEAN FUNCTIONS: A Unified Formalism for Exact Timing Analysis, William K.C. Lam, Robert K. Brayton ISBN: 0-7923-9454-2

AN ANALOG VLSI SYSTEM FOR STEREOSCIPIC VISION, Misha Mahowald ISBN: 0-7923-944-5

ANALOG DEVICE-LEVEL LAYOUT AUTOMATION, John M. Cohn, David J. Garrod, Rob A. Rutenbar, L. Richard Carley ISBN: 0-7923-9431-3

VLSI DESIGN METIlOOOLOGIES FOR DIGITAL SIGNAL PROCESSING ARCHITECTURES, Magdy A. Bayoumi

ISBN: 0-7923-9428-3 CIRCUIT SYNTIIESIS WITII VHDL, Roland Airiau, Jean-Michel Berge, Vincent Olive

ISBN: 0-7923-9429-1 ASYMPTOTIC WAVEFORM EVALUATION, Eli Chiprout, Michel S. Nakhla

ISBN: 0-7923-9413-5

CO-SYNTHESIS OF HARDWARE AND SOFTWARE

FOR DIGITAL EMBEDDED SYSTEMS

by

Rajesh Kumar Gupta

University of Illinois

~.

" SPRINGER SCIENCE+BUSINESS MEDIA, LLC

ISBN 978-1-4613-5965-4 ISBN 978-1-4615-2287-4 (eBook) DOI 10.1007/978-1-4615-2287-4

Library of Congress Cataloging-in-Publication Data

A C.I.P. Catalogue record for this book is available from the Library of Congress.

Copyright © 1995 by Springer Science+Business Media New York Originally published by Kluwer Academic Publishers in 1995 Softcover reprint of the hardcover 1 st edition 1995

AlI rights reserved. No part of this publication may be reproduced, stored in a retrieval system or transmitted in any form or by any means, mechanical, photo-copying, recording, or otherwise, without the prior written permis sion of the publisher, Springer Science+Business Media, LLC.

Printed on acid1ree paper.

CO-SYNTHESIS OF HARDWARE AND SOFTWARE

FOR DIGITAL EMBEDDED SYSTEMS

To Anand Swarup Gupta.

CONTENTS

FOREWORD

PREFACE

1 INTRODUCTION 1 1.1 Design of Embedded Systems 3 1.2 Synthesis Solutions 5 1.3 Co-design and Co-synthesis 6 1.4 Motivations for Hardware-Software Co-synthesis 8 1.5 Applications 12 1.6 The Opportunity of Co-synthesis 13 1.7 Scope and Contributions 18 1.8 Outline of the Book 18

2 RELATED WORK 21 2.1 CAD Systems for Hardware-Software Co-design 22 2.2 CAD for Hardware-Software Co-synthesis 26

3 SYSTEM MODELING 33 3.1 System Specification using Procedural HDL 34 3.2 System Model and its Representation 39 3.3 The Flow Graph Model 41 3.4 Interaction Between System and its Environment 57 3.5 }/1J, Execution Rate and Communication 59 3.6 Constraints 63 3.7 Summary 69

CO-SYNTHESIS FOR DIGITAL EMBEDDED SYSTEMS

4 CONSTRAINT ANALYSIS 71 :1:.1 Scheduling of Operations 72 4.2 Deterministic Analysis of Min/max Delay Constraints 78 4.3 Deterministic Analysis of Execution Rate Constraints 81 4.4 Constraints Across Graph Models 99 4.5 N'D Cycles in A Constraint Graph 100 4.6 Probabilistic Analysis of Min/max and Rate Constraints 108 4.7 Flow Graph as a Stochastic Process 114 4.8 Summary 122

5 SOFTWARE AND RUNTIME ENVIRONMENT 125 5.1 Processor Cost Model 126 5.2 A Model for Software and Runtime System 130 5.3 Estimation of Software Performance 133 5.4 Estimation of Software Size 136 5.5 Software Synthesis 155 5.6 Step I: Generation of Program Threads 159 5.7 Step II: Generation of Program Routines 167 5.8 Step III: Code Synthesis 169 5.9 Issues in Code Synthesis from Program Routines 171 5.10 Summary 174

6 SYSTEM PARTITIONING 177 6.1 Partition Cost Model 179 6.2 Local versus Global Properties 184 6.3 Partitioning Feasibility 186 6.4 Partitioning Based on Separation of Control and Execute

Procedures 191 6.5 Partitioning Based on Division of N'D Operations 191 6.6 Partition Related Transformations 195 6.7 Summary 197

7 SYSTEM IMPLEMENTATION 199 7.1 Vulcan System Implementation 199 7.2 Implementation of Target Architecture in Vulcan 206

Contents

7.3 Co-simulation Environment 7.4 Summary

8 EXAMPLES AND RESULTS 8.1 Graphics Controller 8.2 Network Controller

9 SUMMARY, CONCLUSIONS, AND FUTURE

214 220

221 222 227

WORK 235 9.1 Future Work 237

Bibliography 239

REFERENCES 239

A A NOTE ON HARDWAREC 251

B BILOGIC GRAPHS 253

C PROCESSOR CHARACTERIZATION IN VULCAN 257

D RUNTIME SCHEDULER ROUTINES 259

INDEX 263

FOREWORD

Hardware/software co-design problems stem from the need of balancing the components of a digital system in the search for implementations with maximal performance under cost and power-consumption constraints. Whereas such problems have been solved for years by the ingenuity of digital designers, it is now clear that computer-aided solutions to the evaluation and synthesis of hardware/software systems can lead to better implementations with reduced design-time and cost. This explains the increasing interest in industry and in academia on computer aids to hardware/software co-design.

Efficient solutions to co-design problems are particularly important for em­bedded systems, which are digital systems dedicated to specific applications. Embedded systems, such as signal processing and control systems, have ex­tensive applications in the transportation industry (e.g., automotive control, aircraft and ship guidance), in the manufacturing industry (e.g., plant control, robots), in the telecommunication domain, and for the environmental control and defense of the territory.

A seminal research on computer-aided analysis and synthesis of hardware/soft­ware systems started at Stanford University in 1990. This book highlights major findings achieved in five years of research and experimentation. This research represents the evolution of techniques developed for hardware chip synthesis in the direction of supporting system-level hardware/software syn­thesis. It questions the need for developing application-specific integrated cir­cuits and argues for their most efficient use in conjunction with programmable, off-the-shelf processors and processor core macro-cells.

A prerequisite for this type of research is to perform a broad analysis of the models for hardware and software that allows a designer or a computer pro­gram to extract quality measures of the implementations of both the hardware and software components. This book provides the reader with modeling and analysis techniques, as well as with synthesis methods for hardware, software and interfaces under different types of constraints that are specific to embedded systems.

CO-SYNTHESIS FOR DIGITAL EMBEDDED SYSTEMS

This book is of interest to CAD researchers and developers who want to branch off into the exciting and expanding field of hardware/software co-design, as well as to digital system designers who are interested in the present power and limitations of CAD techniques and their likely evolution.

Giovanni De Micheli Stanford University

PREFACE

This book is a revised edition of my doctoral thesis, submitted in 1993 to Stanford University. It has been written to introduce the reader to the emerging area of system design from a CAD perspective. The objective of this book is to present important problems and solutions in developing CAD for embedded systems.

As with any system-building effort, much of the work borrows from the exist­ing body of research in diverse areas. In particular, this work develops design automation of embedded systems by extending techniques for synthesis of dig­ital hardware and software compilation. The primary motivation for this work comes from recent advancements on two fronts: (a) maturity of chip-level hard­ware synthesis tools that have made it possible to synthesize custom hardware circuits under strict timing constraints; and (b) the availability of powerful mi­croprocessors either as a single-chip or as processor core devices. With these developments, it is now possible to realize complex system function ali ties using off-the-shelf microprocessors and memory parts as building blocks. Although most digital functions can be implemented in software, customized hardware is often needed to meet performance constraints. This process of joint synthesis of software and hardware is termed as co-synthesis. Practical applications of co-synthesis are in the area of embedded systems.

This book addresses both theoretical and practical aspects embedded system design. It provides a decomposition of the co-synthesis problem into sub­problems of modeling, simulation, partitioning, and synthesis, each of which is then examined in detail. It develops the notion of constraint satisfiability both in the deterministic and probabilistic sense. The satisfiability analysis pro­ceeds by identifying cases where no possible implementation exists that meets the timing constraints due to the structural properties of the system model. We identify the cases when the deterministic analysis fails to produce an answer. For such cases, a notion of marginal satisfiability of constraints is developed that determines the satisfaction of timing constraints under a specified bound on the probability of violation. In limited cases, a transformation of the input model is suggested to increase the probability of constraint satisfaction. This

CO-SYNTHESIS FOR DIGITAL EMBEDDED SYSTEMS

treatment of constraint satisfiability is useful in distinguishing cases where a timing constraint must always be met from the ones where timing constraint satisfaction is primarily a performance issue.

Timing constraint analysis provides the user with important feedback on the eff'ect of constraints on the quality and the cost of implementation. This con­straint analysis can be used interactively by the system designer in exploring cost/performance tradeoff's. In the co-synthesis context, timing constraint anal­ysis is used to define the boundary between hardware and software portions of the functionality. An iterative partitioning approach is used to maximize the software component without violating constraint satisfiability of an implemen­tation. The partitioned models are translated into hardware using high-level synthesis techniques.

Software synthesis for hardware-software systems is a challenging problem due to two reasons: (a) the inherently serial nature of program executions that must interact with concurrently operating hardware components and (b) the non~determinism in the software execution due to data-dependent and syn­chronization operations. These issues respectively point to a need for pseudo­concurrency in software and a need for low overhead system synchronization mechanisms. This is achieved by implementing the software into concurrently active fixed-latency multiple program threads. A FIFO-bases runtime sched­uler is developed to preserve the control-flow among the concurrent program threads. We demonstrate the applicability of control FIFO-based hardware­software synchronization schemes for embedded systems.

We believe that the techniques presented in this book would be useful in building complex embedded systems and provide a competitive advantage over purely hardware or software implementations of time-constrained embedded systems.

Urbana-Champaign, Illinois R.K. G.

Preface

Acknowledgements

My gratitude is to Professor Giovanni De Micheli for giving me the opportunity to explore new grounds in the computer-aided design of electronic systems. My thanks to my associate advisor, Professor Michael J. Flynn and other members of my reading committee, Professor Krishna Saraswat, Professor Kunle Oluko­tun and Dr. Martin Freeman of Philips Research, Palo Alto. Dr. Freeman also helped in monitoring and guiding this research as a mentor under the Philips Graduate Fellowship program. I would like to thank Uzi Bar-Gadda and Joe Kostelec of Philips Research, and Dr. Rick Reis and Carmen Miraflor of the Center for Integrated Systems for the honor to have been supported by the Philips Fellowship for the years 1992 and 1993.

This research builds upon the prior work of many people. I would like to thank all the other people involved in the synthesis project at Stanford. Of particular mention are David Ku, Frederic Mailhot, and Thomas Truong for writing the Olympus Synthesis System upon which the project is based. Claudionor Coelho wrote the simulator and contributed in numerous ways to this research work.

Many thanks are due to past and present members of our research group at Stanford. I am thankful to my colleagues Maurizio Damiani, Polly Siegel, Jerry Yang and David Filo for providing a supportive and productive environment. I would also like to take this opportunity to thank my friends outside our research group, Rohit Chandra and Kourosh Gharachorloo, for many discussions and for providing the valuable 'non-CAD' feedback to this research. Many thanks are due to Ms. Lilian Betters and Bonnie Howard for valuable administrative support.

Many thanks to my colleague and one of the most critical examiners of this research, Dr. Mani Bhushan Srivastava of AT&T Bell Laboratories. I would also like to thank Professors Gaetano Borriello of the University of Washington, Wayne Wolf of Princeton University, Daniel Gajski of the University of Cali­fornia, Irvine and Alberto Sangiovanni-Vincentelli of UC Berkeley for taking active interest in this research and for their encouragement.

Finally, my regards to my parents, Sanjay and Neena for their love and under­standing.

Financial support for this research was provided by a fellowship provided by Philips and the Center for Integrated Systems, and by NSF-ARPA under grant MIP 9115432. I am grateful for their support.