BTEC NC - Microprocessor Systems and Application - Using a Microprocessor Development System
CN310 Microprocessor Systems Design · A device incorporates most or all of the functions of a...
Transcript of CN310 Microprocessor Systems Design · A device incorporates most or all of the functions of a...
CN310 Microprocessor Systems DesignMicroprocessor Architecture
Nawin Somyat
Department of Electrical and Computer EngineeringThammasat University
Outline
Course Contents1 Introduction2 Simple Computer3 Microprocessor Architecture4 Memory5 Peripherals6 Applications
Outline1 Diagram2 Architecture
Processor CoreMemoryBuses
3 Instruction SetBasicsData AccessControl Flow
CN310 Microprocessor Systems Design 2 / 60
Block Diagram
A graphical representation of principal structure and itsinterconnections, used for a higher level, less detailed description ofthe overall concepts.
Blocks: parts / components / functionsLines: connections / relationshipsThick lines: grouped connectionsArrows: direction of energy / current / signal / data
CN310 Microprocessor Systems Design 3 / 60
Block Diagram
CN310 Microprocessor Systems Design 4 / 60
Block Diagram
CN310 Microprocessor Systems Design 5 / 60
Schematic
A graphical representation of the elements of a system usingabstract, graphic symbols rather than realistic pictures.
CN310 Microprocessor Systems Design 6 / 60
Timing Diagram
A graphical representation of the time variation of signals, as wellas the timed relationship between the signals.
CN310 Microprocessor Systems Design 7 / 60
What is Microprocessor
A device incorporates most or all of the functions of a centralprocessing unit (CPU) on a single integrated circuit.
CN310 Microprocessor Systems Design 8 / 60
What is Microprocessor
An electronic component:Need fixed supply DC voltage (Vcc) and ground (GND).Operations rely on voltage signal.Internal operations are based on transistors.
A digital IC:Operate with respect to clock signal.Interpret voltage level as logic.
A device with constrained electrical properties:Can supply only limited current (sink > source)When interfacing with analog signal, input voltage must notexceed supply voltage.
A device with processing capability: compared with similarprocessor core
More frequency (MHz) means faster computation.Larger data width (8bit < 16bit < 32bit < 64bit) means moredata processing and transfer capability.
CN310 Microprocessor Systems Design 9 / 60
Cautions
Microprocessor is built using CMOS technologyLower supply voltage (3.3V,2.5V,1.8V) uses less power, butwill be damaged from 5V circuit.Power loss is proportional to switching frequency.Vulnerable to electrostatic discharge (ESD).
Microprocessor executes code within memory.Memory address must be aligned with instruction/data width.
Microprocessor selection may need to concern regulations.Thermal properties: operating temperature, heat dissipation.Electromagnetic properties: EMC.Production requirements: lead-free, RoHS.
CN310 Microprocessor Systems Design 10 / 60
Processor Core
A microprocessor is a programmable chip that is used for executinginstructions to process data or control other devices.
CN310 Microprocessor Systems Design 11 / 60
Processor Core
Control Unit: manage sequence of processing, e.g.Fetch and execute instructions.Move data among memory locations.Branch to separate instruction based on decisions.
Arithematic and Logic Unit: perform mathematical andlogical operations, e.g.
Addition, subtraction, multiplication, and divisionAND, OR, XOR, and shift operations.
Registers and Flags:Instruction register/decoder:Program counter (PC): memory address of next instruction
Memory bus: path to access memory
CN310 Microprocessor Systems Design 12 / 60
Processor Core: Example
CN310 Microprocessor Systems Design 13 / 60
Processor Core: Example ARM
CN310 Microprocessor Systems Design 14 / 60
Processor Core: Example AVR
CN310 Microprocessor Systems Design 15 / 60
Processor Core: Example Core 2
CN310 Microprocessor Systems Design 16 / 60
Concepts
Instruction = what to do!Register = temporary memoryData = intermediate (constant) or reference(register/memory)Memory = place of code (ROM) or data (RAM)Address = location in memory of code/data
CN310 Microprocessor Systems Design 17 / 60
Architecture
Fundamental operational structure of processor core fromprogramming viewpoint
Instruction setRegistersData typesAddressing modesMemory architectureInterrupt and exception handlingExternal I/O
CN310 Microprocessor Systems Design 18 / 60
Instruction Set
An instruction set is a list of all the opcodes (machine language)that a processor can execute.
instruction = opcode + operands
CN310 Microprocessor Systems Design 19 / 60
Instruction Set
Registers for arithmetic, addressing, or control functionsMemory locations or offsetsOperands referred by addressing modes
Arithmetic instructions, e.g. add, subtractLogic instructions, e.g. and, or, notData instructions, e.g. move, input, output, load, storeControl flow instructions, e.g. goto, if-goto, call, returnSpecial instructions, e.g. test-and-set, vector/floating-point
CN310 Microprocessor Systems Design 20 / 60
Instruction set
Other than their functions, instructions may be grouped based onthe number of operands.
0-operand (stack machines): arithmetic operations use datafrom stack.push a; push b; add; pop c;
1-operand (accumulator machines): specify an operand(register, mem location, constant) with implicit accumulatorload a; add b; store c;
2-operand:load a,reg1; load b,reg2; add reg1,reg2;
3-operand: complex operations or addressing modesCISC = move a,reg1; add reg1,b,c;RISC = load a,reg1; add reg1,reg2,reg3;(add reg1+reg2 -> reg3)
more operands:
CN310 Microprocessor Systems Design 21 / 60
Registers and Flags
Registers are limited internal storage within microprocessor, fastestto access from MPU side.
Used as temporary storage for execution input and outputIndicate the execution capability of instruction/data, e.g. 8bit,16bit, 32bit, 64bitReflect the size of word, group of bits that processor canhandle in one operation
Flags refer to one or more bits within a register, that store a binaryvalue representing a specific meaning
CN310 Microprocessor Systems Design 22 / 60
Registers and Flags
Instruction registers stores the instruction currently beingexecuted or decodedGeneral purpose registers hold data/address values
Data registers hold numeric valuesAddress registers hold index values for memory addressing
Control and status registers include program counter, stackpointer, and status registerConditional registers hold enable/disable conditions forspecific instructionsSpecial purpose registers store program stateHardware registers contain bits of hardware state.Some architectures include additional registers, e.g. floatingpoint registers, vector registers
CN310 Microprocessor Systems Design 23 / 60
AVR Registers
AVR architecture uses fast-accessregister file containing 32 x 8-bitregisters.
Single clock cycle access timeSixteen 16-bit addressable units
CN310 Microprocessor Systems Design 24 / 60
AVR Status Register
Status Register (SREG) is updated after all arithmetic and logicalinstructions, containing a set of status flags:
I: Global Interrupt EnableH: Half Carry FlagV: Twos Complement Overflow FlagZ: Zero Flag
T: Bit Copy StorageS: Sign BitN: Negative FlagC: Carry Flag
CN310 Microprocessor Systems Design 25 / 60
Memory Models
Memory model is the way that processor can reference to an entityin memory.
Flat memory model: single space up to 2n
Simple, efficient for single task.Not appropriate for multitasking OS (required MMU)
Paged memory model: multiple pages, each page up to 2n
Suitable for multitasking environmentHarder for low-level management
Segmented memory model: combined segment:offsetMore efficient due to variable page boundariesMore difficult for compilers
CN310 Microprocessor Systems Design 26 / 60
Memory Map
A memory map is a representation of memory layout for storingcode and data.
Program codeInternal or external flash memory
Read/write memory
Internal or external RAMHardware registers mapping
CN310 Microprocessor Systems Design 27 / 60
Harvard Architecture
Harvard → code and data use separate memory space.
CN310 Microprocessor Systems Design 28 / 60
von Neumann Architecture
von Neumann → code and data use shared memory space.
CN310 Microprocessor Systems Design 29 / 60
Cache Memory
CPU cache is a smaller, faster memory used by CPU to reduce theaverage time to access system memory.
Cache stores copies of frequently usedcode/data in main memoryModern processors integrate threetypes of cache
Instruction cache to speed upexecutable instruction fetch.Data cache to speed up data fetchand store.Translation lookaside buffer to speedup virtual-to-physical addresstranslation
Efficiency depends on hit/miss ratio
CN310 Microprocessor Systems Design 30 / 60
Architecture Classification
Instruction Set:Complex Instuction Set Computer (CISC): limitedaccumulators, complex instruction set, various addressingmodes.
Aim for 1 processing/1 instruction = small code size
Reduced Instruction Set Computer (RISC): general-purposeregisters, simple instruction set, limited addressing modes,load-store execution
Aim for 1 clock/1 instruction = better MIPSOthers: DSP, VLIW, . . .
Word size: 8 / 16 / 32 / 64 bitMemory space: program and data.
von Neumann architecture: share address space.Harvard architecture: separate address space.
CN310 Microprocessor Systems Design 31 / 60
Questions
What architecture typesof AVR coreHow many registers inAVR coreWhat is word length ofAVR coreHow large memory can beaddressedHow many addressingmodes AVR core support
CN310 Microprocessor Systems Design 32 / 60
Processor Bus
Processor bus is a subsystem that transfers data betweencomponents inside a microprocessor.
Data bus: transport data to/from memoryAddress bus: provide address of memory locationsControl bus: control devices on bus
There are different type of processor buses
System bus or memory bus:CPU ↔main memoryPeripheral bus or I/O bus:bridge ↔ peripheral devices
CN310 Microprocessor Systems Design 33 / 60
Bus Addressing & Timing
Processor core accesses to code and data in memory using asequence of signals from address/data/control buses.
Generate and hold address valueon address bus
Some address bits may beused for memory chipselection
Assert Read/Write signal fromcontrol busAccess data via data bus
CN310 Microprocessor Systems Design 34 / 60
System and Peripheral Clocks
Microprocessor components are digital logics which operate w.r.t.clock signals.
Clock source may be external or internal oscillatorPLL (phase-locked-loop) multiplies clock frequency
Use low-frequency oscillatorPrescalar divides clock frequency
Peripheral devicesLower-speed devices
CN310 Microprocessor Systems Design 35 / 60
System and Peripheral Clocks: Example AVR
CN310 Microprocessor Systems Design 36 / 60
System and Peripheral Clocks
Clock source can be selected via I/O register
Changing clock source requires time to stabilize frequencyAdjusting clock frequency makes trade-off between processingpower and power consumption
CN310 Microprocessor Systems Design 37 / 60
Computer Buses
Computer buses cover data pathway among CPU, mainboardchipset, and external devices.
Northbridge or memory controller hub: front-side busMemory (RAM)Highspeed graphics subsystem
Southbridge or I/O controller hub:PCI bus = standardized bus for expansion cardsSATA and IDE = hard disk driveSPI bus = flash BIOS, SMBus = batteryUSB bus
CN310 Microprocessor Systems Design 38 / 60
Computer Buses: Example
CN310 Microprocessor Systems Design 39 / 60
Instruction Set
An instruction set is a list of all the opcodes (machine language)that a processor can execute.
Arithmetic instructions, e.g. add, subtractLogic instructions, e.g. and, or, notData instructions, e.g. move, input, output, load, storeControl flow instructions, e.g. goto, if-goto, call, returnSpecial instructions, e.g. test-and-set, vector/floating-point
Programming env. at level of machine instructions includes
Data typesAddressing mode
Execution statusInstruction timing
CN310 Microprocessor Systems Design 40 / 60
Instruction Cycle
Fetch-and-Execute cycle is a sequence where instructions arefetched from memory, then executed.
1 Fetch the instruction at PC into instruction register:IR ← [PC]
2 Decode the instruction and increment PC:PC ← PC + n
3 Fetch operands from memory (instruction with indirectaddress)
4 Execute the instruction by control unit or ALU5 Store result to memory
CN310 Microprocessor Systems Design 41 / 60
Execution Timing
The Parallel Instruction Fetches and Instruction Executions
Single Cycle ALU Operation
CN310 Microprocessor Systems Design 42 / 60
Accumulator Architecture
CISC processors have limited accumulators, complex instructions,orthogonal addressing modes.
Load data into accumulator.Execute instructions with additional data from memory.Store results into memory.
CN310 Microprocessor Systems Design 43 / 60
RISC Architecture
RISC processors have many working registers, simple addressingmodes, memory access via load/store instructions.
Load data from memory into registersExecute instructions using registersStore results into memory
CN310 Microprocessor Systems Design 44 / 60
ALU-Related Instructions
Basic arithematic and logic instructions that almost ALUs canperform:
Integer arithmetic operations: addition, subtraction,multiplication, divisionBitwise logic operations: AND, NOT, OR, XORBit-shifting operations: to the left or right, with or withoutsign extension
Shifts can be interpreted as multiplications by 2 and divisions by 2.Additional complex ALU operations are optional for the design ofinstruction set architecture.
Floating-point calculation is handled by FPU, not ALU.
CN310 Microprocessor Systems Design 45 / 60
Binary Representation
Two’s complement of a binary number is the value obtained bysubtracting the number from 2n.
−1 = 28(100000000)− 1(00000001) = 11111111
Encode negative numbers into ordinary binary without specialcircuit to handle signed computationRepresent number in the range −2n−1 to +2n−1 − 1
binary base-10 binary base-100111 1111 127 1111 1111 -10111 1110 126 1111 1110 -20000 0001 1 1000 0001 -1270000 0000 0 1000 0000 -128
CN310 Microprocessor Systems Design 46 / 60
Machine Data Size
Processor core view machine data types according to therelationship between instructions and registers/flags.
Bit: 0 or 1Each flag in conditional registers can be accessed via specificinstructionsA few processor cores can access general purpose registers atbit level
Byte: an octet (8-bit)Similar to word for 8-bit processorsNeed downsizing for 16-/32-/64-bit processors
Word: word length equals the size of registersSome processors support instructions that handle operandswith 2 words or more
CN310 Microprocessor Systems Design 47 / 60
Machine Data Types
Programming data types are translated at compiler level intomachine data types
Boolean, char, integer types are treated as word-length dataFloating-point value is handled by software or co-processor
Integer processing is the fastest since it is word-alignedFloating-point processing is the slowest if no co-processorArithematic operations based on native instructions, e.g. add,shift, are faster
In C language, integer promotion rules are applied for thecomputation of char/integer/long data
CN310 Microprocessor Systems Design 48 / 60
Status Register
Status register refers to a group of registers containing flags (bits)showing the status of microprocessor and execution result. Typicalstatuses include:
Carry Flag = result has carry from arithemetic operationZero Flag = result is zeroNegative Flag = result is negativeOverflow Flag = result is overflowParity Flag = result is odd or even’Interrupt Enable Flag = flag to enable/disable interruptTrap Flag = trap condition occurs w.r.t. execution result
Some instructions can manipulate these flags directly, orexecute according to their value.
CN310 Microprocessor Systems Design 49 / 60
Data Instructions
The movement of data between processor and external devices ishandled via the control unit through processor bus.
Set register to a constant value.Move data among registers and memory locations: copy,move, load, store.Read and write data with hardware devices: in, out.
Flexibility of referencing memory locations allow processor tohandle data transfer easier → addressing mode.
CN310 Microprocessor Systems Design 50 / 60
Addressing Modes
Addressing mode specifies how to calculate the effective memoryaddress of an operand by using information held in registers and/orconstants.
Register: operand is in the registerImmediate: operand is in the instruction itselfDirect: address of operand is in the instructionRegister Direct: address of operand is in the given registerBase Displacement: address is the sum of register content anda constantIndirect: instruction have address, the contents at the addressis the address of the operandRegister Indirect: register contains address, the contents atthe address is the address of the operand
CN310 Microprocessor Systems Design 51 / 60
Addressing Modes
Addressing modes for codeDirect: jump addrRegister Direct: jump regBase Displacement: jump offset
Addressing modes for dataDirect: load reg,addrBase Displacement: load reg,base,offset
CN310 Microprocessor Systems Design 52 / 60
Addressing Modes: Examples
Direct Data Addressing
CN310 Microprocessor Systems Design 53 / 60
Addressing Modes: Examples
Indirect Data Addressing with Displacement
CN310 Microprocessor Systems Design 54 / 60
Control Flow Instructions
Jumping (unconditional) or Branching (conditional) is the abilityto load the PC register with a new address that is not the nextsequential address.⇒ executing these instructions alters the flow of software.
Jump instructions:Absolute: local or longRelative
Branch instructions:Status register’s flagsComparison result
Subroutine instructions:Call and returnSoftware traps
CN310 Microprocessor Systems Design 55 / 60
Control Flow Instructions: Branch Instructions
CN310 Microprocessor Systems Design 56 / 60
Subroutine Call
A subroutine is a group of instructions that will be used repeatedlyin different locations of the program.⇒ basis of function call in high-level language.
CALL instruction: redirect the execution to the subroutineRET insutruction: return the execution to the calling routine
To return after subroutine ends, how processor can rememberits code address and execution state.
CN310 Microprocessor Systems Design 57 / 60
Stack
Processor stack is a memory portion used as temporary storageduring execution.
Stack operation is based onlast-in, first-out mechanism
Push register into stackPop top stack to register
Stack is always used for savingstatus and passing argumentsPC, status registers, workingregisters
PC, calling argumentsReturn value
CN310 Microprocessor Systems Design 58 / 60
Stack: Frame
Stack pointer (SP) is thememory address of stack lastdata
Kept by stack pointer registerEither increase or decrease,depend on processor
Stack overflow is the problem ofpushing too much data intostack
CN310 Microprocessor Systems Design 59 / 60
Stack: Subroutine
Hardware level: PC and SREG are saved by default.Software level: required registers by PUSH instruction.High-level language: all registers before each function call.
CN310 Microprocessor Systems Design 60 / 60