CMS HCAL Clock and Control Module QPPL/Crystal Upgrade

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CMS HCAL Clock and Control Module QPPL/Crystal Upgrade T. Shaw S. Holm 10 OCT 2012 1

description

CMS HCAL Clock and Control Module QPPL/Crystal Upgrade. T. Shaw S. Holm 10 OCT 2012. Clock and Control Module (CCM) V4. Board 1 Board 5 Board 3 Board 4. Clock and Control Module (CCM) V4. HB/HE/HO all use a CCM in every readout box (RBX) Board 1 - PowerPoint PPT Presentation

Transcript of CMS HCAL Clock and Control Module QPPL/Crystal Upgrade

Page 1: CMS HCAL  Clock and Control Module QPPL/Crystal Upgrade

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CMS HCAL Clock and Control Module

QPPL/Crystal Upgrade

T. ShawS. Holm

10 OCT 2012

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Clock and Control Module (CCM) V4

Board 1 Board 5 Board 3 Board 4

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Clock and Control Module (CCM) V4

• HB/HE/HO all use a CCM in every readout box (RBX)Board 1

Provides I2C communication via RBX backplane This board has opto-coupler experiencing SEUs -> rework of

board jumper (approved ECR)

Board 5 TTCrx Interface, FPGAs

Board 3 QPPL and clock distribution to 1st half RBX backplane

Board 4 QPPL and clock distribution to 2nd half RBX backplane

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Clock and Control Module (CCM) V4

• Boards 3 & 4 have QPLLs and are used to distribute 40MHz clock to all Front end electronics

HCAL boards were built before discovery of “activity dip” problems in the crystals. A new recommendation to provide a power reduction circuit was late for HCAL.

Aerial mod was done to try to patch problem. Probably not a good idea because crystals can be damaged by heat and mechanical force.

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Clock and Control Module (CCM) V4

• PCB layout of HCAL boards around QPLL also did not benefit from later recommendations which exist in latest QPLL manual.

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Clock and Control Module – Proposal to upgrade boards 3 & 4

• We propose to upgrade CCM boards 3 and 4.– Version 5

• New layout– Includes crystal power reduction circuitry– Follows the PCB recommendations in latest QPLL manual

• New design – Allow for redundancy in clock drive capability– Old design used a QPLL/crystal to drive half an RBX backplane

(Board3 ) and another QPLL/crystal to drive the other half (Board 4)– New design still uses two QPLL/crystal combinations, but selects

one to drive clocks to the entire RBX backplane. The second QPLL/crystal stands by as a hot spare ready to be switched to.

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CCM Boards 3 & 4 upgrade (V5)QPLL Selection

QPLLA 1

QPLLA 2

2 :10MUX

SEL

CLK

Loc k

CLK

Loc k

CLK Bac kplaneCloc k Dr iv e r

MC100LV EP1112:10

2:1

SEL

Bac kplaneCloc k Dr iv e r

MC100LV EP1112:10

2:1

SEL

DFFD Q

/QR

CLO CK S E LE CT

Q P LL RE S E T

CLO CK A

CLO CK B

QPLLLoc k A

QPLLLoc k B

B O A RD 4

+3.3vCan add more A ND gates

to c reate a de lay .

B O A RD 3

MC100LV EEP111

Q P LL RE S E T

CLO CK S E LE CT

See page 2 f o r TMRimp lementa tion

MC100LV EL05MC100LV ELT23

MC100LV ELT22

Because we retain CCM boards 1&5, we are constrained in the design to use two available control signals “QPLL_RESET” and “CLOCK_SELECT”

Designed by Scott Holm

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CCM Boards 3 & 4 upgrade (V5)QPLL Selection – TMR section

MC100-LV EL30

D Q

/QR

MC100-LV EL30

D Q

/QR

MC100-LV EL30

D Q

/QR

MC100LV ELT23

MC100LV EL05

MC100LV EL01

Triple Modular Redundancy

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CCM Boards 3 & 4 upgrade (V5)QPLL Selection – Timing

QPLL A QPLL B QPLL A QPLL AQPLL B QPLL B

QPLL BQPLL A

Board 1 Mux Selec t

Bac kplane c loc k

Cloc k Selec t

QPLL Res et(TTC Res et)

Bac kplaneCloc k

Enab led

Bac kplaneCloc k

Enabled

Bac kplaneCloc k

Enabled

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• Design/Timing has been tested at Fermilab and at CERN• QPLL lock range tested on two pre-production boards 3 & 4

(Work done by Dick Kellogg at CERN )– No activity dips observed– Minimum range 7.4KHz centered almost perfectly at fLHC, at 40.0791

CCM Boards 3 & 4 upgrade (V5)QPLL Selection – Timing

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CCM Boards 3 & 4 upgrade (V5)Jitter Measurement

Measurements on unloaded HB backplane4 October 2012

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– HCAL Radiation levels• Radiation from LS1-LS2 (when CCMs will all be removed) are relatively low

– Worst levels (with safety margin): TID – 190rad, neutron level – 1.3E11 n/cm2 • Component types were all tested before. [Stick to same family of chips.]

– Chosen MC100LVEL family of chips which have been shown to be robust. Board is designed with TMR, which should make it immune to SEUs

– Test new chips for performance degradation after gamma exposure.

– Radiation Testing Proposal – radiation levels are low enough and new components are low risk we are advocating not to do additional testing

• Rad testing cost ($16500)– CERN gamma facility (available Oct/Nov/Dec)

» TID exposure of chips (free beam + simple (bread board) fixture)» Cost: $100 shipping + $2k tech time + $500 boards = $2600

– MGH (machine problems – available only after Dec)» Cost: $650/hr (~6hrs) + travel to Boston + special board to test chips [$3900 (beam)

+ $5k (boards) + $2000 (travel) + $3k eng time] = $13900

Radiation Testing Proposal

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• Pre-production CCM boards 3 and 4 (V5) have been tested and work

• No changes required to move into production phase

Conclusions