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Transcript of CMPUT 229 - Computer Organization and Architecture I1 CMPUT229 - Fall 2002 Topic 2: Digital Logic...
![Page 1: CMPUT 229 - Computer Organization and Architecture I1 CMPUT229 - Fall 2002 Topic 2: Digital Logic Structure Jos Nelson Amaral.](https://reader036.fdocuments.in/reader036/viewer/2022062401/5a4d1b887f8b9ab0599bd7c2/html5/thumbnails/1.jpg)
CMPUT 229 - Computer Organization and Architecture I
1
CMPUT229 - Fall 2002
Topic 2: Digital Logic StructureJosé Nelson Amaral
![Page 2: CMPUT 229 - Computer Organization and Architecture I1 CMPUT229 - Fall 2002 Topic 2: Digital Logic Structure Jos Nelson Amaral.](https://reader036.fdocuments.in/reader036/viewer/2022062401/5a4d1b887f8b9ab0599bd7c2/html5/thumbnails/2.jpg)
CMPUT 229 - Computer Organization and Architecture I
2
Reading Material
Patt & Patel, Chapter 3
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CMPUT 229 - Computer Organization and Architecture I
3
The Light Switch
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CMPUT 229 - Computer Organization and Architecture I
4
A N-MOS transistor
A Metal-Oxide Semiconductor (MOS) transistor has three terminals. The Gate controls the flow of electrons between the two other terminals.
In a N-type MOS transistor, electrons will flow when a voltage of 2.9 Vis applied to the Gate (closed circuit).If 0.0 V is applied to the Gate no electrons will flow (open circuit).
2.9 Voltbattery(powersupply)
Gate GateGate
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CMPUT 229 - Computer Organization and Architecture I
5
The NOT GateProblem: Use two MOS transistors to implement the following logic circuit:
NOT
2.9 Volts
0 Volts
In Out
Your NOT circuit should implement the following logic function:
In Out 0 Volts 2.9 Volts
2.9 Volts 0 Volts
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CMPUT 229 - Computer Organization and Architecture I
6
P-MOS Transistor
The operation of a P-type MOS transistor, is the opposite of an N-MOS:
- electrons will flow when a voltage of 0.0 V is applied to the Gate (closed circuit).- If 2.9 V is applied to the Gate no electrons will flow (open circuit).
Gate
#1
#2
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CMPUT 229 - Computer Organization and Architecture I
7
2.9V0V
0 Volts
2.9 Volts
0V
2.9 Volts
0 Volts
2.9V
The NOT Gate
In
2.9 Volts
0 Volts
Out
In Out 0 Volts 2.9 Volts
2.9 Volts 0 Volts
In Out 0 1 1 0
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CMPUT 229 - Computer Organization and Architecture I
8
A= 0V
B=0V
The NOR GateA B C
0 Volts 0 Volts 2.9 Volts
A
C
BC= 2.9V
![Page 9: CMPUT 229 - Computer Organization and Architecture I1 CMPUT229 - Fall 2002 Topic 2: Digital Logic Structure Jos Nelson Amaral.](https://reader036.fdocuments.in/reader036/viewer/2022062401/5a4d1b887f8b9ab0599bd7c2/html5/thumbnails/9.jpg)
CMPUT 229 - Computer Organization and Architecture I
9
The NOR GateA B C
0 Volts 0 Volts 2.9 Volts 0 Volts 2.9 Volts 0 Volts
A
C
B
A= 0V
C= 0V
B=2.9V
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CMPUT 229 - Computer Organization and Architecture I
10
The NOR Gate
A
C
B
A= 2.9V
C= 0V
B= 0V
A B C 0 Volts 0 Volts 2.9 Volts 0 Volts
2.9 Volts 2.9 Volts 0 Volts
0 Volts 0 Volts
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CMPUT 229 - Computer Organization and Architecture I
11
The NOR GateA B C
0 Volts 0 Volts 2.9 Volts 0 Volts
2.9 Volts 2.9 Volts
2.9 Volts 0 Volts
2.9 Volts
0 Volts 0 Volts 0 Volts
A
C
B
A= 2.9V
C= 0V
B= 2.9V
A B C 0 0 1 0 1 1
1 0 1
0 0 0
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CMPUT 229 - Computer Organization and Architecture I
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What Logic Function this Circuit Implements?
A
BC
D
A B C D 0 0 1 0 0 1 1
1 0 1
0 0 0
1 1 1
1
This is an OR gate.
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CMPUT 229 - Computer Organization and Architecture I
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The AND Gate
A
B CD
A B C D 0 0 1 0 0 1 1
1 0 1
1 1 0
0 0 1
1
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CMPUT 229 - Computer Organization and Architecture I
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Logic Functions
INVERTER
X X’
X X’0 11 0
If X=0 then X’=1If X=1 then X’=0
OR
AB C=A+B
A B C0 0 00 1 11 0 11 1 1
If A=1 OR B=1 then C=1 otherwise C=0
AB C=A·B
A B C0 0 00 1 01 0 01 1 1
If A=1 AND B=1 then C=1 otherwise C=0
AND
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CMPUT 229 - Computer Organization and Architecture I
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NOR and NAND
Because these combination of gates are used often, thereare special symbols to represent them:
XY
Z XY
Z
ZXY
XY Z
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CMPUT 229 - Computer Organization and Architecture I
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First DeMorgan’s Law
The complement of the OR is equal the AND of the complements.
(X+Y)’ = X’Y’
XY
Z
X Y X+Y (X+Y)’ X’ Y’ X’Y’0 0 0 1 1 1 10 1 1 0 1 0 01 0 1 0 0 1 01 1 1 0 0 0 0
ZY
X
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CMPUT 229 - Computer Organization and Architecture I
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Decoders General decoder structure
Typically n inputs, 2n outputs 2-to-4, 3-to-8, 4-to-16, etc.
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CMPUT 229 - Computer Organization and Architecture I
18
Decoders
3-to-8Line
Decoder
y0 = a’b’c’y1 = a’b’cy2 = a’bc’y3 = a’bcy4 = ab’c’y5 = ab’cy6 = abc’y7 = abc
abc
a b c y0 y1 y2 y3 y4 y5 y6 y7 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 1 1 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 1 0 1 0 0 0 0 0 1 0 0 1 1 0 0 0 0 0 0 0 1 0 1 1 1 0 0 0 0 0 0 0 1
+
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CMPUT 229 - Computer Organization and Architecture I
19
Multiplexers
4-to-1MUX
I0
I1
I2
I3
A B
Z
A B Z 0 0 I0 0 1 I1 1 0 I2 1 1 I3
+
ABI3
AB’I2
A’BI1
A’B’I0
Z
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CMPUT 229 - Computer Organization and Architecture I
20
AddersBasic building block is “full adder”
1-bit-wide adder, produces sum and carry outputs X Y Cin S Cout
0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 1 1 1
Cout is one if two or moreof the inputs are one.
S is one if an odd numberof inputs are one.
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CMPUT 229 - Computer Organization and Architecture I
21
Full-adder circuit
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CMPUT 229 - Computer Organization and Architecture I
22
Ripple adder
Speed limited by carry chain Faster adders eliminate or limit carry chain
2-level AND-OR logic ==> 2n product terms3 or 4 levels of logic, carry lookahead
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CMPUT 229 - Computer Organization and Architecture I
23
A bi-stable circuitHow to control it?
Control inputsS-R latch
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CMPUT 229 - Computer Organization and Architecture I
24
D latch
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IN OUTSELWR
IN OUTSELWR
IN OUTSELWR
IN OUTSELWR
IN OUTSELWR
IN OUTSELWR
IN OUTSELWR
IN OUTSELWR
IN OUTSELWR
IN OUTSELWR
IN OUTSELWR
IN OUTSELWR
IN OUTSELWR
IN OUTSELWR
IN OUTSELWR
IN OUTSELWR
IN OUTSELWR
IN OUTSELWR
IN OUTSELWR
IN OUTSELWR
IN OUTSELWR
IN OUTSELWR
IN OUTSELWR
IN OUTSELWR
IN OUTSELWR
IN OUTSELWR
IN OUTSELWR
IN OUTSELWR
IN OUTSELWR
IN OUTSELWR
IN OUTSELWR
IN OUTSELWR
DOUT3 DOUT2 DOUT1 DOUT0
3-to-8decoder
2
1
0
A2
A1
A0
0
1
2
3
4
5
6
7
DIN3 DIN0DIN2 DIN1
WE_LCS_L
OE_L
WR_L
IOE_L
0
1
1
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IN OUTSELWR
IN OUTSELWR
IN OUTSELWR
IN OUTSELWR
IN OUTSELWR
IN OUTSELWR
IN OUTSELWR
IN OUTSELWR
IN OUTSELWR
IN OUTSELWR
IN OUTSELWR
IN OUTSELWR
IN OUTSELWR
IN OUTSELWR
IN OUTSELWR
IN OUTSELWR
IN OUTSELWR
IN OUTSELWR
IN OUTSELWR
IN OUTSELWR
IN OUTSELWR
IN OUTSELWR
IN OUTSELWR
IN OUTSELWR
IN OUTSELWR
IN OUTSELWR
IN OUTSELWR
IN OUTSELWR
IN OUTSELWR
IN OUTSELWR
IN OUTSELWR
IN OUTSELWR
DOUT3 DOUT3 DOUT3 DOUT3
3-to-8decoder
2
1
0
A2
A1
A0
0
1
2
3
4
5
6
7
DIN3 DIN3DIN3 DIN3
WE_LCS_L
OE_L
WR_L
IOE_L
0
1
1
![Page 27: CMPUT 229 - Computer Organization and Architecture I1 CMPUT229 - Fall 2002 Topic 2: Digital Logic Structure Jos Nelson Amaral.](https://reader036.fdocuments.in/reader036/viewer/2022062401/5a4d1b887f8b9ab0599bd7c2/html5/thumbnails/27.jpg)
IN OUTSELWR
IN OUTSELWR
IN OUTSELWR
IN OUTSELWR
IN OUTSELWR
IN OUTSELWR
IN OUTSELWR
IN OUTSELWR
IN OUTSELWR
IN OUTSELWR
IN OUTSELWR
IN OUTSELWR
IN OUTSELWR
IN OUTSELWR
IN OUTSELWR
IN OUTSELWR
IN OUTSELWR
IN OUTSELWR
IN OUTSELWR
IN OUTSELWR
IN OUTSELWR
IN OUTSELWR
IN OUTSELWR
IN OUTSELWR
IN OUTSELWR
IN OUTSELWR
IN OUTSELWR
IN OUTSELWR
IN OUTSELWR
IN OUTSELWR
IN OUTSELWR
IN OUTSELWR
DOUT3 DOUT3 DOUT3 DOUT3
3-to-8decoder
2
1
0
A2
A1
A0
0
1
2
3
4
5
6
7
DIN3 DIN3DIN3 DIN3
WE_LCS_L
OE_L
WR_L
IOE_L
0
1
1
![Page 28: CMPUT 229 - Computer Organization and Architecture I1 CMPUT229 - Fall 2002 Topic 2: Digital Logic Structure Jos Nelson Amaral.](https://reader036.fdocuments.in/reader036/viewer/2022062401/5a4d1b887f8b9ab0599bd7c2/html5/thumbnails/28.jpg)
IN OUTSELWR
IN OUTSELWR
IN OUTSELWR
IN OUTSELWR
IN OUTSELWR
IN OUTSELWR
IN OUTSELWR
IN OUTSELWR
IN OUTSELWR
IN OUTSELWR
IN OUTSELWR
IN OUTSELWR
IN OUTSELWR
IN OUTSELWR
IN OUTSELWR
IN OUTSELWR
IN OUTSELWR
IN OUTSELWR
IN OUTSELWR
IN OUTSELWR
IN OUTSELWR
IN OUTSELWR
IN OUTSELWR
IN OUTSELWR
IN OUTSELWR
IN OUTSELWR
IN OUTSELWR
IN OUTSELWR
IN OUTSELWR
IN OUTSELWR
IN OUTSELWR
IN OUTSELWR
DOUT3 DOUT3 DOUT3 DOUT3
3-to-8decoder
2
1
0
A2
A1
A0
0
1
2
3
4
5
6
7
DIN3 DIN3DIN3 DIN3
WE_LCS_L
OE_L
WR_L
IOE_L
0
1
1