CMP Process Development for the Via-Middle 3D TSV Applications at 28nm

Technology Node

UMC/ ATD_AM / CMP Department

T. C. Tsai, W. C. Tsao, Welch Lin, C. L. Hsu, C. L. Lin, C. M. Hsu, J. F. Lin, C. C. Huang and J. Y. Wu

2

Introduction

3

3D-TSV Integration Schemes

Before (CMOS) FEOL

After FEOL (Before BEOL)

(Via Middle)

Before Bonding(After BEOL)

After Bonding

IBM, NEC, Elpida, OKI, Tohoku, DALSA….

UMC, TI, TSMC,IMEC, Global Foundry, Tezzaron, Ziptronix…

ASE, Infineon, Zycube, IZM, …

Samsung, IBM,MIT LL, RTI, RPI….

Source: Yole Development; P. Pangaud, U. de la Méditerranée, CMOS Emerging Technologies Workshop, 2009

Via-Last Approach

Via-First Approach

4

Via-Middle TSV Process Flow

Through Silicon Via

RIE

Insulator Deposition

Barrier/Seed Deposition Via Filling

Cu/Ta-CMP OX/SiN CMP

Bondable metalStress-absorbing metalMechanically strengthened dielectrics

SiO2 (L1)

M1 M2

Cu_M3

Cu_MnIMD

PASVAl-pad (L2)

BEOL

q Via-middle between Cont and BEOL 3D-TSV scheme has become the mainstream for IC foundry.

5

Experimental

6

q 300mm blanket wafers with Si-substrate/ inter-layer dielectric (ILD) oxide layer/ SiN layer were prepared to form via-middle TSV structure wafers.

q The 70um deep TSVs with 10um diameter size were constructed with electrochemical deposition (ECD) of Cu film/ PVD Cu seed/ Ta(N) barrier/ SACVD oxide liner.

q Two Cu metal layers with 28nm BEOL design rule were stacked on TSV structures to evaluate the process impacts of the intrinsic TSV Cu extrusion on BEOL layers.

Experimental

7

Schematic of Via-middle TSV Structure Wafers post ECD Process

ECD Cu

ILD Oxide Layer

Si

SACVD Oxide LinerSIN CMP Stop Layer

Ta(N) Barrier

8

q The TSV CMP was carried out a rotary type polisher with three polishing platens.

q Three different kinds of silica based slurries were utilized to polish off 1). excess copper film on platen one; 2). Ta(N) barrier and oxide liner layers (stop on SiN layer) on platen two; 3). SiN layer (final stop on ILD oxide layer) on platen three.

q Varied pre-TSV CMP anneal temperatures (350C~410C) and ECD with different electroplating chemical solutions were investigated to eliminate the formations of the Cu extrusion and voids induced by BEOL thermal budget.

Experimental

9

Via-Middle TSV-CMP Potential Issues

q TSV recess, ILD range, T/P and defectivityare the key issues need to be fixed.

Platen 2

Polish Ti(Ta)/OX stop on SiN

OX/SiN Residue

Polish Cu stop on Ti(Ta)

ILDSIN

OXTiTa(N)

Cu

ILDSIN

OXTiTa(N)

ILD

SIN

OXTiTa(N)

Cu Residue/ Dishing

Polish SiN stop on ILD

Platen 3

Platen 1

ILD

OXTiTa(N)

ILD range/ Cu recess / Defectivity

10

q Cu film thickness before and after TSV CMP was detected by using a KLA RS-100 four point probe.

q ILD oxide layer thickness loss and range were measured by KLA F5x thin film measurement system.

q The TSV Cu recesses were characterized by using high-resolution atomic force profiler. The TSV structures post deep reactive ion etching (RIE), ECD and CMP processes were determined by using top and cross-sectional viewed SEM micrographs.

Experimental

11

Results and Discussion

12

Cross-sectional TSV SEM Pictures

a). b).

c).

d).

a). b).

c).

d).

q TSV with aspect ratio (AR) ~7 structures post (a~c) deep reactive ion etch (RIE) and (d) Electrochemical Deposition (ECD) steps.

13

Cu Peeling/Residue and OX/SiN Dielectric Residue Issues post TSV-CMP

Cu Peeling

Cu Residue

OX/SiN Residue

Cu Peeling

Cu Residue

OX/SiN Residueq Cu peeling/residue and OX/SiN dielectric residue found due to

unsuitable ECD and TSV CMP processes.

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Before and after Electrochemical Deposition (ECD) Cu THK Profiles Optimization

0

5000

10000

15000

20000

25000

30000

35000

-150 -120 -90 -60 -30 0 30 60 90 120 150W afer Diam eter from W afer C en ter (m m )

TS

V C

u T

hic

knes

s (A

)

Before Process T uning During Proce ss T uning Final Proc ess optimizat ion

0

5000

10000

15000

20000

25000

30000

35000

-150 -120 -90 -60 -30 0 30 60 90 120 150W afer Diam eter from W afer C en ter (m m )

TS

V C

u T

hic

knes

s (A

)

Before Process T uning During Proce ss T uning Final Proc ess optimizat ion

q The range of WiW Cu film thickness can be much improved from ~20000A to 1500A by ECD process optimization.

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qWtW and WiW ILD THK mapping range control can be <100A as ILD THK loss ~100A post P3 polishing.

ILD THK Range Control Performance post TSV-CMP Platen Three Polishing

Rem

ain

ing

ILD

TH

K (

A)

1900

1950

2000

2050

2100

2150

Wafer No.

#5 #7 #8#6

# 25

1850

#9 # 10

# 11

# 12

# 13

# 14

# 15

# 16

# 17

# 18

# 19

# 20

# 21

# 22

# 23

# 24

Rem

ain

ing

ILD

TH

K (

A)

1900

1950

2000

2050

2100

2150

Wafer No.

#5 #7 #8#6#5 #7 #8#6

# 25

1850

#9 # 10

# 11

# 12

# 13

# 14

# 15

# 16

# 17

# 18

# 19

# 20

# 21

# 22

# 23

# 24

Range = 65A

Range = 59A

16

TSV Cu Recess Level for Each Polishing Step(TSV Areas Marked by Red Cycles)

a ) . P re -T S V C M P b ) . P o s t P 1 p o lis h

c ) . P o s t P 2 p o l is h d ) . P o s t P 3 p o lis h

R e c e s s : ~ 5 2 0 0 A R e c e s s : ~ 3 3 0 A

R e c e s s : ~ 2 1 0 A R e c e s s : ~ 1 1 0 A

a ) . P re -T S V C M P b ) . P o s t P 1 p o lis h

c ) . P o s t P 2 p o l is h d ) . P o s t P 3 p o lis h

R e c e s s : ~ 5 2 0 0 A R e c e s s : ~ 3 3 0 A

R e c e s s : ~ 2 1 0 A R e c e s s : ~ 1 1 0 A

q The TSV Cu recess can be continuously reduced form around 330A to 110A as polishing through platen 1 to platen 3 TSV-CMP process.

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Cu Extrusion Found post TSV CMP Cap and Metal 3 Cap Layer Depositions

a).

~560A Cu extrusion (350C x 10 anneal)

~60A Cu extrusion (400C x 10 anneal)

Post Metal 3 Cap 95A Cu Extrusion

~560A Cu extrusion (Pre- 350C x 10min. Anneal)

Post Metal 3 Cap 95A Cu Extrusion

~60A Cu extrusion (Pre- 400C x 10min. Anneal)

q Severe Cu extrusion was easily found post TSV CMP cap and even post metal 3 cap layer deposition.

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Cu Extrusion Induced Metal/ULK Thinning and BEOL Peeling with Cu Voids

q Metal /ULK thinning were found due to Cu extrusion for pre - TSVCMP anneal condition.

M2V1

ULKM1/ V1/ ULK/ M2 Thinning

M1TSV Cu

Extrusion

TSV Si

M1

a).

b).

c).q Metal /ULK thinning were found due to Cu extrusion for pre - TSVCMP anneal condition.

M2V1

ULKM1/ V1/ ULK/ M2 Thinning

M1TSV Cu

Extrusion

TSV Si

M1

a).

b).

M2V1 M2

ULKM1/ V1/ ULK/ M2 THK Thinning

M1TSV Cu

Extrusion

TSV Si

M1

q Cu extrusion of TSV is indeed a potential concern to result in metal and ultra-low k (ULK) film thinning and delamination or damage of the BEOL.

19

Effects of pre-TSV CMP Anneal Condition on Cu Extrusion and Void Formation

350C x 10’(Post CMP)

350C x 10’(Post Cap)

400C x 10’(Post CMP)

f).

W/O Anneal

No Anneal (Post CMP)

350C x 20’(Post CMP)

410C x 20’(Post CMP)

(Post CMP)

(Post Cap)

(Post CMP)

f).

(Post CMP)

(Post Cap)

(Post CMP)

W/O Anneal

No Anneal (Post CMP)

(Post CMP) (Post CMP)

W/O Anneal

No Anneal (Post CMP) (Post CMP) (Post CMP)

q Increasing pre-TSVCMP anneal temp. could reduce Cu extrusion, but induce Cu voids issue.

20

Effects of Different ECD Chemical Solutions on TSV Cu Voids (400Cx10 min. Anneal)

Chemical Solution 1 Chemical Solution 2

0

0.2

0.4

0.6

0.8

1.0

C Cl O N SImpurities of the Cu ECD

Chemical SolutionsN

orm

aliz

ed Im

pu

rity

C

on

cen

trat

ion

Chemical Solution 1Chemical Solution 2

0

0.2

0.4

0.6

0.8

1.0

C Cl O N SImpurities of the Cu ECD

Chemical SolutionsN

orm

aliz

ed Im

pu

rity

C

on

cen

trat

ion

Chemical Solution 1Chemical Solution 2

q TSV Cu voids can be eliminated by reducing the impurities of the Cu electrochemical deposition (ECD) chemical solutions.

21

Conclusions

22

Conclusions

q Via-middle between Cont and BEOL 3D-TSV scheme has become the mainstream for IC foundry.

q WiW Cu film thickness range can be much improved from ~20000A to 1500A by ECD process optimization.

q WtW and WiW ILD THK mapping range control can be <100A as ILD THK loss ~100A post P3 polishing.

q TSV Cu recess can be continuously reduced from around 330A to 110A as polishing through platen 1 to platen 3 TSV-CMP process.

23

Conclusions

q Severe Cu extrusion was easily found post TSV CMP cap and even post metal 3 cap layer deposition.

q Cu extrusion of TSV is indeed a potential concern to result in metal and ultra-low k (ULK) film thinning anddelamination or damage of the BEOL.

q Increasing pre-TSVCMP anneal temperature could reduce Cu extrusion, but induce Cu voids issue.

q TSV Cu voids can be eliminated by reducing the impurities of the Cu electrochemical deposition (ECD) chemical solutions.

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Thank You!