CMOS Transistor Theory Lec7

Advanced VLSI DesignLecture 7: CMOS Transistor Theory

Shaahin HessabiDepartment of Computer Engineering

Sharif University of TechnologyAdapted with modifications from lecture notes from

Rutgers university

Advanced VLSI Design Slide 2 of 29Sharif University of Technology

OutlineIntroductionMOS CapacitornMOS I-V CharacteristicspMOS I-V CharacteristicsAdjustments for non-ideal 2nd-order effects


IntroductionSo far, we have treated transistors as ideal switches

An ON transistor passes a finite amount of currentDepends on terminal voltagesDerive current-voltage (I-V) relationships

Transistor gate, source, drain all have capacitanceI = C (ΔV/Δt) -> Δt = (C/I) ΔVCapacitance and current determine speed


MOS CharacteristicsMOS – majority carrier deviceCarriers: e-- in nMOS, holes in pMOSVt – channel threshold voltage

(cuts off for voltages < Vt)


nMOS Enhancement Transistor

Moderately doped p type Si substrateTwo heavily doped n+ regions


I vs. V Plots

Enhancement and depletiontransistors

CMOS: uses only enhancement transistorsnMOS – uses both


MOSFET TransistorsFor given Vds & Vgs, Ids controlled by:

Distance between source & drain LChannel width WVt

Gate oxide thickness tox

ε gate oxideCarrier mobility μ


MOS CapacitorGate and body form MOS capacitorOperating modes

AccumulationDepletionInversion

polysilicon gate

(a)

silicon dioxide insulator

p-type body+-

Vg < 0

(b)

+-

0 < Vg < Vt

depletion region

(c)

+-

Vg > Vt

depletion regioninversion region


Terminal VoltagesMode of operation depends on Vg, Vd, Vs

Vgs = Vg – Vs

Vgd = Vg – Vd

Vds = Vd – Vs = Vgs – Vgd

Source and drain are symmetric diffusion terminalsBy convention, source is terminal at lower voltage (NMOS)Hence Vds ≥ 0

nMOS body is grounded. First assume source is 0 too.Three regions of operation

CutoffLinearSaturation

Vg

Vs Vd

VgdVgs

Vds+-

+

-

+

-


nMOS CutoffNo channelIds = 0

+-

Vgs = 0

n+ n+

+-

Vgd

p-type body

b

g

s d


nMOS LinearChannel formsCurrent flows from d to s

carriers (e- for nMOS) from s to d

Ids increases with Vds

Similar to linear resistorAt drain end of channel, only difference between gate & drain voltages effective for channel creation

+-

Vgs > V t

n+ n+

+-

Vgd = V gs

+-

Vgs > V t

n+ n+

+-

Vgs > V gd > V t

Vds = 0

0 < V ds < V gs-Vt

p-type body

p-type body

b

g

s d

b

g

s d Ids


nMOS SaturationChannel pinches offIds independent of Vds

We say current saturatesSimilar to current source

+-

V gs > V t

n+ n+

+-

Vgd

< Vt

Vds

> Vgs

-Vt

p-type body

b

g

s d Ids


I-V CharacteristicsIn Linear region, Ids depends on

How much charge is in the channel?How fast is the charge moving?


Channel ChargeMOS structure looks like parallel plate capacitor while operating in inversionQchannel = CVC = Cg = εoxWL/tox = CoxWLAverage gate to channel potential:

V = Vgc – Vt = (Vgs – Vds/2) – Vt

n+ n+

p-type body

+

Vgd

gate

+ +source

-

Vgs

-drain

Vds

channel-

Vg

Vs Vd

Cg

n+ n+

p-type body

W

L

tox

SiO2 gate oxide(good insulator, εox = 3.9)

polysilicongate

Cox = εox / tox

Vgc=(Vgs+Vgd)/2 = (Vgs-Vds/2)


Carrier Velocity

Charge is carried by e-Carrier velocity υ proportional to lateral E-field between source and drainυ = μE μ called mobilityE = Vds/LTime for carrier to cross channel:

t = L / υ


nMOS Linear I-VNow we know

How much charge Qchannel is in the channelHow much time t each carrier takes to cross

c h a n n e l

o x 2

2

d s

d sg s t d s

d sg s t d s

QIt

W VC V V VL

VV V V

μ

β

=

⎛ ⎞= − −⎜ ⎟⎝ ⎠

⎛ ⎞= − −⎜ ⎟⎝ ⎠

o x = WCL

β μ

Current ∝ Vgs-Vt since Vgs-Vt sets the number of carriers in the channelCurrent ∝ Cox ∝ 1/toxCurrent ∝ W/L Resistance ∝ L/W


nMOS Saturation I-VIf Vgd < Vt, channel pinches off near drain

When Vds > Vdsat = Vgs – Vt

Now drain voltage no longer increases current

( )2

2

2

dsatds gs t dsat

gs t

VI V V V

V V

β

β

⎛ ⎞= − −⎜ ⎟⎝ ⎠

= −


nMOS I-V Summary

( )2

cutoff

linear

saturatio

0

2

2n

gs t

dsds gs t ds ds dsat

gs t ds dsat

V VVI V V V V V

V V V V

β

β

⎧⎪ <⎪⎪ ⎛ ⎞= − − <⎜ ⎟⎨ ⎝ ⎠⎪⎪

− >⎪⎩

Shockley 1st order transistor models


Ideal Quadratic NMOS I-V Curve


ExampleUsing a 0.6 μm process from AMI Semiconductor

tox = 100 Åμ = 350 cm2/V*sVt = 0.7 V

Plot Ids vs. VdsVgs = 0, 1, 2, 3, 4, 5Use W/L = 4/2 λ

( )14

28

3.9 8.85 10350 120 /100 10ox

W W WC A VL L L

β μ μ−

−

⎛ ⎞• ⋅ ⎛ ⎞= = =⎜ ⎟⎜ ⎟⋅ ⎝ ⎠⎝ ⎠

0 1 2 3 4 50

0.5

1

1.5

2

2.5

Vds

I ds (m

A)

Vgs = 5

Vgs = 4

Vgs = 3

Vgs = 2Vgs = 1


pMOS I-VAll dopings and voltages are inverted for pMOSMobility μp is determined by holes

Typically 2-3x lower than that of electrons μn

Thus pMOS must be wider to provide same current

In this class, assume:μn / μp = 2


Non-ideal I-V EffectsThe saturation current increases less than quadratically with increasing Vgs

Caused by 2 effects:1. velocity saturation: at high lateral

field strengths (Vds/L), carrier velocity ceases to increase linearly with E.

lower Ids than expected at high Vds.

2. mobility degradation: at high vertical field strengths (Vgs/tox), the carriers scatter more often less current than expected at high Vds.


Channel length modulationThe saturation current increases slightly with Vds.

Reason: higher Vds increases the size of the depletion region around the drain effectively shortens the channel.


Leakage CurrentSources of leakage current in nominally OFF transistors:

1. Subthreshold conduction: at Vgs < Vtthe current drops off exponentially, rather than abruptly becoming zero.

Vt itself is influenced by Vsb, called body effect.

2. Junction leakage: source and drain diffusions are reverse-biased diodes with respect to substrate or well.

3. Tunneling through the gate: as the thickness of gate oxide decreases, electrons tunnel through the gate (Ig > 0).


Gate Leakage Current


Velocity Saturation and Mobility Degradation

At high field strengths, drift velocity rolls off due to carrier scattering and saturates at υsat:υ = μ Elat/(1+ Elat/ Esat)

υsat = μ Esat• 6-10 x 106 cm/s for electrons

saturation field: 2 x 104 V/cm for NMOS transistors.

• 4-8 x 106 cm/s for holes.

Saturation current for completely velocity saturated transistors (υ = υsat): Ids = Cox W (Vgs – Vt) υsat

Current is linearly (rather than quadratically) dependent on voltage.


Velocity Saturation (cont’d)α-power law model:

0; Vgs < Vt cutoff Ids = Idsat Vds/Vdsat ; Vds < Vdsat linear

Idsat ; Vds > Vdsat saturation

Long channel transistors or low VDD: quadratic I-V characteristics in saturation (α =2).α decreases to 1 for velocity-saturated transistors.α also takes into account the mobility degradation.For short channel transistors, the lateral field increases (unless VDDdecreases) and transistor becomes more velocity saturated.

• No performance benefit to raising VDD

• Two transistors in series deliver more than half the current of a single transistor.PMOS transistors experience less velocity saturation.


Temperature DependenceBoth mobility and threshold voltage decrease with rising temperature.

μ decrease (important for ON transistor) lower Ids at high T.Vt decrease (important for OFF transistor) higher leakage current at high T.

MOS characteristics degrade with temperature.


Geometry DependenceLeff = Ldrawn + XL -2LD Weff = Wdrawn + XW -2WD

XL:manufacturer’s adjustment (usually negative)LD: lateral diffusion under the gate

A transistor drawn twice as long may have an effective length that is more than twice as great current is less than half. Other reasons for this:

Vt increases for longer transistors less currentLong transistors experience less channel length modulationless current

For current matching, use the same L and W for all devices; make current ratios by tying identical transistors in parallel.

CMOS Transistor Theory Lec7

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