CMOS polycrystalline silicon circuits on steel substrates

Ming Wu *, Sigurd Wagner

Department of Electrical Engineering and Center for Photonics and Optoelectronic Materials, Princeton University,

Princeton, NJ 08544, USA

Abstract

We report the fabrication and performance of complementary metal-oxide-silicon (CMOS) circuits made from

polycrystalline silicon films on steel substrates. The steel substrate was coated with �0.5 lm SiO2 for planarization and

insulation. The polysilicon film was crystallized from a-Si:H at 750 �C in 2 min. The n- and p-channel transistors and

circuits were made with a self-aligned process and ion-implanted source/drain. The field-effect mobilities were �20

cm2=V s for electrons and �15 cm2=V s for holes. Inverters and ring oscillators operate in the MHz range. These results

lay the groundwork for a circuit technology based on furnace processing on non-breakable and flexible substrates and

with performance much better than that of amorphous silicon. � 2002 Published by Elsevier Science B.V.

PACS: 85.30.Tv; 85.40.)e; 81.10.Jt

1. Introduction

Electronics on flexible substrates are becomingincreasingly interesting for applications in flexibleflat panel displays, mechatronics, and sensitive skin,etc. [1,2]. Thin film transistors (TFTs), circuits, anddisplay backplane matrices made from hydroge-nated amorphous silicon (a-Si:H) have been fab-ricated on flexible substrates of plastic or steel[3–5]. Putting polycrystalline silicon (polysilicon)circuits on flexible substrates is desirable for driv-ing high current loads such as entire a-Si:H TFTactive matrices or organic light emitting diodes(OLEDs). With its n- and p-channel capability,polysilicon can be made into CMOS circuits

for low-power-consumption applications. Devicequality polysilicon films are formed by crystalli-zation of a-Si using furnace annealing [6], rapidthermal annealing via lamp heating [7], and laserannealing [8–10]. We chose furnace annealing be-cause it is a batch process and is isothermal, andthus produces polysilicon films with uniformtransport properties over an entire plate. The hightemperature tolerance of steel substrate allowsfurnace crystallization in much shorter times [11]than conventional glass substrate [12,13]. Forthese reasons, n- and p-channel polysilicon TFTshave been made on steel substrates [14,15], andcrystallization times as short as minutes or secondshave been demonstrated [15]. Here we show thatCMOS polysilicon circuits on steel can operate at1 MHz, which is a further step toward polysilicon-on steel technology for rugged and flexible back-planes for large area electronics.

Journal of Non-Crystalline Solids 299–302 (2002) 1316–1320

www.elsevier.com/locate/jnoncrysol

* Corresponding author. Tel.: +1-609 258 5902; fax: +1-609

258 1840.

E-mail address: mingwu@ee.princeton.edu (M. Wu).

0022-3093/02/$ - see front matter � 2002 Published by Elsevier Science B.V.

PII: S0022 -3093 (01 )01153 -X

2. Experiments

We describe first the preparation of polycrys-talline silicon films on steel, and then the fabrica-tion of CMOS circuits. A 200 lm thick foil ofAISI grade 304 stainless steel (Fe/Cr/Ni 72/18/10wt.%) was cleaned with acetone and methanol. Toreduce the roughness of the steel foil surface, a 210nm thick planarizing film of spin-on glass (Film-troics, Butler, PA, Grade 500 F) was applied toboth sides and cured. Then a 270 nm thick film ofSiO2 was deposited on both sides by plasma-enhanced chemical vapor deposition (PECVD) ata substrate temperature of 250 �C. The planarizedand encapsulated substrate was heated in a tubefurnace from 450 to 800 �C at a rate of 5 �C/min.Fig. 1 shows the scanning electron micrographs of(a) an as-rolled bare AISI 304 steel surface and (b)the substrate surface coated with the �0.5 lm SiO2

layer after anneal. The �0.5 lm thick insulationlayer reduced the RMS surface roughness mea-sured by AFM from 5 nm for bare steel foil to <2nm. Next, a 160 nm thick a-Si:H precursor filmwas deposited by PECVD at a substrate temper-ature of 150 �C. For crystallization, the samplewas first heated at 450 �C for 30 min in flowing N2

gas, then brought to 750 �C and heated for 2 min.The transfer and temperature ramping time wasmeasured by a thermocouple to be less than 1 s.Completion of crystallization was monitored exsitu by measuring the ultraviolet reflectance at

k ¼ 276 nm [7,16]. The electrical conductivity ofthe polysilicon film was �10�6 S=cm, i.e., which iscomparable to that of intrinsic polysilicon crys-tallized on glass [17] and suggests the absence ofelectrically active impurities introduced from thesteel substrate.

TFTs and circuits were fabricated in a top-gateco-planar configuration with self-aligned ion-implanted source and drain [11]. Device fabrica-tion started with the definition of the polysiliconfilm into individual TFT islands by reactive ionetching (RIE). The 150 nm SiO2 gate dielectricwas deposited by PECVD at 350 �C, followed by200 nm a-Si:H deposited at 270 �C for the gate.The a-Si:H and SiO2 were patterned by RIE andthen wet etched to define source/drain. �1 lmAZ5214 photoresist was patterned by photoli-thography as the nþ ion-implant mask, and thesource and drain of the n-channel TFTs were im-planted with phosphorus at 50 keV and a dose of2 � 1015 cm�2. After the nþ photoresist mask wasremoved, another photoresist layer was appliedand patterned as the pþ ion-implant mask. Thesource and drain of p-channel TFTs were im-planted with boron at 35 keV and a dose of 2�1015 cm�2. After photoresist removal the samplewas cleaned in a mixture of sulfuric acid and hy-drogen peroxide. The implant damage was an-nealed out at 750 �C for 30 min, and the samplewas immersed in a hydrogen glow discharge at 350�C for 1 h. A 200 nm passivation SiO2 was applied

Fig. 1. Scanning electron micrographs of (a) as-rolled AISI 304 steel surface and (b) the steel surface coated with �0.5 lm SiO2

planarization layer.

M. Wu, S. Wagner / Journal of Non-Crystalline Solids 299–302 (2002) 1316–1320 1317

at 250 �C and wet etched to open the contactwindows. 300 nm Al was evaporated and pat-terned for source/drain and gate electrodes andinterconnections. Finally, the TFTs and circuitswere annealed at 250 �C for 15 min in forming gas(15 vol% hydrogen and 85 vol% nitrogen mixture).

3. Results and discussion

TFTs and the dc characteristics of CMOS in-verters were evaluated with an HP 4155 semicon-ductor parameter analyzer while the steel foil waskept flat and grounded. The transient character-istics of the CMOS inverters and ring oscillatorswere evaluated with a Tektronix 3200 digital os-cilloscope using very low capacitance probes.

The transfer characteristics (drain current IDS

against gate-source voltage VGS) of typical n- andp-channel polysilicon TFTs are plotted in Fig.2(a). Both TFTs have channel width W ¼ 60 lmand length L ¼ 2 lm. We calculated the thresholdvoltage Vth and the electron and hole field effectmobilities in the linear regime le;lin and lh;lin fromthe linear plot of the drain current IDS against gate-source voltage VGS at drain–source voltage VDS of0.1 V or )0.1 V. The TFTs have le;lin ¼ 20 cm2=V s and lh;lin ¼ 15:3 cm2=V s, respectively. The off

currents of the n- and p-channel TFTs are 23pA=lm and 1:2 pA=lm of channel width, and thedrain current ON/OFF ratios are 106 and 107 forthe n- and p-channel TFTs, respectively. The Vth ofthe n-channel TFT is 3.1 V while the thresholdvoltage of the p-channel TFT is 22 V, an asym-metry reported earlier for polysilicon TFTs onglass made by furnace crystallization [18]. Fig. 2(b)shows the effect of channel length on the n- and p-channel TFT linear mobilities and threshold volt-ages. Measured on channels 1–15 lm long, theelectron linear mobility ranges from 28 to16 cm2=V s, while the hole linear mobility lies at�15 cm2=V s. n-channel TFTs with channel lengthL6 2 lm shows substantially better performancethan the TFTs with longer channels. This resultsuggests that either the grain size of the polysiliconfilm is of the order of 2 lm or that the 1 h hy-drogenation following ion-implantation is notlong enough for long TFT channels. Polysiliconfilms crystallized at 600 �C had a grain size of �2lm [19] and a film crystallized at 950 �C had agrain size of �0.5 lm [20]. Normally the grain sizeof furnace-annealed polysilicon decreases with in-creasing crystallization temperature. The grain sizeof our film lies between 0.1–0.2 lm (from AFM),0:5 lm (from electron microscopy), and 2 lm(from Fig. 2(b)).

Fig. 2. (a) Transfer characteristics of p- and n-channel polysilicon TFTs on steel with channel width W ¼ 60 lm and length L ¼ 2 lm.

(b) Linear mobilities and threshold voltages of n- and p-channel TFTs plotted vs. channel length.

1318 M. Wu, S. Wagner / Journal of Non-Crystalline Solids 299–302 (2002) 1316–1320

We made CMOS polysilicon-on-steel invertersand ring oscillators. Fig. 3(a) is the optical mi-crograph of a CMOS inverter on steel made of n-and p-channel TFTs with channel width W ¼60 lm and length L ¼ 2 lm, and Fig. 3(b) shows

the transient characteristics of the inverter. At asupply voltage VDD ¼ 30 V, this inverter operatesat 1.0 MHz. The fall and rise times are 130 and 190ns, respectively. These values are consistent withthe calculated RC time constants composed of the

(a) (b)

Fig. 3. (a) Optical micrograph of a polysilicon CMOS inverter on steel, made with n- and p-channel TFTs of channel length L ¼ 2 lm.

Note reflection from the rough interface between the steel and the transparent planarization layer. (b) AC characteristics of the inverter

operating at 1.0 MHz.

Fig. 4. (a) Five-stage ring oscillator operating at 1.03 MHz with supply voltage VDD ¼ 30 V. (b) Oscillation frequency and amplitude

as functions of supply voltage.

M. Wu, S. Wagner / Journal of Non-Crystalline Solids 299–302 (2002) 1316–1320 1319

transistor channel resistance and the 1 pF loadcapacitance between the output metal pad and thesteel substrate.

Fig. 4(a) shows the transient characteristics of afive-stage CMOS ring oscillator, made of p- and n-TFTs with channel width W ¼ 60 lm and lengthL ¼ 4 lm. At the supply voltage VDD ¼ 30 V, thisoscillator oscillates at 1.03 MHz. As shown in Fig.4(b), the oscillator starts oscillating when VDD isP 17 V. The oscillation frequency increases from30 KHz to 1.03 MHz with increasing supplyvoltage, and the oscillation amplitude saturates at�7 V.

4. Conclusions

We fabricated polycrystalline silicon thin filmtransistor circuits on flexible steel substrates. Thepolysilicon was formed by furnace crystallizationof hydrogenated amorphous silicon at 750 �C/2min on SiO2 coated steel substrates. The electronand hole mobilities in the linear regime are �20cm2=V s. CMOS polysilicon circuits operating at 1MHz were fabricated. These results suggest thatpolysilicon-on-steel technology can furnish rug-ged, large-area, and flexible TFT backplanes withthe performance required for driver and matrixcircuits of displays, sensor arrays, and mechatronicmaterials.

Acknowledgements

This research is supported by DARPA’s HDSand MLP programs. The authors thank ProfessorStephen J. Fonash for sharing the cost of maskfabrication at the Penn State NanofabricationFacility and Professor James C. Sturm of Prince-

ton University for many helpful discussions. MingWu thanks the Princeton Plasma Physics Labo-ratory for a fellowship.

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