Cmos Fully Integrated Heterodyne RF Receivers

7/31/2019 Cmos Fully Integrated Heterodyne RF Receivers

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Cmos Fully IntegratedHeterodyne RF Receivers

BySonam kandalgaonkar


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Contents

IntroductionOverview of receiver architectures

Proposed receiver architectureConclusionReferences


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Introduction

RF circuit designers are facing an increasingdemand for low-cost and small size circuits.

Many efforts are ongoing on the integration of RF receivers in low-cost CMOS technologies.

Fully integrated 5GHz RF receivers haverecently been implemented.


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Contd..

Objective: The feasibility of implementing fullyintegrated heterodyne 5GHz front end receiversin a standard CMOS 0.18m technology.

It does not use automatic tuning, DC offsetcancellation or calibration circuits.

The main idea relies on cascading two imagereject notch filters, which results in strong andwide bandwidth image rejection.


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Overview of Receiver Architecture

The specifications of 5GHz RF receivers forthe 802.11a WLAN

applications aresummarized in Table 1.Different RF receiverarchitectures that couldmeet theserequirements have beenintroduced


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Receivers Architecture


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Contd..

Figure 1a shows the basic structure of a homodynereceiver. In this scheme, the RF signal is directly downconverted by the mixer to baseband.As a result, the image signal is the same as the RFsignal, and this type of architecture does not suffer fromthe image problem.The noise performance of a homodyne receiver is alsoaffected by the 1/f noise.The noise limitations of homodyne receivers can bemitigated by employing architectures with intermediatefrequency (IF), such as the Weaver architecture or theimage-reject topology .


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Weaver architectureShown in Fig. 1b, the Weaver receiver exploits the factthat the image and the desired signal are out of phaseafter down conversion.By down converting the detected RF signal through twodifferent paths using a set of quadrature mixers,cancellation of the image signal can be realized.This technique would offer a suitable solution for

implementing 5GHz front-end receivers, only if perfectmatching in the gains and phases of the two paths couldbe achieved5GHz frequency range, a CMOS Weaver architecturepractically generates only between 25 to 35 dB of imagerejection.


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Image reject mixer basedarchitecture

Shown in Fig. 1c, the image-reject downconverter is yet another implementation of an IFhomodyne receiver.

It uses constant gain broadband 90 degreesphase shifters


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Heterodyne structures


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Contd..

Typically, a heterodyne receiver employs off-chip image reject filters, which increases thecost and the complexity of the overall design.The first IF (2.6GHz) of the receiver is set athalf the frequency of the RF input signal (5.2GHz), while the second IF is chosen to be atbaseband.As a result, at the first mixer, the image signal isat very low frequencies (DC), and therefore isheavily attenuated by the antenna and theprefiltering RF blocks.


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Proposed Architecture


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Contd..Figure 3 shows the proposed architecture.

The signal detected by the antenna is typically inthe micro-volts range, which explains the needof preamplifying it before further processing.This task is performed by a low-noise amplifier(LNA) which, in this work, incorporates dualimage reject notch filters. For a 5.2GHz receiverwith a 1GHz IF, and a mixer frequency of 6.2GHz, the image signal would lie in thevicinity of 7.2GHz.Finally, by adding two notches to the LNA, awide image rejection bandwidth is obtained, and

no extra notch tunning circuits are needed.


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Double balanced mixer


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Contd..The mixer used in the front-end is shown in Fig. 5.It is implemented as a double balanced active Gilbertstructure.The linearity of the mixer was maximized by groundingthe sources of the differential RF input pair.Current sources I1 and I2 were added in order to decreasethe biasing currents of the switching transistors M1-M4,thus reducing their noise, while ensuring a proper biasingof the RF differential pair.Finally, a complementary-gm voltage controlled oscillatorwas used for the LO+ and LO- signals generation .


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Simulation results


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Summary


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ConclusionA new approach for implementing 5GHz front-end heterodyne receivers was proposed.

The circuit does not employ automatic circuitsnor off-chip components.

Simulation results showed that the specificationsfor the IEEE 802.11a WLAN standard can bemet using a standard CMOS technology.


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referencesK. Lee and M.N. El-Gamal A very low-voltage

(0.8V) CMOS receiver frontend for 5GHz RFapplications, Proceedings of the 2002 IEEE

International Symposium on Circuits and Systems,pp. 125 -128, May 2002.H. Samavati, H.R. Rategh, and T.H. Lee, A 5-

GHz CMOS wireless LAN receiver front end, IEEE Journal of Solid-State Circuits, Vol. 35, pp.765-772, May 2000.J.R. Long, A low-voltage 5.1-5.8-GHz image-

reject downconverter RF IC, IEEE Journal of Solid-State Circuits, Vol. 35, pp. 1320-1328, Sep.2000.


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Any Questions ?????


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Thank you

Cmos Fully Integrated Heterodyne RF Receivers

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