cmos amplifier design.pdf

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CMOS Low Noise Amplifier DesignOptimization Technique

Trung-Kien Nguyen, Nam-Jin Oh, Hyung-Chul Choi, Kuk-Ju Ihm, and Sang-Gug Lee

Information and Communications University119 Munjiro, Yuseong-gu, Daejeon, 305-714 South [email protected]

Abstract

In this paper, a set up noise parameter expression and the third order intermodulation product expression (IM3)for a power-constrained simultaneous noise and inputmatching low noise amplifier design optimizationtechnique are introduced. Based on these expressions,the methodology to design LNA to archive the power-constrained simultaneous noise and input matching aswell as satisfy the linearization condition is explained. Inadditional, the power gain is enhanced by using a verysimple positive feedback. The proposed LNA for 5GHzWLAN applications is fabricated based on 0.18 mCMOS technology. Measured results show 20 dB power gain, 1.5 dB NF and –5 dBm IIP3. The proposed LNAdissipates DC current of 3 mA at supply voltage of 2.5V.

1. Introduction

With the recent proliferation of wireless transceiver applications, there is an extensive effort to develop low

cost, highly integrated RF circuits. CMOS has become acompetitive technology for radio transceiverimplementa-tion due to the technology scaling, higher level of integrability, lower cost, etc. [1]. In typicalreceiver architectures, a low noise amplifier (LNA) is theone of the most critical blocks that determines thesensitivity of wireless receiver systems [2-[4]. Normally,LNA design involves the tradeoff between noise figure(NF), gain, linearity and power consumption.Consequently, the goal of LNA design is to achievesimultaneous noise and input matching at any givenamount of power dissipation as well as satisfy thelinearization conditions. The LNA design optimization

technique proposed in [4] can be applied for power-constrained simultaneous noise and input matching.However, as discussed in [4], the fully potential of thistechnique is not provided clearly. This paper attempts toanalyze and provide clear and perspe-ctive understandingone of the LNA design optimization techniques, namely power-constrained simultaneous noise and inputmatching technique. The analyses are based on the noise parameter expressions and the expression for the third order intermodulation product (IM3). By using thoseexpressions, the design principle, advantages and practical limitation for the mentioned LNA technique areexplained. In additional, in this paper, the power gain of the LNA is improved by using simple positive feedback technique. The simple positive feedback is implemented by one additional capacitor connected from drain

terminal of the cascode transistor to that of commonsource transistor. The description of the methodology for LNA design optimization and the proposed LNA arediscussed in detail in section 2 and 3, respectively. The proposed LNA for 5 GHz WLAN applications isfabricated based on 0.18 m CMOS technology.Measured results show 20 dB power gain, 1.5 dB NF and –5 dBm IIP3. The proposed LNA dissipates the DC

current of 3 mA at supply voltage of 2.5 V.

2. Methodology for Low Noise Amplifier Design

A. Noise Optimization Analysis

Figure 1-a shows the schematic of a cascode LNAtopology that is adopted to explain the PCSNIM LNAdesign technique. The LNA shown in Fig. 1-a differs byone additional capacitor C ex in comparison with thetypical cascode LNA.

M 2

M 1

C ex

Ls

Matching Circuit

Lg

Rss Z '

vs

V bias

id

(a)

C

+

-

g gsgC ex2ngi

gsv

gsvgm 2nd i

Ls

Lg Matching Circuit

Z in Z s

Rss Z '

id

2nsv

(b)

Fig. 1. Simple cascode LNA to adopt the PCSNIM technique(a) and its small-signal equivalent circuit (b)

This LNA topology was first introduced in [3] as asolution to reduce the noise figure of the LNA at low power dissipation, however, the potential and thetheoretical analysis as a power-constrained (i.e., low power) simultaneous noise and input matchable LNAtopology has not been recognized. Fig. 1-b shows thesimplified small-signal equivalent circuit of the cascode

amplifier shown in Fig. 1-a for the noise analysis. In Fig.1-b, the effects of common-gate transistor M 2 on thenoise and frequency response are neglected [2]. Thenoise parameter expressions for a circuit with series



feedback, shown in Fig. 1-b, can be obtained by applyingthe Kickoff’s law [1]. The results are simple enough to provide useful insights as shown below [5]

2

2

0 2

22

2 2 2 2

1 15

11

15

15

eff

t g s

d

eff

t sm s

eff

m t s g

s C L L | c |

g

F sC R |c |g R

c g sC R sL

(1)

221 1

5min

T

F (

| c | ) (2)

2

22

2

55 1

55 1

t

gs

opt s

t

gsgs

C j c

C ( c ) Z sL

C C c

C ( c )

(3)

1n

m

Rg

(4)

where C t = C gs1+C ex

As can be seen from (2) and (4), F min and Rn are notaffected by the addition of C ex. In other word, by usingC ex, the minimum noise figure and the noise resistanceexpressions for power-constrained simultaneous noiseand input matching technique are the same as those in[3]. From Fig. 1-(b), the input impedance of the LNA isgiven by

1m s

in s

t t

g L

Z sL sC C (5)

In (5), the source degeneration generates real part atthe input impedance. This is important because there isno real part in the input impedance without degenerationwhile there is in the optimum noise impedance.Therefore, Ls helps to reduce the discrepancy betweenthe real parts of the optimum noise impedance and theLNA input impedance. Furthermore, from (5), theimaginary part of Z in is changed by sLs, and this isfollowed by nearly the same change in Z opt in (3),especially with advanced technology considering thevalue of c is higher than 0.4 (e.g., c 0.5 with 0.25 m

technology), and becomes lower than 1 [6]. Now, for the circuit shown in Fig. 1-(a), the conditions

that allow the simultaneous noise and input matching are

2

22

2

5 1Re[ ]

55 1

s

t gs

gs

( c ) Z

C C c

C ( c )

(7)

22

2

5Im

55 1

t

gs

s s

t gs

gs

C j c

C sL Z

C C cC ( c )

(8)

Re[ ]m ss

t

g L Z

C (9)

1Im

s s

t

sLsC

Z (10)

As mentioned above, for the advanced CMOStechnology parameters, (8) is approximately equal to

(10). Therefore, (10) can be dropped, which means thatfor the given value of Ls, the imaginary value of theoptimum noise impedance becomes approximately equalto that of the input impedance with opposite sign. Nowthen, the design parameters that can satisfy (7)-(9) areV GS , W (or C gs), Ls, and C ex. Since there are threeequations and four unknowns, (7)-(9) can be solved for an arbitrary value of Z s, by fixing the value of one of thedesign parameters that can be the power dissipation or V GS . In other word, this LNA design optimizationtechnique allows to design simultaneous noise and inputmatching at any given amount of power dissipation.

B Linearity Analysis

In RF circuit design, the linearity is another importantaspect to consider. Since LNA is the first block in thetypical receiver system, the linearity of the LNA iscommonly estimated by the third order intermodulation

product. Two signals of adjacent channels Asin 1 and Asin 2 will generate products IM3 such as Asin(2 1- 2)

and Asin(2 2- 1) at the output of nonlinear circuit. IM3

usually calculated in the literature as the ratio of intermo-dulation of the third order and the response magnitude of the fundamental frequency which is given by

3 1 22

1

23

3 4

A

IM A A

(11)

where A1, A3 are the first order and third order coefficientof Volterra series.

Rss Z '

sv

C

+

-gs

gsvgsvg

m1

Ls

Lg Matching Circuit

Z s

C exinv

Z in

id

Y o1

gm2

Fig. 2 Circuit model for nonlinear analysis

For linearity analysis purpose, the equivalent smallsignal circuit of LNA in Fig. 1 is depicted in Fig. 2.

Now, M 2 can be considered and modeled by the seriestrans-conductance gm2, assuming r ds2 >> Rout . In this case,the effects of the C gs2 and C gd1 have been neglected. Theoutput admittance seen at the drain of M 1, Y o1, is added inthe model with the purpose to identify the outputcontribution. Using the Kickoff’s law in the model of Fig. 6 the input signal can be written as

1 2in gs d v s v a s i a s (12)

Where 1 1t in sa s sC Z sL (13)

12

2

1 os

m

Y a s sL

g

(14)



When the effective mobility reduction is taken intoaccount, the current between the source and drainterminals of the transistor M 1 is given as

2

1 2

sat ox gs t o

ds

gs t sat

Wv C V V I

V V Lv

(15)

where 1 2o sat Lv and gs GS gV V v s Here, V GS is the DC bias voltage of the transistor, vgs is

the small signal between gate and source, and vsat is thecarrier velocity saturation. Using (12), the Volterra seriesexpression of id is derived as

(16) 2 31 2 1 2 3 1 2 3d in ini A s v A s ,s v A s ,s ,s v in

Here the coefficients of order higher than three areignored. Usually, the adjacent channel frequencies 1and 2 providing the intermodulation products are veryclose to the fundamental frequency therefore s s1 s2

can be assumed. The |IM3| at (2 1 - 2) is

321 2

3 1 331 3 22 m

A s A

IM a s g g Bg 2 (17)

2 1 2 12 2 2 2 2s s s B sL s a A s sL s a s A s (18)

11

1 1 2

m

m

g A s

a s g a s

(19)

2 20

2 3

1

4

2

sat

gs t sat

K L vg

V V Lv

,

2 20

3 4

1

4

2

sat

gs t sat

K L vg

V V Lv

(20)

1 2s s s

where g2 and g3 are the second and third degreecoefficients of the transistor nonlinear Taylor expansion.The B coefficient is the second-order interaction of the

products 2 , 1- 2, and 2- 1. A1(s) is the transcon-ductance of the circuit. Substituting (19) into (17), itshows the dependence of | IM3| with inverse of the term

3

11

2

1 ot in s m

m

Y sC R sL g

g

(21)

As can be seen in (17), the linearity can be improved byusing different ways. Revising (17), the | IM3| can belowered with the reduction of a1(s), g3, or with theincrease (21). As shown in (13), with inductivedegeneration the s

2C t Ls term will cancel the “1” term,

and as a result a1(s) is reduced. This indicates that theselected topology is more adequate to keep the | IM3|

small in comparison with resistive and capacitivedegeneration topology, where such cancellation does notexist. The joint effect of g3 and g2 coefficients in | IM3| isinversely dependent on the bias (V gs-V t ), indicating thatthe linearity can be improved by increasing gate sourcevoltage. However, increasing the gate source voltage willincrease the power dissipation. With large Y o1 and gm1

values and small gm2 value (21) is increased such that thelinearity will be increased. For the same reason, anyincrease in C t , preserving the matching condition in theinput circuit, also improves the linearity.

C. Design Consideration

In this section, the overall consideration for LNAdesign to obtain power-constrained simultaneous noiseand input matching as well as linearization is described.

The qualitative description of the proposed design process would be as follows. First, choose the DC bias,V GS , for example the bias point that provides minimumF min. Second, choose the transistor size, W , based on the power constraint, P D. Third, choose the additionalcapacitance, C ex, as well as the degeneration inductance,

Ls, to satisfy (7), (9), and s

2

C t Ls = -1 conditions (asmentioned, to improve the linearity of circuit thecondition s

2C t Ls = -1 need to be satisfied). With the given

Ls the condition Im[ Z in*] = Im [ Z opt ] is automatically

satisfied. At this point, the simultaneous noise and inputmatching is achieved. As the last step, if there exists anymismatch between Z in and Z s

’, as shown in Fig. 1 (b), animpedance matching circuit can be added.

This design optimization technique suggest that, byusing an additional capacitor, Cex, the LNA can bedesigned to archive power-constrained simultaneousnoise and input matching as well as satisfy thelinearization condition. The limitations of the PCSNIM

technique are high Rn and low effective cut-off frequency. High Rn can be a serious limitation for the practical high yield LNA design.

3. Gain Enhancement Technique and Proposed LNA

One of the simple ways to improve the power gain ofLNA is using positive feedback. In this paper, the positive feedback is realized by C f shown in Fig. 3-a.This phenomenon can be understood by another point ofview as the form of oscillator. In Fig. 3-a, C gs1, C f , and M 2 constitutes an oscillator topology with inductivetermination at the output [1]. The effect of the positivefeedback will increase maximum available gain of the

cascode amplifier at high frequencies. Note that noadditional active device is used therefore no more DC power is dissipated and no noise is contributed. The limitto amount of feedback is governed by stabilityconsideration. To ensure the stability condition, Gtol mustalways positive. This technique is first introduced in [7];however, the reported results are simulation-based only.This paper tries to realize this idea in term of measured results. The simplified proposed LNA is shown in Fig. 3- b. The proposed LNA is implemented by combining thePCSNIM design technique described in previous sectionand the gain enhancement technique shown in Fig. 3-a.In the Fig. 3-b, the simple L

o-C

o network represents the

output-matching network and Lo is implemented by off chip inductor.

RFin

Ls

M 2

V DD

M 1

Lg

Lo C o RFout

C ex

C f M 1

V DD

V

Lo C o RFout

C f

bias

C gs1

i1

V bias

(b)(a)Fig. 3 Gain enhancement technique and the proposed LNA



4. Measurement Results

To demonstrate the potential of power-constrained simultaneous noise and input matching optimizationtechnique and the gain enhancement technique, thecurrent dissipation of the proposed LNA is fixed at 3mA. Three LNA versions are fabricated based on 0.18

m CMOS technology, the first circuit is simple cascodeinductive degeneration topology, the second one simplecascode with C ex and the third one is the proposed LNAshown in Fig. 3. Note that, all the circuits are designed atthe same power dissipation. A Comparison of measured NF results are shown in Fig. 4. As can be shown in Fig.4, by using the power-constrained simultaneous noiseand input matching technique, the obtained NF is lower than that for the case of simple cascode inductivedegeneration. The main reason of the improvement in NF

can be understood as the discrepancy between real partsof input and noise matching conditions

0.5

1

1.5

2

2.5

3

3.5

4 4.5 5 5.5 6 6

Freq [GHz]

N o i s e F i g u r e [ d B ]

.5

Fig. 4 Measured NF of LNAs

0

5

10

15

20

25

4 4.5 5 5.5 6 6.5

Freq [GHz]

P o w e r G a i n [ d B ]

Fig. 5 Measured power gain of LNAs

Fig. 5 shows the measured results comparison of twoLNAs simple cascode and proposed LNA shown in Fig.3-b. As can be seen from Fig. 5, the power gain isimproved by 3 dB compare to that of simple cascodetopology. Fig. 6 shows the measured result of input third order intermodulation product of the proposed LNA. The proposed LNA has power gain of 20 dB, NF of 1.5 dB at

5.25 GHz and IIP3 of –5 dBm. The microphotograph of the three circuits is shown in Fig. 7.

5. Conclusion

In this paper, a very simple and insightful set of noise parameter expressions and the third order intermodu-lation product for the power-constrained simultaneousnoise and input matching LNA design optimizationtechnique is newly introduced. Based on those expres-sions, the design principle, advantage, and the limitation

for the power-constrained simultaneous noise and inputmatched technique are explained. To demonstrate the potential of this design technique, the proposed LNA isdesigned and optimized for 5 GHz WLAN applications.The measured results show good agreement withtheoretical analysis.

-110

-80

-50

-20

10

40

-40 -30 -20 -10 0 10

Input Power [dBm]

O u t p u t

P o w e r [ d B m ]

Fundamental

IM3

With Cex

Without Cex

Fig. 6 IIP3 of the proposed folded cascode LNA

Fig. 7 Microphotograph of the three LNA: (a) simple cascode,(b) simple cascode includes C ex, and (c) proposed LNA

References

[1] B. Razavi, “CMOS technology characterization for analog and RF

design,” IEEE Journal of Solid- State Circuits, Vol. 34, pp. 268-276,March 1999.

[2] S. P. Voinigescu et al., “A Scalable High-Frequency Noise Model for Bipolar Transistors with Application Optimal Transistor Sizing forLow-Noise Amplifier Design,” IEEE J. Solid- state Circuits, Vol. 32, pp 1430-1439, Sep 1997.

[3] D. K. Shaeffer et al., “A 1.5V, 1.5 GHz CMOS Low Noise Amplifier”,IEEE Journal of Solid-Stage Circuits, Vol. 32, pp 745-758, May 1997.

[4] G. Girlando et al., “Noise Figure and Impedance matching in RFCascode Amplifiers,” IEEE Transaction on Circuits and Systems-II,Vol. 46, pp. 1388-1396, Nov. 1999.

[5] Trung-Kien Nguyen, et al., “CMOS Low Noise Amplifier DesignOptimization Techniques,” Accepted to be published on IEEETransactions on Microwave Theory and Technique, May 2004.

[6] G. Knoblinger et al., “A New Model for Thermal Channel Noise of Deep-Submiron MOSFET and its Applications in RF-IC Design,”IEEE Journal of Solid- State Circuits, Vol. 36, pp. 831-837, May2001.

[7] K. L. Chan, et al., “1.5 V 1.8 GHz Bandpass Amplifier,” IEESymposium of Circuits Devices and Systems pp. 331-333, Dec. 2000.

With Cf

Without Cf

(a) (b)

(c)

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