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Institut de Microlectroniqueet Microsystmes

Research review 2003, Institute of Microelectronics and Microsystems

FULLY DIFFERENTIAL CURRENT-MODE LOGIC CIRCUITS AND

INTERCONNECTS FOR VERY HIGH-SPEED SYSTEM DESIGN

Keywords: Current mode logic (CML), signal integrity, capacitive and inductive coupling

Personnel: S. Badel, Z. Toprak, I. Hatirnaz, Y. LeblebiciPartners:

Funding: EPFL

Laboratory/groupand contact (e-mail):

Microelectronic Systems Laboratory (LSM)yusuf.leblebici@epfl.ch

Recent research indicates that differential cur-rent mode logic (MCML) circuits offer signifi-cant advantages in terms of switching speed(clock frequency > 5 GHz) in deep submicronCMOS technologies, while providing improvednoise immunity and limited power dissipation.However, these advantages have not beenfully exploited in high-speed VLSI design,mainly due to the lack of standard cell librariesand implementation platforms, and due to thedifficulties of integrating the fully differentialbuilding blocks into the classical digital VLSIdesign flow.

One of the goals of this project is to explore thedesign of a comprehensive cell library that con-

sists of current-mode logic primitives, and tovalidate circuit performance under realistic op-erating conditions. Initial results indicate thatswitching speeds of up to 8 GHz are feasibleusing inductive / non-inductive peaking tech-niques. The power dissipation of MCML gatesbecomes comparable to that of classicalCMOS logic gates at switching frequenciesaround 2 GHz. Additional advantages of cur-rent-mode design include reduced voltageswing operation, and significant suppression ofpower supply noise due to the fact that thesupply current is constant. This property can

be exploited very effectively for the design ofDPA-resistant logic blocks, there power supplycurrent variations can be effectively masked forimproved data security.

The design of fully differential high-speed logiccircuits also requires completely symmetric inter-connect architectures with reduced capacitive andinductive coupling properties. An extensive model-ing and simulation effort has already been con-ducted, resulting in the design special twisted dif-ferential line (TDL) structures to suppress cou-pling noise between neighboring lines. It has beenshown that the magnitude of crosstalk can be re-duced by two orders of magnitude by properchoice of TDL structures and shielding. Furtherresearch will concentrate on the design of regulararray architectures using CML logic elements andan optimized interconnect fabric, as well as thedevelopment of a top-down design flow to exploitthe advantages of differential logic.

1. I. Hatirnaz and Y. Leblebici, Twisted Differ-ential On-Chip Interconnect Architecture forInductive/Capacitive Crosstalk Noise Cancel-lation, International Symposium on System-on-Chip 2003, Tampere, Finland, November2003.