CLOCK GATINGW A T MAHESH DANANJAYA

CLOCK GATING

• Major dynamic power reduction technique

• Gate the clock as much as the flop is not necessary to be toggled

• Otherwise in every clock cycle flop will toggle and dissipate more power

• Local clock gating has a new enable to every flop where clock gating is

necessary

• But with complex VLSI design it is not sustainable to use local clock

gating

• We need to derive a logic for new enable with the current logic

LOCAL CLOCK GATING

• Local enable is used to gate the flop

• Enable and clock are and gated and the gated clock is provided to the flop

• Local enable, do not have a global perception

AND

FLOP

D Q

Enable

Clock

Data IN Data Out

CLOCK GATING METHODS

• Latch Based Clock Gating

• Latch Free Clock Gating

AND

FLOP

D Q

Enable

Clock

Data INData Out

Gated CLK

AND

FLOP

D QEnable

Clock

CLK

Data OutData CLK D Q

FLOP

Gated CLK

MULTI LEVEL BOOLEAN LOGIC

• Satisfiability Don’t Care (SDC)

• Design spots where certain input/ input combination to a circuit can never

occur. There may be possible causes for the SDC conditions.

• Observability Don’t Care (ODC)

• Design spots where local changes cannot be observed at the

primary outputs.

NEW TRENDS OF CLOCK GATING• Based on the multi level Boolean logic derivations

• There are two ways of clock gating to derivate new enable based on the input and output logics.

• Stability Condition (STC)

• Stability condition is defined with the stability of the input to the flop when upstream flop is stable, no

new data or changes come to the downstream flop

• Observability Don’t Care (ODC)

• There are Situations where the output of the flop is changing or staying constant, but that output is

not used in the downstream and read only for a certain time period of time

STABILITY CONDITION (STC)• Stability condition is defined as stability of the input to the flop when

upstream flop is stable, no new data or changes come to the downstream

flop.

• If the input to the flop is not changing with the (Stable) for a period of time,

there is no use of toggling the flop for state changes.

• In such situation input to the flop is just remain constant thus output of the

flop also stable without changing.

• Then we can stop providing clock to the flop and save more powerEN1

Upstream register

Downstream register

STABILITY CONDITION (STC)

• Before STC

• After STC

EN

CLK

CLK

EN

OBSERVABILITY DON’T CARE (ODC)

• There are Situations where the output of the flop is changing or staying

constant, but that output is not used in the downstream and read only for a

certain time period of time.

• Then toggling and state changes of the flop for entire time period is not

required.

• Therefore we can shut down that flop for a relevant time period where the

output of the flop will not be read and unnecessary.

• And we can reactivate the flop when someone is actually reading its output.

0

1Q

OBSERVABILITY DON’T CARE (ODC)

• Before ODC

• After ODC

SEL

0

1Q X

CLK

SEL

0

1Q X

CLOCK GATING EFFICIENCY & ENABLE STRENGTHENING

• Most of the devices have explicit or already instantiated clock enables in the digital

designs according to records advanced SOC designs such as mobile application

units is recommended to have around 90% of clock gating cross designs.

• Although the digital designs consist of explicit or instantiated clock enables, all of

them are not efficient and provided an efficient clock gating.

• Therefore modern approaches are focusing on finding a new enable which

strengthen the existing enable.

• This process and new enable are often known as Enable Strengthening and the

Strengthened Enable respectively.

• Basis behind this approach is to strengthen the existing one with new one, if the

percentage of power reduction through the new enable surpasses the existing

enable.

ENABLE STRENGTHENING

• There are two types of strengthening methodologies based on the logic

they are acquired.

• Strong STC

• In a gated flop, if the input is not changing for a period of time and the flop is still clocking or

toggling then we can find out a condition for causing input to be stable. We can use this

new logic to strengthen the existing enable.

• Strong ODC

• In a gated flop, if the output is not read for a period of time but the flop is still clocking, we

can find out the conditions for output not t be observed. Then we can enable the existing

enable with this new logic. This is known as strong ODC.

MEMORY POWER REDUCTION

Most off the digital systems are associated with memory systems. There are

different techniques for memory power reduction.

• Remove redundant read

• Remove redundant write

• Memory as steering point for register power reduction

• Light sleep power reduction

REDUNDANT READ REMOVAL

• Any read access occurring when the memory output is not observable is a

redundant read and can be removed based on the ODC technique.

•   And also if the read address is stable then every read after the first one is

redundant, if no new address write is taken. This is based on the STC techniques.

REDUNDANT WRITE REMOVAL

• If the data and write addresses are stable, then ever write

access after the first one is redundant and can be removed