CLASSICAL LOGIC 2 3 4 5 SRFPGA layout With I/O pins 6 Var1 var2 var3 var4 var5 var6 var7 var8 var9 var10 var11 var12 var13 var14 var15 var Input test vector InputtestvectorInputtestvector Test output TestoutputTestoutput Faults observed during column test C = 2. Faults observed during diagonal test D = 2 Total number of Faults N = C * D = 2 * 2 = 4. REVERSIBLE LOGIC 7 A logic gate is reversible if Each input is mapped to a unique output It permutes the set of input values A combinational logic circuit is reversible if it satisfies the following: Has only one Fanout, Uses only reversible gates, No feedback path, has as many input wires as output wires, and permutes the input values. 8 9 NOT gate a b a c Controlled-NOT or Feynman gate 10 a b c a b f Toffoli gate (Controlled-Controlled NOT gate) 11 Swap gate Implementation of Swap gate using controlled-NOT 12 Swap gate Implementation of Swap gate using controlled-NOT 13 a b c a f g Fredkin gate (Controlled SWAP gate) 14 MMD: Transformation based Gupta-Agrawal-Jha: PPRM based Mishchenko-Perkowski: Reversible wave cascade Kerntopf: Heuristics based Wille: BDD based synthesis 15 16 c b ac o b o a o PPRM form for each output in terms of Input variables are given as follows and node is created PPRM form for each output in terms of Input variables are given as follows and node is created Parent node is explored by examining each output variable in the PPRM expansion. Factors are searched in the PPRM expansions that do not contain the same input variable. For example in the expansion below appropriate terms are c and ac The substitution is performed as In this example OR 17 18 19 New nodes are created based on substitution 20 21 22 Common problem with current approaches: they invariably use nxn Toffoli gates, that might imposes technological limitations. High Quantum cost of Toffoli gates with many inputs. Synthesize only reversible functions, not Boolean functions that is not reversible. 23 24 Implementation of 4x4 Toffoli gate with Quantum realizable 2x2 primitives such as controlled-V, controlled-NOT, controlled-V +. CREATING QUANTUM ARRAY FROM LATTICE 25 26 Positive Davio Tree can be created by expanding PPRM function using positive Davio expansion. Positive Davio Lattice is created by performing joining operation for neighboring cells at every level. Other Lattices can be created using similar method but using expansions such as Shannon or Negative Davio expansions or combination of them. On the previous foils I showed representation of the Davio and Shannon cells as cascade of reversible gates. Next I present unique method to create Quantum Array from Positive Davio Lattice. The same approach can be used for other Lattices. 27 28 Each node represents pDv cell. d d a d b b 1 a a c 1 30 a b c d a1 ad1 bab1 d a aabdb adabddb1 bddab bcdcdacbcabdaddb1 garbage function 31 a b c d a1 ad1 bab1 d a aabdb adabddb1 bddab bcdcdacbcabdaddb1 garbage function 32 Each node represents pDv cell. 33 Reversible circuit synthesized with only 3x3 Toffoli gates. Generates reversible circuit for any ESOP. Adds ancilla bits but overall cost of the circuit will be lower due to use of low cost 3x3 Toffoli gates. 34 35 36 37 DIPAL GATES, DIPAL GATE FAMILIES AND THEIR ARRAYS 38 39 40 a b c cabaf a b c cabaf cb a Shannon cell Dipal cell representation with reversible gates There are 2 3 ! = 8! = x3 Reversible logic functions, however only handful of them shown earlier are useful for synthesis purpose. Dipal gate is a reversible equivalent of Shannon cell Dipal gate is a reversible equivalent of Shannon cell 41 a b c bacaf a b c a cb bacaf Shannon cell with negative variable Dipal cell with negative variable represented with reversible gates 42 a b c cabaf a b c cabaf cb a Shannon cell Dipal cell representation with reversible gates There are 2 3 ! = 8! = x3 Reversible logic functions, however only handful of them shown earlier are useful for synthesis purpose. Dipal gate is a reversible equivalent of Shannon cell Dipal gate is a reversible equivalent of Shannon cell cbaa inputoutput 45 EXPERIMENTAL RESULTS 46 47 Benchmark#Real inputs #Garbag e inputs #Gates Lattice Cost Lattice CPU time Lattice #Gates DMM Cost DMM #Gates AJ Cost AJ 2to rd323148< rd < _ < sym NA 5mod < mod541618< ham33037< xor55044< Xnor55155< decod < Cycle10_ ham 48 Benchmark#Real inputs #Garbage inputs #Gates Lattice Cost Lattice CPU time Lattice #Gates DMM Cost DMM #Gates AJ Cost AJ graycode66555< graycode < graycode < nth_prime3_ inc 3446< nth_prime4_ inc < nth_prime5_ inc alu52517< _ hwb < hwb hwb pprm144933< 49 Benchmark#Inputs#Gates pDv Lattice Cost pDv Lattice #Gates Shannon Lattice Cost Shannon Lattice 2to rd rd _ sym mod mod Ham xor Xnor Decod Cycle10_ Ham 50 Benchmark#Inputs#Gates pDv Lattice Cost pDv Lattice #Gates Shannon Lattice Cost Shannon Lattice Graycode Graycode Graycode nth_prime3_ inc nth_prime4_ inc nth_prime5_ inc Alu _ Hwb Hwb Hwb Pprm 51 52 Fig. 2. Circuit for function FX2 created with our method for traditional cost function calculation that does not take Ion Trap technology constraints into account. 53 Fig. 3. Circuit from Figure 2 modified with adding SWAP gates for new cost function calculation that does take Ion Trap technology constraints into account, with XX gates added. It has 36 SWAP gates added to realize LNNM. 54 55 Example of Positive Davio Lattice from [Perkowski97d]. Positive Davio Expansion is applied in each node. Variable d is repeated 56 Transformation of function F3(a,b,c) from classical Positive Davio Lattice to a Quantum Array with Toffoli and SWAP gates. Each SWAP gate is next replaced with 3 Feynman gates.(a) intermediate form, (b) final Quantum Array. 57 58 59 General layout of the layered diagram Each box represents a gate from family of Dipal gate 60 61 Benchmark#Gates Lattice Cost Lattice #Gates with SWAP insertion for Lattice Cost with SWAP gates for Lattice #Gates DMM Cost DMM #Gates with SWAP insertion for MMD Cost with SWAP gates for MMD 2to rd rd _ sym mod mod Ham Xor Xnor decod Cycle10_ Ham 62 Benchmark#Gates Lattice Cost Lattice #Gates with SWAP insertion for Lattice Cost with SWAP gates for Lattice #Gates DMM Cost DMM #Gates with SWAP insertion for MMD Cost with SWAP gates for MMD Graycode Graycode Graycode2019 Nth_prime3 _inc Nth_prime4 _inc Nth_prime5 _inc Alu _ hwb hwb hwb pprm GENERALIZED REGULARITIES FOR QUANTUM AND NANO- TECHNOLOGIES 63 64 (a)(b)(c) (d) 65 66 67 68 69 70 71 72 73 QUANTUM CIRCUITS AND QUANTUM ARRAYS FROM TRULY QUANTUM GATES 74 Basic single qubit quantum gates 75 Transformation of the circuit realized in Fig. 7 using Toffoli gate. Each Toffoli and SWAP gates are replaced by quantum CNOT and CV/CV+ quantum gates and rearranged to satisfy the neighborhood requirements of Ion trap. 76 The transformations of blocks of quantum gates to the pulses level. 77 CONCLUSIONS 78 Experimental results proved that our algorithm produced better results in terms of quantum cost compared to other contemporary algorithms for synthesis of reversible logic. New gate family called Dipal gate Presented new synthesis method with layered diagrams. More accurate technology specific cost model for 1D qubit neighborhood architecture. 79 A new method based of lattice diagram to synthesize reversible logic circuit with 3x3 Toffoli gates. A new method based of lattice diagram to synthesize reversible logic circuit with 3x3 Toffoli gates. A new family of gates called Dipal Gates. A new family of gates called Dipal Gates. New diagrams called layered diagram that uses family of Dipal gate for synthesis of reversible logic function. New diagrams called layered diagram that uses family of Dipal gate for synthesis of reversible logic function. Software for creating Lattice diagrams and software for creating quantum array from Lattice (Lattice to QA). Software for creating Lattice diagrams and software for creating quantum array from Lattice (Lattice to QA). Program to implement a variant of MMD algorithm. Program to implement a variant of MMD algorithm. 80