Class Notes (Part 1) - University of Reginazhang/201-09/classnotes1.pdf · ... The function truth...

Class Notes (Part 1)

CS201

Dr. C. N. Zhang Department of Computer Science

University of Regina Regina, SK, Canada, S4S 0A2

C. N. Zhang, CS400 2

I. DIGITAL CIRCUITS

1 Binary Algebra and Gates

1.1 Binary Algebra

An algebra that deals with binary variables and logic operations.

� All variables take on two discrete values 1 and 0 (binary variable).

� There are three basic operations: OR, AND, NOT de�ned as follows:

AND OR NOT

X Y X.Y

0011

0101

0001

X Y X+Y

0011

0101

0111

X

01

10

X

Figure 1: Truth tables of the three basic operations.

1.2 Logic Gates

X

YZ = X . Y Z = X + Y X

X

YX

AND gate OR gate NOT gate or INVERTER

AB F = ABCC

Three-input AND gate

F = A + B + C + D

Four-input OR gate

ABCD

X 0 10 1

Y 0 01 1

(AND) X . Y

0 11 1(OR) X + Y

0 00 1

1 01 0(NOT) X

Figure 2: Some logic gates and their timing diagrams.


2 Boolean Function and Simplification

� Boolean function: Boolean function consists of an algebraic expression formed with

binary variables, the constants 0 and 1, the logic operation symbols, parentheses, and an

equal sign. For a given value of the binary variables, the Boolean function can be equal

to either 1 and 0.

� Duality function f: f� is obtained by interchange OR and AND operators and

replacing 10s and 00s and 00s and 10s.

� Duality principle: if f1 = f2 then f�

1 = f2�

If f�1 and f�2 are duality functions of two Boolean functions f1 and f2, then f�

1 = f2�

2.1 Truth Table

A tabular representation of the Boolean function f(x1; : : : ; xn). It consists of a list of 2n

combinations of the n binary variables and a column that shows the values of the function.

F = X + Y Z

Table 1: The function truth table.

x y z F

0 0 0 0

0 0 1 1

0 1 0 0

0 1 1 0

1 0 0 1

1 0 1 1

1 1 0 1

1 1 1 1

2.2 Logic Circuit Diagram

Logic circuit diagram is logic gate implementation of a Boolean function. For example,

X

Y

Z

F

Figure 3: Logic circuit diagram for F = X + Y Z.


2.3 Basic Identities of Boolean Algebra

1. X + 0 = X

3. X + 1 = 1

5. X + X = X

7. X + X = 1

9. X = X

10. X + Y = Y + X

12. X + (Y + Z) = (X + Y) + Z

14. X(Y + Z) = XY + XZ

16. X + Y = X . Y

2. X . 1 = X

4. X . 0 = 0

6. X . X = X

8. X . X = 0

11. X . Y = Y . X

13. X . (Y . Z) = (X . Y) . Z

15. X + Y . Z = (X + Y) . (X + Z)

17. X . Y = X + Y

Commutative

Associative

Distributive

DeMorgan Law

Figure 4: Basic identities of Boolean Algebra.

� All of these identities can be proved by truth table. For example, (X + Y ) = X � Y

Table 2: Truth tables to verify DeMorgan's theorem.

X Y X + Y X + Y X Y X Y X � Y

0 0 0 1 0 0 1 1 1

0 1 1 0 0 1 1 0 0

1 0 1 0 1 0 0 1 0

1 1 1 0 1 1 0 0 0

� Simpli�cation of Boolean functions using basic identities.

Example 1:F = XY Z +XY Z +XZ

= XY (Z + Z) +XZ by (14)

= XY � 1 +XZ by (7)

= XY +XZ by (2)

X

Y

Z

FF

X

Y

Z

F = X Y Z + X Y Z + X Z F = X Y + X Z

Figure 5: Implementation of the Boolean function with gates.


Example 2:

XY +XZ + Y Z = XY +XZ + Y Z(X +X by (7)

= XY +XZ +XY Z +XY Z by (14)

= XY +XY Z +XZ +XY Z by (12)

= XY (1 + Z) +XZ(1 + Y ) by (14)

= XY +XZ by (7)

Example 3:

(A+B)(A+ C) = AA+AC +AB +BC by (14)

= AC +AB +BC by (8)

= AC +AB +ABC +ABC by (1 and 14)

= AC(1 +B) +AB(1 + C) by (14)

= AC +AB by (3)

Example 4:

(A+ C)(B + C) = AB +AC +BC + CC by (14)

= AB +AC +BC + C by (6)

= AB + (A+B + 1)C by (14)

= AB + C by (3)

� Find complement of Boolean function.

The complement of Boolean function f(x1; : : : ; xn) denoted by f (x1; : : : ; xn) can be ob-

tained by the following approaches:

1. Approach-1 (based on truth table): The truth table of f(x1; : : : ; xn) can be

obtained from the truth table of f(x1; : : : ; xn) by exchanging the values of 0 to 1

and 1 to 0 in the function value column.

2. Approach-2 (apply DeMorgan Law repeatedly):

Example-1: Find complement of function F = XY Z +XY Z.

F = XY Z +XY Z

= (XY Z) (XY Z)

= (X + Y + Z) (X + Y + Z)

= XX +XY +XZ +XY + Y Y + Y Z +XZ + Y Z + ZZ

= X +XY +XZ +XY + Y Z +XZ + Y Z

= X (1 + Y + Z + Y + Z + Y ) + Y Z + Y Z

= X + Y Z + Y Z


Example-2: Find complement of function F = X (Y Z + Y Z).

F = X(Y Z + Y Z)

= X + Y Z + Y Z

= X + Y Z � Y Z

= X + (Y + Z) � (Y + Z)

= X + ZY + ZY

3. Approach-3:

First, �nd dual of f , f�, and then complete each variable of f�

Example: Find complement of function F = X (Y Z + Y Z)

F � = X + (Y + Z)(Y + Z)

F = X + (Y + Z)(Y + Z)

= X + Y Z + Y Z

� Time delay of a gate: It is the time duration from the time of input signals arrived to

the time of output signal established. Example: NOT gate (5 � 10ns); AND and OR

gate (10� 20ns).

A B

∆t

5V

5V

t

t

5 ns < < 10 ns∆t

Figure 6: Time delay of an inverter.

� Time delay of logic circuit: It adds up the time delay of all gates on a path from

input to output which requires longest time delay.

� Logic circuit cost: It depends on:

{ number of gates required

{ number of inputs for each gate

� Minimum cost logic circuit design:

{ minimum number of gates with minimum total number of inputs

� Goal of logic circuit design:

{ minimum cost and minimum time delay


3 Simplification Using Map

3.1 Minterms and Maxterms

� Minterms: It is a product term in which all the variables (either complemented or

uncomplemented) appear exactly once.

� Maxterms: It is a summation term in which all variables (either complemented or

uncomplemented) appear exactly once.

Example:

X Y Z

00001111

00110011

01010101

XXXXXXXX

YYYYYYYY

ZZZZZZZZ

Product Term Symbol Sum Term Symbol

mmmmmmmm

0

1

2

3

4

5

6

7

MMMMMMMM

0

1

2

3

4

5

6

7

X + Y + ZX + Y + ZX + Y + ZX + Y + ZX + Y + ZX + Y + ZX + Y + ZX + Y + Z

MINTERMS MAXTERMS

Figure 7: Minterms and maxterms for three variables.

� Relationship: The minterm and maxterm have relationship as follows:

mi =M i

3.2 Two Canonical Forms

Any Boolean function can be expressed as a unique sum of minterms or as a unique product

of maxterms. For example, �nd two canonical forms of E(X;Y;Z) = XY + Z.

1. Sum of minterms.

E(X;Y;Z) = XY + Z

= XY (Z + Z) + (X +X)(Y + Y )Z

= XY Z +XY Z +XY Z +XY Z +XY Z +XY Z

= XY Z +XY Z +XY Z +XY Z +XY Z

= � (m0 +m1 +m3 +m5 +m7)

= � m(0; 1; 3; 5; 7)


2. Product of maxterms.

E(X;Y;Z) = XY + Z

= (X + Z)(Y + Z)

= (X + Z + Y Y )(Y + Z +XX)

= (X + Y + Z)(X + Y + Z)(X + Y + Z)(X + Y + Z)

= �M4 �M6 �M2

= � M(2; 4; 6)

Note:

if f(x1; x2; : : : ; xn) = �m(i1; i2; : : : ; in), then f(x1; x2; : : : ; xn) = �M(j1; j2; : : : ; jn), where

fi1; i2; : : : ; ikg + fj1; j2; : : : ; jlg = f0; 1; : : : ; 2n � 1g and jm 6= in for all 1 � m � l and

1 � n � k.

3.3 Two Standard Forms of Boolean Functions

� Sum of Products (SOP) Form:

Any Boolean function can be expressed by a summation of product terms.

� Product of Summations (POS) Form:

Any Bollean function can be expressed by a product of summation terms.

Where each product term and each summation term may have one, two, or any number

of variables (literals).

Example-1: Rewrite the function F = AB + C(D + E) in SOP form.

F = AB + C(D + E)

= AB + CD + CE

Example-2: Rewrite the function F = AB + C(D + E) in POS form.

F = AB + C(D + E)

= (A+ C(D + E))(B + C(D + E))

= (A+ C)(A+D + E)(B + C)(B +D + E)

� OR-AND implementation:

Any Boolean function in POS form can be implemented by an OR-AND two level net-

work, where OR gate corresponds to the summation term and AND gate is for the logic

product.

Example: F = X(Y + Z)(X + Y + Z).

Note: term of X does not need an OR gate.


XY

Z

X

Z

YF

Figure 8: The logic gate for F = X(Y + Z)(X + Y + Z).

� AND-OR implementation:

Any Boolean function in SOP form can be implemented by an AND-OR two level net-

work. Each product term requires an AND gate, the logical sum is formed with an OR

gate.

Example: F = AB + CD + CE.

D

CF

C

E

A

B

Figure 9: The logic gate for F = AB + CD + CE.

3.4 Two-Level Minimum Cost Designs

� Simpli�ed SOP Expression: It is a SOP form with a minimum number of products

and each product has the fewest number of literals.

F = AB +ABC +ABC +B

is a SOP but not simpli�ed, because:

F = AB +B

= A+B

� Simpli�ed POS form: It is a POS form with minimum number of summation terms

and each summation term has the fewest number of literals.

F = (A+B)(B + C)(A+ C)(B + C)

is not a simpli�ed POS form, because:

F = (A+ C)(A+B)(B + CC)

= (A+ C)B


3.5 Karnaugh Map

Karnaugh map is a table made up of squares, each of which represents one minterm of a

function.

� Two variable map.

m 0 m 1

m 2 m 3

0 1

1

0

XY 0 1

1

0

XY

X Y

X Y X Y

X Y

Y

X

X

Y

Figure 10: Two variable map.

� Three variable map.

m 0 m 1

m 4 m 5

00 01

1

0

X

YZ

m 3 m 2

m 7 m 6

11 10

X Y Z

00 01

1

0

X

YZ11 10

X Y Z X Y Z X Y Z

X Y Z X Y Z X Y Z X Y Z

Y

Z

X

Figure 11: Three variable map.

� Four variable map.

m 0 m 1

m 4 m 5

00 01

00

WX

YZ

m 3 m 2

m 7 m 6

11 10 00 01WX

YZ11 10

12 13

m 8 m 9

15 14

m 11 m 10

m m m m

01

11

10

00

01

11

10

Z

Y

W

X

Figure 12: Four variable map.


3.6 Map Manipulation

� The key idea in the formation of the map is that any two horizontally and vertically

adjacent squares corresponding to two minterms di�er in one variable only.

Note: Adjacency of the map includes right-most, left-most, top-most, and down-most.

Example-1: In the three variable map, m0 and m2 are adjacent, and we have:

m0 = XY Z

m2 = XY Z

m0 +m2 = XZ

Example-2: In the four variable map, m0, m2, m8, and m10 are adjacent, and we have:

m0 +m2 +m8 +m10 = WXY Z +WXY Z +WXY Z +WXY Z

= WXZ +WXZ

= XZ

Note: In general, if there are 2k adjacent squares, then their corresponding product has

n� k variables.

� Prime Implicant: It is a product term corresponding to a 2k adjacent squares in the

map in which at least one square is not adjacent to any other adjacent squares (excluding

any sub adjacent squares of these adjacent squares).

Example: Consider f(X;Y;Z) = �m(1; 3; 4; 5).

0 1

1

1

1 0 0

0

00 01 11 10

0

1

X

YZ

m 1 m 3 m 2m 0

m 5 m 7 m 6m 4

Figure 13: Map for example �m(1; 3; 4; 5).

There are three adjacent squares: (m4;m5), (m1;m5), and (m1;m3). Their corresponding

products are XY , Y Z, and XZ, respectively.

We say that XY is a prime implicant because there is only one square, m4, which does

not belong to these adjacent squares, (m4;m5). Similarly, XZ is a prime implicant. On

the other hand, Y Z is not a prime implicant because all its squares, (m1;m5), belong to

other adjacent squares (m1 belongs to (m1;m3), and m5 belongs to (m4;m5)).


� Procedure (�nding simpli�ed SOP form):

1. Make '1' for those squares corresponding to the minterms of the function, mark the

rest of squares by '0'.

2. Find all adjacent squares which correspond to prime implicants (the number of

adjacent squares is power of two) and circle them together, write down their corre-

sponding products.

3. Find the largest adjacent squares on the map, circle them together, and write down

the corresponding products. Repeat this step until all 1's have been circled.

4. List all products and write them in SOP form.

Note:

{ Any square marked by '1' can be selected more than once, but at least once.

{ If there are 2k squares adjacent together, then k variables should be eliminated.

Example-1: F (X;Y;Z) = �m(1; 2; 3; 4; 5)

1. '1' is marked in each minterm of the function.

2. Find all possible adjacent squares which correspond to a prime implicant in the map,

write down the corresponding products, i.e., XY and XY .

3. There is only one square uncircled in the map (i.e.,m1). The largest adjacent square

which includes m1 can be (m1;m5) or (m1;m3). Since both of them have the same

number of squares (i.e., two), we can pick up any one of them. Let (m1;m5) be the

chosen square and Y Z be the product. Now all squares marked by '1' have been

circled.

4. Write down the function in sum of product form: F = XY +XY + Y Z.

0 1

1

1

1 0 0

1

00 01 11 10

0

1

X

YZ

X Y

Y ZX Y

Figure 14: The map for example �m(1; 2; 3; 4; 5).

Example-2:

F1(X;Y;Z) = �m(3; 4; 6)

F2(X;Y;Z) = �m(0; 2; 4; 5; 6)


1

1 1

00 01 11 10

0

1

X

YZ

Y ZX Y Z

1

1

1

1 1

00 01 11 10

0

1

X

YZ

ZX Y

F = X Y Z + Y Z1 F = X Y + Z2

Figure 15: The map of F1 and F2.

3.7 Don't Care Conditions

In some applications, a Boolean function is not speci�ed for certain minterms which are referred

to as don't care items.

Example: Four bit binary code for the decimal digits has six minterms which are not used

(unspeci�ed). In general, a Boolean function with don't care items can be represented by:

F = �m(: : :) and D = �m(: : :)

where D is a collection of all don't care minterms of F .

Example:

F (W;X; Y; Z) = �m(1; 3; 7; 11; 15) and D(W;X; Y; Z) = �m(0; 2; 5)

The procedure of map manipulation for functions with don't care conditions can be modi�ed

as follows:

� In step 1, mark 'X' for those don't care minterms.

� In step 2 and 3, we can assign each 'X' as '1' or '0' to make larger adjacent squares.

Example:

00 01WX

YZ11 10

00

01

11

10

Z

Y

W

X0

1x

0

0

0

0

1

1

0

0

1x

x

0

1 W X

Y Z

F (W,X,Y,Z) = Σ m (1,3,7,11,15)

D (W,X,Y,Z) = Σ m (0,2,5)

F = W X + Y Z

Figure 16: The map with don't care.


4 NAND, NOR, XOR, and XNOR Gates

X

YF

FX

Y

NAND

NOR

XOR

XNOR(Exclusive-NOR)

FX

Y

FX

Y

Y

F = X Y + X Y

= X

Y

F = X Y + X Y

= X

F = X + Y

F = X . Y

(Exclusive-OR)

X0011

Y0101

F1110

X0011

Y0101

F1000

X0011

Y0101

F0110

X0011

Y0101

F1001

Figure 17: Logic gate symbols and truth tables.

4.1 Universal Gate (Circuit)

A gate or circuit is universal if all OR, NOT, and AND operations can be implemented by

this kind of gate (circuit) only.

Example-1: NAND is a universal gate.

Y

X

X

Y

X

X Y = X + Y

X Y = X Y

XNOT

AND

OR

Figure 18: Universal NAND.

Example-2: NOR is a universal gate.

X

X

Y

X

Y

XNOT

OR

AND

X + Y = X + Y

X + Y = X Y

Figure 19: Universal NOR.


4.2 NAND-NAND and NOR-NOR Implementation

� Conversions between NAND-NAND and AND-OR networks.

AB + CD = AB + CD

= AB CD

Any AND-OR network can be converted into a NAND-NAND network by:

1. replacing each AND (OR) gate by a NAND gate.

2. if there is a single input to the OR gate, then replace it by its complement.

Example:

D

CFE

A

B

D

CE

A

BF

Figure 20: NAND-NAND implementation.

� Conversion between NOR-NOR and OR-AND networks.

(A+B)(C +D) = A+B C +D

= A+B + C +D

Similarly, we have that anyOR-AND network can be replaced by aNOR-NOR network

and vice versa.

D

CF

E

A

B

D

C

E

A

B

F

Figure 21: NOR-NOR implementation.

4.3 XOR and XNOR Gates

Exclusive-OR function is represented by the following logic equation: X � Y = XY +XY

Exclusive-NOR function is denoted by the following logic equation: X � Y = XY +XY

Note: its is easy to prove that XY +XY = XY +XY .


4.4 Single Error Detection Using Parity Bit

Even (odd) parity bit: A parity bit is an extra bit for a binary message to make the total

number of 1's even (odd).

Parity bit generator: The circuit that generates the parity bit is called parity bit generator.

Parity bit checker: The circuit that checks the parity bit and the message in the receiver.

If the number of 1's including message bits and parity bit is even (odd), then there is no

error. Otherwise, it �nds an error.

Example: 3 bit message (X,Y,Z), even parity bit.

P = X � Y � Z

C = X � Y � Z � P

P

X

Y

Z

C

X

Y

Z

P

Figure 22: Multiple input XOR functions.

5 Integrated Circuits

5.1 Digital Logic Families

� TTL: transistor-transistor logic

� ECL: emitter-coupled logic

� MOS: metal-oxide semiconductor

� CMOS: complementary metal-oxide semiconductor

5.2 Levels of Integration

� SSI: small scale integration (number of gates < 10)

� MSI: medium scale integration (10 � 100)

� LSI: large scale integration (100 � 5000)

� VLSI: very large scale integration (> 5000)

� WSI: wafer scale integration (> 30000 ?)


6 Combinational Circuits

6.1 De�nition

A combinational circuit consists of logic gates whose output at any time is fully determined by

the values of the inputs.

CombinationalCircuit

n inputs m outputs

Figure 23: A combinational circuit.

Design Procedure

1. From the speci�cation of the circuit, determine the number of inputs and the number of

outputs. Assign a letter symbol to each input and output.

2. Derive the truth table. The size of the table depends on the number of inputs and outputs.

The values of the outputs are determined by the speci�cation of the circuit.

3. Obtain the simpli�ed SOP form for each output using map approach.

4. Draw the logic diagram for all outputs.

Example-1: Design a combinational circuit with three inputs and one output. The output

will be in logic '1' when the binary values of the inputs are less than three. Otherwise, it will

be in logic '0'. Use NAND gates only.

1. Let X;Y;Z be the inputs and F be the output.

2. The truth table is as follows:

Table 3: Truth table.

X Y Z F

0 0 0 1

0 0 1 1

0 1 0 1

0 1 1 0

1 0 0 0

1 0 1 0

1 1 0 0

1 1 1 0


3. Map simpli�cation:

11

00 01 11 10

0

1

X

YZX Y

1

X Z

Figure 24: Map F = XY +XZ.

4. The circuit:

Z

X

Y

F

Figure 25: Logic diagram.

Example-2: Design a code converter from a BCD code to excess-3 code.

1. BCD code : ABCD

Axcess-3 code: WXYZ

2. Truth table:

Table 4: Truth table for code converter.

Decimal A B C D W X Y Z

0 0 0 0 0 0 0 1 1

1 0 0 0 1 0 1 0 0

2 0 0 1 0 0 1 0 1

3 0 0 1 1 0 1 1 0

4 0 1 0 0 0 1 1 1

5 0 1 0 1 1 0 0 0

6 0 1 1 0 1 0 0 1

7 0 1 1 1 1 0 1 0

8 1 0 0 0 1 0 1 1

9 1 0 0 1 1 1 0 0

10 1 0 1 0 x x x x...

......

......

......

......

15 1 1 1 1 x x x x


3. Map simpli�cation:

00 01AB

CD11 10

00

01

11

10

D

C

A

Bx

1

x

1

x

x

x

x

11 1

00 01AB

CD11 10

00

01

11

10

D

C

A

B

1

1 x x

1

1

W = A + B C + B D

xxxx

1

X = B C + B D + B C D

00 01AB

CD11 10

00

01

11

10

D

C

A

Bx

1

x

1

x

x

x

x

1

1

1

Y = C D + C D

00 01AB

CD11 10

00

01

11

10

D

C

A

Bx

1

x

1

x

x

x

x

1

1

1

Z = D

Figure 26: Maps for W;X; Y; Z codes.

4. The circuit:

Z

Y

W

A

XB

C

D

Figure 27: Code converter circuit.


6.2 Half Adder

1. Input: X and Y

Output: S (sum) and C (carry)

2. Truth table:Table 5: Truth table for Half Adder.

X Y C S

0 0 0 0

0 1 0 1

1 0 0 1

1 1 1 0

3. S = XY +XY = X � Y

C = XY

4. Logic diagram: X

YS

C

Figure 28: Logic diagram of Half Adder.

6.3 Full Adder

1. Input: X, Y , and Z

Output: S and C

2. Truth table:Table 6: Truth table for Full Adder.

X Y Z C S

0 0 0 0 0

0 0 1 0 1

0 1 0 0 1

0 1 1 1 0

1 0 0 0 1

1 0 1 1 0

1 1 0 1 0

1 1 1 1 1


3. Map:

11

00 01 11 10

0

1

X

YZ

1 1

1

1

00 01 11 10

0

1

X

YZ

11

= X Y Z + X Y Z + X Y Z + X Y Z= X Y Z

S = X Y + X Z + Y Z= X Y + Z (X Y + X Y)= X Y + Z (X Y)

C

Figure 29: Map for Full Adder.

S = X � Y � Z

C = XY + Z(X � Y )

4. Logic diagram:

X

Y S

CZ

Figure 30: Logic diagram of Full Adder.

6.4 Parallel Adder

C S 1S 2S 3 S 04

A 0B 0A 1B 1A 2B 2A 3B 3

C 0C 1C 2C 3

FA FA FA FA

Figure 31: 4-bit Parallel Adder.


6.5 Decoder

It generates 2n minterms with n inputs.

Example-1: (2 � 4) decoder with enable input.

A

E

A

1

0

D 0

D 1

D 2

D 3

A

0A

1

E

(2 x

4) D

ecod

er D 0

D 1

D 2

D 3

Figure 32: A (2� 4) decoder.

D0 = EA1A0, D1 = EA1A0, D2 = EA1A0, D3 = EA1A0

Example-2: Construct a (3� 8) decoder from two (2 � 4) decoders.

A

A 1

0

D 0

D 1

D 2

D 3

(2x4) Decoder

Enable

2

2

0

1

0

1

2

3

D 4

D 5

D 6

D 7

(2x4) Decoder

Enable

2

2

0

1

0

1

2

3

A 2

Figure 33: A (3� 8) decoder.

Example-3: AnyBoolean function can be implemented by a decoder and OR gate: F (X;Y;Z) =

�m(0; 1; 5; 6; 7).

X

Y

F

01234567

Z

(3x8

) D

ecod

er

Figure 34: Decoder-OR implementation of a Boolean function.


6.6 Encoder

It does inverse operation of a decoder.

Example: 8 to 3 encoder.

Table 7: Truth table for octal to binary encoder.

D7 D6 D5 D4 D3 D2 D1 D0 A2 A1 A0

0 0 0 0 0 0 0 1 0 0 0

0 0 0 0 0 0 1 0 0 0 1

0 0 0 0 0 1 0 0 0 1 0

0 0 0 0 1 0 0 0 0 1 1

0 0 0 1 0 0 0 0 1 0 0

0 0 1 0 0 0 0 0 1 0 1

0 1 0 0 0 0 0 0 1 1 0

1 0 0 0 0 0 0 0 1 1 1

A0 = D1 +D3 +D5 +D7

A1 = D2 +D3 +D6 +D7

A2 = D4 +D5 +D6 +D7

A

A

01234567

A

(8 to

3)

Enc

oder

0

1

2

D0D1D2D3D4D5D6D7

Figure 35: Octal to binary encoder.

6.7 Multiplexer (MUX)

It selects a binary information from one of many input lines and directs it to a single output line.

Example-1: 4 to 1 MUX.

Y = S1S0D0 + S1S0D1 + S1S0D2 + S1S2D3


Table 8: Function table for 4 to 1 MUX.

S1 S0 Y

0 0 D0

0 1 D1

1 0 D2

1 1 D3

S

S 1

0

D 0

D 1

D 2

D 3

S 0

S 1

(4 to 1) MUX

D 0 D 1 D 2 D 3

Y

Y

Figure 36: Logic diagram of (4 to 1) MUX.

Note: Let n be the number of input lines and k be the number of selection lines, then we

have n = 2k.

Example-2: Construct a (4 to 1) MUX by using (2 to 1) MUXs.

S(2 to 1) MUX

D0 D1

Y

1

S(2 to 1) MUX 0 S(2 to 1) MUX 0

D2 D3

0 01Y(4 to 1) MUX:

(2 to 1) MUX:

S(2 to 1) MUX

Y

D0 D1

Y = S D + S D0 1

3= S D +S 0 11 S DS 0 21 S DS 0 31 S DS+ +

1S= ( 0 0S D + 0 1S D ) 1S+ ( )0 2S D + 0 3S D

Figure 37: Diagram to construct a (4 to 1) MUX from (2 to 1) MUXs.


Example-3: (2 to 1) MUX is a universal circuit.

Proof:

a(2 to 1) MUX

Y = a

1 0

(i) Inverter:

a(2 to 1) MUX

Y = a b

0 b

(ii) AND gate:

b(2 to 1) MUX

Y = a b + b = a + b

a 1

(iii) OR gate:

Figure 38: (2 to 1) MUX as universal circuit.

6.8 Demultiplexer (DEMUX)

It does inverse operation of a multiplexer.

Example: (1 to 4) DEMUX.

S

S 1

0

D 0

D 1

D 2

D 3

E

D 0 = S S E1 0

D 1 = S S E1 0

D 2 = S S E1 0

D 3 = S S E1 0

Figure 39: Diagram of (1 to 4) DEMUX.

C.N.Zhang,CS400

26

6.9

ReadOnly

Memory(ROM)

Itisessen

tially

amem

ory

device

where

perm

anentbinary

inform

atio

nissto

red.

�ROM

canbebuilt

byadeco

der

andaset

ofORgates.

Example:

Constru

ctaROM

which

isa16-word

mem

ory

from

address

0to

15.Each

word

has4bits

asshownin

Table9.Thetablecanbeview

edasthetru

thtableforfour

functio

nswhich

havethesameinputvaria

bles

(X1 ;X

2 ;X3 ;X

4 ).

Table9:Truth

tablefortheROM.

Address

Z1

Z2

Z3

Z4

0000

00

00

0001

00

01

0010

00

11

0011

00

10

0100

01

10

0101

01

11

0110

01

01

0111

01

00

1000

11

00

1001

11

01

1010

11

11

1011

11

10

1100

10

10

1101

10

11

1110

10

01

1111

10

00

XX

Z

01234567

X

(4x16) Decoder

Z

89101112131415

X

1234

ZZ

43

21

Figure

40:Logicdiagram

ofaROM.


The four functions can be represented by:

Z1 = �(8; 9; 10; 11; 12; 13; 14; 15)

Z2 = �(4; 5; 6; 7; 8; 9; 10; 11)

Z3 = �(2; 3; 4; 5; 10; 11; 12; 13)

Z4 = �(1; 2; 5; 6; 7; 9; 10; 13; 14)

� Types of ROMs:

1. Mask Programming: is is done by semiconductor company (�xed).

2. Programmable ROM (PROM): it allows users to program the PROM in their

own labs.

3. Erasable PROM (EPROM): it can be reprogrammed to a new ROM by user.

6.10 Programmable Logic Array (PLA)

It is similar to ROM in concept, except that the PLA does not provide all minterms (full de-

coder). The decoder is replaced by an array of AND gates.

Example:

F1 = X1X2 +X1X3 +X1X2X3

F2 = X1X2 +X1X3 +X1X2X3

X

X2

1

P 4P 1 P 2 P 3

F

X3

1

F 2

I 1I 2

I 3I 4

I 5I 6

Figure 41: Logic diagram of a PLA.


7 Sequential Circuits

� A sequential circuit consists of a combinational circuit and storage elements ( ip- ops)

that together form a feedback system.

OutputsInputsNext state

Combinationalcircuit Storage

elementsPresentstate

Figure 42: Block diagram of a sequential circuit.

� The values of the outputs are determined by the inputs as well as the present states of

the stotage elements.

7.1 Flip-Flop (Storage Element)

� SR ip- op:

S

Q

Q

R

(Set)

(Reset)

10001

00101

11000

00110

S R Q Q

Set state

Reset state

Undefined

Figure 43: Logic diagram and truth table of a SR ip- op.

� Clocked SR ip- op: Characteristic equation: Q(t+ 1) = S +RQ and SR = 0

S

Q

Q

R

0011

0101

S R Q(t+1)

Q(t)C0

1?

Operation

No changeResetSetIndeterminate

Q

QR

S

(a) Logic diagram (b) Characteristic table (c) Symbol (d) Excitation table

0011

0101

S RQ(t+1)

010x

Q(t)

x010

Figure 44: Clocked SR ip- op.


� JK ip- op: Characteristic equation: Q(t+ 1) = JQ+KQ

0011

0101

S R Q(t+1)

Q(t)C0

1

Operation

No changeResetSetComplement

Q

QK

J

(a) Characteristic table (b) Symbol (c) Excitation table

0011

0101

J KQ(t+1)

01xx

Q(t)

xx10Q(t)

Figure 45: JK ip- op.

� D ip- op: Characteristic equation: Q(t+ 1) = D

01

D Q(t+1)C0

1

Operation

ResetSet

Q

Q

D

(a) Characteristic table (b) Symbol (c) Excitation table

0011

0101

DQ(t+1)

0101

Q(t)

Figure 46: D ip- op.

7.2 Sequential Circuit Design using Flip-Flops

� State: A state of sequential circuits is a possible combination values of ip- ops (a

string of 0 and 1) which can be represented by a binary value or a label.

� State Diagram: A state diagram is a directed graph to represent a sequential cir-

cuit. Each node in the graph represents a state and each directed edge denotes a state

transformation.

For example, AX=Y

! B represents the transformation from state A to state B, the input

X, and the current output value Y . In general, the state diagram of a sequential circuit

with m ip- ops and n inputs has 2m nodes (states), each of which has 2n outgoing edges.

The following example illustrates how to obtain the state diagram of a sequential circuit.

Example: Draw the state diagram of the following circuit.

1. There are up to four states (nodes): 00, 01, 11, and 10. Each node has two outgoing

edges. Each edge has one input X and one output Y .

2. According to the circuit, write down the input equations for all inputs of the ip- op

A and B.

DA = AX +BX

DB = AX


XDA

C

DB

C

A

A

B

B

Y

Clock

Figure 47: Logic diagram for design example.

3. Write down characteristic equation for each ip- op and substitute all inputs by the

input functions obtained in step 2.

A(t+ 1) = DA

= A(t)X +B(t)X

B(t+ 1) = DB

= A(t)X

4. Write down output equation.

Y = (A+B)X

5. Draw state diagram starting from state 00 by trying all possible input value X

and determining which state is the next state for this input value according to the

equations obtained in step 3, and determine the output value.

00

1110

010/1

1/01/0

0/1 1/0

1/00/0

0/1

Figure 48: State diagram for design example.


� State table: is a table representing a sequential circuit. It includes columns of present

state, input(s), next state, and output(s). For example, state table for the above circuit

is as follows:

Present state Input Next state OutputA B X YA B00001111

00110011

01010101

00010101

01010000

00101010

Figure 49: State table for design example.

Note: Any state diagram can be converted into a state table and vice versa.

� Design Procedure:

1. Obtain state table from state diagram or from design requirements of the circuit.

2. Derive circuit excitation table and output function(s) from state table.

3. Use map to simplify the output functions and ip- op input functions

4. Draw the circuit.

Example-A: Design a sequential circuit whose state diagram is shown below.

00

11

10

01

0/0

1/0

1/1

0/0

0/0

0/0

1/0

1/1

Figure 50: State diagram.


1. Obtain state table from state diagram.

Present state Input Next state Output

A B X YA B

00001111

00110011

01010101

00101110

01010110

01000100

Figure 51: State table for design example-A.

2. Draw excitation table using JK ip- op.

Present state Input Next state Flip-flop Inputs

A B X JA B

00001111

00110011

01010101

00101110

01010110

0010xxxx

K J KA BA

xxxx0001

01xx01xx

xx10xx01

B

Figure 52: Excitation table for design example-A.

3. Simplify all functions using map.

1

00 01 11 10

0

1

A

BX

J = B X

x x x x A

X

B

A

1

00 01 11 10

0

1

A

BX

K = B X

x x x x

A

X

B

A

1

00 01 11 10

0

1

A

BX

J = X

xx

x x A

X

B

B

1

00 01 11 10

0

1

A

BX

K = A X + A X

x x

x x A

X

B

B

1

1

= A X

1

00 01 11 10

0

1

A

BX

Y = B X

1

A

X

B

Figure 53: Map for design example-A.


4. Draw circuit.

X J

C

J

C

A

A

B

B

Y

Clock

K

K

X

Figure 54: Logic diagram for design example-A.

Example-B: Find the state diagram for the following sequential circuit. The circuit has one

input and one output. The output will be in logic '1' if and only if a pattern '101' occurs in

the input sequence, e.g.

if input(X): '001010100101', then output(Y): '000010100001'

Since the pattern has three bits, let (00, 01, 10, 11) be the four states, where each of which

represents the �rst two bits of any input received.

Start from one state (node), the next two states and the value of the outputs are determined

by checking the value of the next inputs, i.e. for both X = 0 and X = 1. Repeat this step until

all states have been examined.

00

1110

010/0

0/0

1/00/0

0/0

1/0

1/01/1

Figure 55: State diagram for example-B.


7.3 Register

It consists of a set of D ip- ops and MUXs.

� The number of D ip- ops = the number of bits of the register.

� The size of the MUX is determined by the functions performed by the register.

Example: Design a 4-bit register which can perform the following functions under the two

control signals S0 and S1.

0011

0101

S S Register Operation

No changeShift right (down)Shift left (up)Parallel load

Mode Control

1 0

Figure 56: Function table for the 4-bit register.

� The number of D ip- ops = 4 (4-bit)

� The size of MUX is (4 to 1) (4 functions)

� Di = S1S0Ai + S1S0Ai�1 + S1S0Ai+1 + S1S0Ii

D

C

A

A

Clock

A

A

0

1

2

3

QS

0123

(4x1)MUX

S 1

0

D

C

Q

D

C

Q

D

C

Q

S

0123

(4x1)MUX

S 1

0

S

0123

(4x1)MUX

S 1

0

S

0123

(4x1)MUX

S 1

0

I 0

I 1

I 2

I 3

Serial input

Serial input

SS 1

0

Figure 57: Logic diagram of the 4-bit register.


7.4 Synchronous Binary Counter

Design procedure is the same as with any other synchronous sequential circuit.

Example: Design a 4-bit binary up counter using JK ip- ops.

1. State diagram.

0000 0001 1111

Figure 58: State diagram for binary up counter.

Note: it can be viewed as the state diagram of a sequential circuit without input and

output.

2. Excitation table.

Present state Next state Flip-flop Inputs

A A J0000000011111111

0000111100001111

0011001100110011

00000001xxxxxxxx

KA3 A3xxxxxxxx00000001

3 2 A1 A00101010101010101

A A3 2 A1 A00000000111111110

0001111000011110

0110011001100110

1010101010101010

J KA2 A2 J KA1 A1 J KA0 A00001xxxx0001xxxx

xxxx0001xxxx0001

01xx01xx01xx01xx

xx01xx01xx01xx01

1x1x1x1x1x1x1x1x

x1x1x1x1x1x1x1x1

Figure 59: Excitation table for binary up counter.

3. Map simpli�cation.

JA0= KA0

= 1

JA1= KA1

= A0

JA2= KA2

= A0A1

JA3= KA3

= A0A1A2


x x x x

xxxx

x x x x

xxxx

1

1

1

1

x x

x x

xx

xx

x x

x x

xx

xx

1

1

1

1

x x x x

xxxx

x x x x

xxxx

1

1

1

1

J = AA2 0 A 1 J = AA1 0 A 2J = AA3 0 A 1

K = AA2 0 A 1 K = AA1 0

1

1

A 2K = AA3 0 A 1

00 01 11 10

00

01

11

10

A 1 A 0

A 2A 3

A 2

A 1

A 3

A 0

Figure 60: Map for binary up counter.

4. The circuit.

E

J

C

J

C

A

A

Clock

K

K

J

CA

K

J

CA

K

0

1

2

3

OutputCarry

Count Enable

Figure 61: Circuit of binary up counter.


7.5 Other Synchronous Counters

Example: Design a counter using JK ip- ops which repeats the sequence of six states as

shown below:

000 001 110010 100 101

Figure 62: Sequence of six states for synchronous counter.

1. State diagram.

000

001

010

110

101

100

111

011

Figure 63: State diagram for synchronous counter.

2. Excitation table.

Present state Next state Flip-flop Inputs

A B J00001111

00110011

0011xxxx

KA Axxxx0011

C01010101

A00111100

01000100

10001000

J KB B J KC C01xx01xx

xx11xx11

1x0x1x0x

x1x1x111

B C

Figure 64: Excitation table for synchronous counter.


3. Map simpli�cation.

1

00 01 11 10

0

1

A

BC

J = B

x x x x A

C

B

A

1

1

00 01 11 10

0

1

A

BC

K = B

x x x x

A

C

B

A

1

1

00 01 11 10

0

1

A

BC

J = C

x x

x x A

C

B

B

1

1

00 01 11 10

0

1

A

BC

K = 1

x

xx A

C

B

B

1

1x

1

00 01 11 10

0

1

A

BC

J = B

xx

xx A

C

B

C

1

1

00 01 11 10

0

1

A

BC

K = 1

x

x

x

x A

C

B

C

1

111

Figure 65: Map for binary up counter.

4. The circuit.

Clock

J C K J C K J C K

A B C

Logic-1

Figure 66: Synchronous counter circuit.

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