CIS 4930 VLSI Tes.ng and Fault- Tolerant Design Design For...

CIS4930VLSITes.ngandFault-TolerantDesign

DesignForTestability

Dr.HaoZhengCompSci&Eng

UnivofSouthFlorida

Introduc.on•  Tes?ngcannotbeanaAerthought!•  Tes?ngshouldbeconsideringduringthedesignprocess– enhances“testability”&designquality–  reducestestcost

•  Testcomplexitydeterminedbythreefactors– Controllability– Observability– Predictability–abilitytoobtainknowoutputs

•  DesignforTestability(DFT)techniquesaredesigneffortstoensurethatadeviceistestable

2

Testability-Controllability

•  Controllability–  abilitytoestablishaspecificsignalvalueateachnodeinthecircuitbyseOngvaluesonPIs

•  Circuitsdifficulttocontrol:– Decoders– Circuitswithfeedback– Oscillators– Clockgenerators– Counters(eg.,16bitcounter,howclockcycleswillittaketoforceMSBto1?)

3

Testability-Observability

•  Observability– Abilitytodeterminethesignalvalueatanynodeinacircuitbycontrollingcircuit’sinputsandobservingitsoutputs

•  Circuitsdifficulttoobserve:– Sequen?alcircuits– Circuitswithglobalfeedback– EmbeddedRAMs,ROMs,orPLAs– Circuitswithredundantnodes

4

SomeGeneralObserva.ons

•  Sequen?allogicismoredifficulttotestthancombina?onallogic

•  Controllogicismoredifficulttotestthandata-pathlogic

•  Randomlogicismoredifficulttotestthanstructured,bus-orienteddesigns

•  Asynchronousdesignsismoredifficulttotestthansynchronousdesigns

5

Tradeoffs

•  DFTtechniquesoAenreducecoststotest.–  Improvedcontrollabilityandobservability.– Reducedtest?me,testgenera?oncost,–  improvedtestquality->productquality

•  Atmean?me,theyincreaseproductcost.– Siliconarea,I/Opins,powerconsump?on,andcircuitdelay.

6

AdHocDFTTechniques

1.  TestPoints2.  Ini?aliza?on3.  Monostablemul?vibrators(one-shots)4.  Oscillatorsandclocks5.  Counters/ShiARegisters6.  Par??oningLargeCircuits7.  LogicalRedundancy8.  BreakingGlobalFeedbackPaths

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1–TestPointsRule:Employtestpointstoenhancecontrollabilityandobservability

Twotypesoftestpoints:•  Controlpoints(CP)=PIsusedtoenhancecontrollability

•  Observa?onpoints(OP)=POsusedtoenhanceobservability

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EmployingTestPoints

9

AisanOPA’isaCP

0Injec?onCkt

Demandoflarge#ofIOpins!

Mul.plexingMonitorpoints•  ForlimitedIOpins,wecanusemul?plexer•  Drawback–canmonitoronlyoneOPata?me->increasestest?me

•  Selectlinescanbedrivenbyacounter

10

Tradeoffbetweentest?meandIOpins.Nclockcyclesarerequiredbetweentestvectors

Demux/LatchforMul.pleCPs•  Valuesof2ncontrolpointsareseriallyappliedtoinputZ•  StoredinNbit-widelatch•  NeedNcyclestosetupthecontrolvalues

11

350

R

1

2DE

Z MU

NX

1 2 ... n

Xl X2 Xn

DESIGN FOR TESTABILITY

CPl

CP2

CPN

Figure 9.3 Using a demultiplexer and latch register to implement controlpoints

observation ntest

points

normalfunctional

signals

n

MUX

s

SELECT

(a)

n primaryoutputs

normal nprimaryinputs

DEMUX

S

SELECT

(b)

n

normalfunctional

inputs

R

n controltest

points

Figure 9.4 Time-sharing I/O ports

3. enable and read/write inputs to memory devices;

4. clock and preset/clear inputs to memory devices such as flip-flops, counters, andshift registers;

5. data select inputs to multiplexers and demultiplexers;

6. control lines on tristate devices.

Examples of good candidates for observation points are as follows:

Time-sharingNormalI/OPins

12

ControlPointSelec.on–GoodCandidates

•  Control,address,anddatabuslinesonbus-structureddesigns

•  Enable/holdinputstomicroprocessors•  Enableandread/writeinputstomemorydevices•  Clockandpreset/clearinputstomemorydevices•  Dataselectinputstomuxes/demuxes•  Controllinesontri-statedevices

13

Observa.onPointSelec.on-GoodCandidates•  Stemlinesassociatedwithsignalshavinghighfanout

•  Globalfeedbackpaths•  Redundantsignallines•  Outputsoflogicdeviceshavingmanyinputs(muxes,paritygenerators)

•  Outputsfromstatedevices(FFs,Counters,ShiARegisters)

•  Address,control,anddatabusses

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2–Ini.aliza.on

15

Rule:Designcircuitstobeeasilyini=alizable

Shouldbeavoided!

3– MonostableMul.vibrators

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Rule:Disableinternalone-shotsduringtest• One-shotsprovidepulsesinternaltocircuit• DifficultforATEtoremaininsynchroniza?onwiththecircuit354

1

JlII

one-shot

(a)

1/0-1


jumperI

2 V

A

B

C

D

IIIIIIL _

(b)

n E (OP)

Figure 9.8 (a) Disabling a one-shot using jumpers (b) Logical control anddisabling of a one-shot

9.2.5 Partitioning Counters and Shift Registers

Rule: Partition large counters and shift registers into smaller units.

Counters, and to a lesser extent shift registers, are difficult to test because their testsequences usually require many clock cycles. To increase their testability, suchdevices should be partitioned so that their serial input and clock are easily controllable,and output data are observable. Figure 9.10(a) shows a design that does not includetestability features and where the register R has been decomposed into two parts, andFigure 9.10(b) shows a more testable version of this design. For example, Rl and R2may be 16-bit registers. Here the gated clock from C can be inhibited and replaced byan external clock. The serial inputs to Rl and R2 are easily controlled and the serialoutput of R2 is easily observable. As a result, Rl and R2 can be independently tested.

354

1

JlII

one-shot

(a)

1/0-1


jumperI

2 V

A

B

C

D

IIIIIIL _

(b)

n E (OP)

Figure 9.8 (a) Disabling a one-shot using jumpers (b) Logical control anddisabling of a one-shot

9.2.5 Partitioning Counters and Shift Registers

Rule: Partition large counters and shift registers into smaller units.

Counters, and to a lesser extent shift registers, are difficult to test because their testsequences usually require many clock cycles. To increase their testability, suchdevices should be partitioned so that their serial input and clock are easily controllable,and output data are observable. Figure 9.10(a) shows a design that does not includetestability features and where the register R has been decomposed into two parts, andFigure 9.10(b) shows a more testable version of this design. For example, Rl and R2may be 16-bit registers. Here the gated clock from C can be inhibited and replaced byan external clock. The serial inputs to Rl and R2 are easily controlled and the serialoutput of R2 is easily observable. As a result, Rl and R2 can be independently tested.

3– MonostableMul.vibrators

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Rule:Disableinternalone-shotsduringtest• One-shotsprovidepulsesinternaltocircuit• DifficultforATEtoremaininsynchroniza?onwiththecircuit

4–OscillatorsandClocks

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Rule:Disableinternaloscillators/clocksduringtest

5–Par..oningCountersandShiWRegisters•  Rule:Par==onlargecountersandshiCregistersintosmallerunits

•  Counters/SRaredifficulttotestbecausetestsequencesusuallyrequiremanyclockcycles

•  Par??ontheregisterforbeqercontrol/obs.

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6.Par..oningofLargeComb.Circuits

•  Rule:Par==onlargecircuitsintosmallsubcircuitstoreducetestgenera=oncosts.

•  Timecomplexityoftestgenera?ongrowsfasterthanalinearfunc?onofcircuitsize

•  Par??oningcanreducethetestgenera?oncost

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Ad Hoc Design for Testability Techniques

B

sA C

m n\11 \1 \11 \1

D,:::..

p

C 1 C 2

..:::,Eq

t t

357

B

F(a)

G

A

D

A'

C

F

o 1MUX S

C 2 T 1 T 2 ModeS 1 C' 0 0 normalM 0 1 test C 1UX 0 E 1 0 test C 2

G

1 0S MUX

F'(b)

G'

Figure 9.11 Partitioning to reduce test generation cost

Ad Hoc Design for Testability Techniques

B

sA C

m n\11 \1 \11 \1

D,:::..

p

C 1 C 2

..:::,Eq

t t

357

B

F(a)

G

A

D

A'

C

F

o 1MUX S

C 2 T 1 T 2 ModeS 1 C' 0 0 normalM 0 1 test C 1UX 0 E 1 0 test C 2

G

1 0S MUX

F'(b)

G'

Figure 9.11 Partitioning to reduce test generation cost

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7–LogicalRedundancy•  Rule:Avoidtheuseofredundantlogic.•  Redundancymakesfaultsundetectable•  Itmayinvalidatesometestfornonredundantfaults•  Cancausedifficultyinfaultcoveragecalcula?ons•  Redundancycanbeintroducedinadvertantly– Maybedifficulttoremove.–  Testpointscanbeaddedtoremoveredundancyduringtes?ng

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Fault Detection and Redundancy

ab

C --+-----.----1

Figure 4.8

103

Note that in practice, when we deal with large combinational circuits, even irredundantcircuits may not be tested with complete detection test sets. The reason is thatgenerating tests for some faults may consume too much time, and all practical testgeneration programs are set up to 3tOP the test generation process for a fault when itbecomes too costly. In a practical sense, there is no difference between anundetectable fault f and a detectable one g that is not detected by an applied test set.Clearly, g could be present in the circuit and hence invalidate the single-faultassumption.

Identifying redundancy is closely related to the problem of test generation. To showthat a line is redundant means to prove that no test exists for the corresponding fault.The test generation problem belongs to a class of computationally difficult problems,referred to as NP-complete [Ibarra and Sahni 1975]. The traveling salesman problemis one famous member of this class [Horowitz and Sahni 1978]. Let n be the "size" ofthe problem. For the traveling salesman problem n is the number of cities to bevisited; for test generation n is the number of gates in a circuit. An important questionis whether there exists an algorithm that can solve any instance of a problem of size nusing a number of operations proportional to n r, where r is a finite constant. Atpresent, no such polynomial-time algorithm is known for any NP-complete problem.These problems are related in the sense that either all of them or none of them can besolved by polynomial-time algorithms.

Although test generation (and identification of redundancy) is a computationallydifficult problem, practical test generation algorithms usually run in polynomial time.The fact that the test generation problem is NP-complete means that polynomial timecannot be achieved in all instances, that is, any test generation algorithm mayencounter a circuit with a fault that cannot be solved in polynomial time. Experiencehas shown that redundant faults are usually the ones that cause test generationalgorithms to exhibit their worst-case behavior.

4.2.2 Sequential CircuitsTesting sequential circuits is considerably more difficult than testing combinationalcircuits. To detect a fault a test sequence is usually required, rather than a single inputvector, and the response of a sequential circuit is a function of its initial state.

ScanRegisters

•  TestpointsarecostlyintermsofI/Opins•  ScanRegisterisanalterna?ve–tradeoffbetweentest?me,area,andI/Opins

•  ScanRegister(SR)=RegisterwithbothshiAandparallel-loadcapability

•  StoragecellsinSRcanbeusedasobserva?onandcontrolpoints

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ScanStorageCell(SSC)

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Controllability and Observability by Means of Scan Registers 359

sseD Q, SO

s, D

sseNIT

CK

(a) (b)

D 1 Ql D 2 Q2 Dn Qn

Sin SOU!

NIT

CK

(c)

(d)

Figure 9.12 (a) A scan storage cell (SSC) (b) Symbol for a sse (c) A scanregister (SR) or shift register chain (d) Symbol for a scan register

Simultaneous Controllability and Observability

Figure 9.13(a) shows two complex circuits C 1 and C 2 • They can be eithercombinational or sequential. Only one signal (Z) between C 1 and C 2 is shown.

Figure 9.13(b) depicts how line Z can be made both observable and controllable usinga scan storage cell. Data at Z can be loaded into the sse and observed by means of ascan-out operation. Data can be loaded into the sse via a scan-in operation and theninjected onto line Z'. Simultaneous controllability and observability can be achieved.That is, the scan register can be preloaded with data to be injected into the circuit.

N/T = 0

N/T = 1

Normalmode:Disloaded

Tes?ngmode:Sisloaded

ScanRegister

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sseD Q, SO

s, D

sseNIT

CK

(a) (b)

D 1 Ql D 2 Q2 Dn Qn

Sin SOU!

NIT

CK

(c)

(d)






sseD Q, SO

s, D

sseNIT

CK

(a) (b)

D 1 Ql D 2 Q2 Dn Qn

Sin SOU!

NIT

CK

(c)

(d)





Normal mode (N/T = 0) load data (Dx

) in parallel

Test mode (N/T = 1) shift data (from Sin

to Sout

)

SimultaneousControllabilityandObservability

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•  C1andC2canbesequen?al/combina?onal•  ZcanbeloadedintoSSCviascan-inandobservedbyscan-outopera?on

•  DatacanbeloadedinSSCviaD-inputandinjectedontolineZ’

SeparateControllabilityandObservability

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Z’isconnectedtoD-input.CPisconnectedtoScan-in.

ObservabilityOnly

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ControllabilityOnly

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MakingUndetectableFaultsDetectable

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•  X’=Controlpoints Z’=Observa?onpoints•  Letssayfisanundetectablefault•  ChooseX’andZ’suchthatfbecomesdetectable•  R1andR2canbecombinedasasingleregister

Example1–EnhancingTestability

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• C1,C2,…C6areComplexSeq/Combblocks.• #ofCPsandOPsdecidesthelengthofscanregister.• Howdoesitwork?

GenericScan-BasedDesigns

•  ScanDesign–mostpopularstructuredDFTtechnique,employsascanregister

•  Severalformsofscandesigns–differprimarilyinthescancelldesign

•  Threegenericformsofscandesign– FullSerialIntegratedScan–  IsolatedSerialScan– Non-serialScan

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FullSerialIntegratedScan

35

Insteadoftes?ngcircuitin(a)asasequen?alcircuit,nowCcanbetestedusingaseriesoftestvectors.

Allstorageelementsinthedesignbecomepartofscanregister.

IsolatedSerialScan

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•  UnlikeFullSerial,Scanregisterisnotpartofthedatapath

Shadowregister:doesnotinterferethenormalopera?on,butaddsubstan?alareaoverhead.

Rs

Non-SerialScan

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RAMisusedinsteadofshiAregister.IndividualbitscanbemodifiedforselectedCPsorOPs.Areaoverheadishigh.

GenericBoundaryScan•  Concept–indesigningmodulessuchascomplexchipsorPCBs,forlocaltes?ngandfaultisola?on,weshouldbeabletoisolateonemodulefromanother

•  Allchipsonboardaredesignedusingboundaryscanarchitecture

•  Boundaryscanregistersareontheperiphery;notpartofthefunc?on

•  Testvectorscanbescannedinandresponsessavedandscannedout

•  Internalclockmustbedisabled 38

GenericBoundaryScan

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Boundary-ScanStandards•  Goal–toensurechipsofVLSIcomplexitycontainstandardDFTcircuitrytomaketestdevelopmenteffec?veandlesscostly

•  Someini?a?ves–  JointTestAc?onGroup(JTAG)BoundaryScanStd–  VHSICElementTestandMaintenance(IBMStd)–  IEEE1149.1TestabilityBusStandard

•  Primarilydealwith–  TestBus(residesontheboard)–  BusProtocol–  InterfacelogicbetweentestbusportsandDFThardware

•  JTAGBoundaryScanandIEEE1149.1requireabound-scanregisterexistonthechip

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TAP=TestAccessPort•  TDI=TestDataInput•  TDO=TestDataOutput•  TMS=TestModeSignal•  TCK=TestClockTAPController=aFSMcontrolopera?onoftestbus

Boundary-Scan Standards 397

OPTIONAL

Sout ::::::::::::::::::::::::::::::::

APPLICATION LOGIC

Sin::::::::::::::::::::::::::::::::::

.: : : : : : : .: BIST registers :::::::::::: : : : : : : :: Scan registers ::::::::::

Boundary-scan pathIIII

Instructionregister

Miscellaneousregisters

Bypassregister

BS test bus circuitry

...............................................................................

Boundary-scan cell/

I/O Pad //

/

/

.

Figure 9.45 Chip architecture for IEEE 1149.1

9.10.2 Boundary-Scan Cell

Two possible boundary-scan cell designs are shown in Figure 9.46. These cells can beused as either output or input cells. Other cell designs exist for bidirectional I/O ports andtristate outputs.

As an input boundary-scan cell, IN corresponds to a chip input pad, and OUT is tied to anormal input to the application logic. As an output cell, IN corresponds to the output ofthe application logic, and OUT is tied to an output pad. The cell has several modes ofoperations.

Normal Mode: When Mode_Control=O, data passes from port IN to port OUT; then thecell is transparent to the application logic.

TestBusOpera.on

1.  Instruc?onsentseriallyovertheTDIlineintotheinstruc?onregister

2.  Selectedtestcircuitryisconfiguredtorespondtotheinstruc?on–  Moredataneededtoconfiguredataregisters

3.  Thetestinstruc?onisexecuted.TestresultscanbeshiAedoutofselectedregistersandtransmiqedoverTDOlinetothebusmaster.DatacanshiAedinwhileresultsareshiAedout.

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BoundaryScanCell

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• NormalMode:Mode_Control=0,cellistransparent• ScanMode–Boundarycellsareinterconnectedintoascanpath(TDIinput,TDOoutput)ShiCDR=1andClockpulsesappliedtoClockDR• CaptureMode–ShiCDR=0=>inputINiscaptured• UpdateMode–OnceQAisloaded(byscan/capture),setMode_control=1andapplyaclockpulsetoUpdateDRforthevalueinQAappliedtoOUT

Applica?onlogic

BoundaryScanCell–AnotherDesign

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PCBwithIEEE1149.1testbus

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• InterconnectTest• SystemSnapshot• ChipTest

400 DESIGN FOR TESTABILITY

- TDI

TDO

Figure 9.47 A printed circuit board with a IEEE 1149.1 test bus

9.10.4 The Test BusA board supporting IEEE 1149.1 contains a test bus consisting of at least four signals. (Afifth signal can be used to reset the on-chip test-bus circuitry.) These signals areconnected to a chip via its test-bus ports. Each chip is considered to be a bus slave, andthe bus is assumed to be driven by a bus master.

The minimum bus configuration consists of two broadcast signals (TMS and TCK) drivenby the master, and a serial path formed by a "daisy-chain" connection of serial scan datapins (TDI and TDO) on the master and slave devices. Figure 9.51(a) shows a ringconfiguration; Figure 9.51(b) shows a star configuration, where each chip is associatedwith its own TMS signal. Star and ring configurations can be combined into hybridconfigurations. The four bus signals associated with a slave TAP are defined as follows.

TCK - Test Clock. This is the master clock used during the boundary-scan process.

TDI - Test Data Input. Data or instructions are received via this line and are directed toan appropriate register within the application chip or test bus circuitry.

PCBTest–Threemodes•  ExternalTestMode– Testinterconnectsbetweenchips

•  SampleTestMode–  I/Odataofachipcanbesampledduringnormalsystemopera?on– snapshotsofchipIOdata

– Sampleddatacanbescannedoutwhileboardisinnormalopera?on

•  InternalTestMode–  Inputstotheapplica?onlogicisdrivenbytheinputboundary-scancellsandresponsecapturedinoutputboundary-scancells

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Boundary-Scan Standards 401

Chip 1 Chip 2

Output SOUT

Mode Input SOUT

Control Mode

ControlMUX

MUX0

Application0 Application

logiclogic

MUX

MUX0

Q D Q D 0

Q B Q A Q D Q D

Q B Q A

ShiftDRUpdateDR ClockDR SIN

UpdateDR ClockDR SIN ShiftDR

Figure 9.48 External test configuration

TDO - Test Data Output. The contents of a selected register (instruction or data) areshifted out of the chip over TDO.

TMS - Test Mode Selector. The value on TMS is used to control a finite state machinein a slave device so that this device knows when to accept test data or instructions.

Though the IEEE 1149.1 bus employs only a single clock, TCK, this clock can bedecoded on-chip to generate other clocks, such as the two-phase nonoverlap clocks usedin implementing LSSD.

9.10.5 Test-Bus Circuitry

The on-chip test-bus circuitry allows access to and control of the test features of a chip.A simplified version of this circuitry is shown in Figure 9.45, and more details are shownin Figure 9.52. This circuitry consists of four main elements, namely (1) a test accessport (TAP) consisting of the ports associated with TMS, TCK, TDI, and TDI, (2) a TAPcontroller, (3) a scannable instruction register and associated logic, and (4) a group ofscannable test data registers. We will next elaborate on some of these features.

9.10.5.1 The TAP Controller

The TAP controller is a synchronous finite-state machine whose state diagram is shownin Figure 9.53. It has a single input, labeled TMS, and its outputs are signalscorresponding to a subset of the labels associated with the various states, such asCapture-IR. The state diagram shows that there are two parallel and almost identical

ExternalTestConfigura.on

47

UpdateOpera?on Capture

Opera?on

402

Input

Mode

Control

MUX

SOUT

MUX

o


Output SOUT

Mode

Control

MUXApplication

logic 0

MUX

UpdateDR ClockDR SIN ShiftDR

UpdateDR ClockDR

o

SIN ShiftDR

Figure 9.49 Sample test configuration

subdiagrams, one corresponding to controlling the operations of the instruction register,the other to controlling the operation of a data register. The controller can change stateonly when a clock pulse on TCK occurs; the next state is determined by the logic level ofline TMS. The function of some of these control states is described below.

Test-Logic-Reset: In this state the test logic (boundary-scan) is disabled so that theapplication logic can operate in its normal mode.

Run-Test/Idle: This is a control state that exists between scan operations, and where aninternal test, such as a built-in self-test, can be executed (see instruction RUNBIST).

A test is selected by first setting the instruction register with the appropriate information.The TAP controller remains in this state as long as TMS=O.

Seleet-DR-Sean: This is a temporary controller state. If TMS is held low then a scan-datasequence for the selected test-data register is initiated, starting with a transition to thestate Capture-DR.

Capture-DR: In this state data can be loaded in parallel into the test-data registersselected by the current instruction. For example, the boundary-scan registers can beloaded while in this state. Referring to Figure 9.49, to capture the data on the input padshown and the output of the application logic, it is necessary to set ShiftDR low and toactivate the clock line CloekDR.

SampleTestConfigura.on

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InputSampled

OutputSampled

InternalTestConfigura.on

49

InputsfromI/PBScells Response

CollectedintoO/PBScells

50

404

Application chips

TDITCK

#1TMS

Bus TDOmaster

TDO TDITCK

TDI #2TMS

TMS TDO

•TCK ••TDITCK

#NTMSTDO

(a)


Application chips

:- TDITCK

#1TMS

Bus TDOmaster

TDO -.. TDI-TDITMSl TCK

#2TMS2 :.. TMS

• •• • TDO• •TMSN - 1---- •

TCK ••::- TDI

TCK#N

-.. TMS-TDO

(b)

Figure 9.51 (a) Ring configuration (b) Star configuration

The states that control the instruction register operate similarly to those controlling thetest-data registers. The instruction register is implemented using a latched parallel-outputfeature. This way a new instruction can be scanned into the scan path of the instructionregister without affecting the output of the register. The Select-IR-Scan state is again atemporary transition state. In the Capture-IR state, the shift register associated with theinstruction register is loaded in parallel. These data can be status information and/orfixed logic values. In the Shift-IR state this shift register is connected between TDI andTDO and shifts data one position. In the Update-IR control state the instruction shiftedinto the instruction register is latched onto the parallel output of the instruction register.This instruction now becomes the current instruction.

The TAP controller can be implemented using four flip-flops and about two dozen logicgates.

9.10.5.2 Registers

The Instruction Register and Commands

The instruction register has the ability to shift in a new instruction while holding thecurrent instruction fixed at its output ports. The register can be used to specify operationsto be executed and select test-data registers. Each instruction enables a single serial test-data register path between TDI and TDO. The instructions BYPASS, EXTEST, and

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IEEE1149.1TestBusCircuitry•  TAP–TCK,TMS,TDI,TDO•  TestDR•  ScannableIR•  TAPcontroller

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StateDiagramof

TAPController

Instruc.onRegisterandCommands

•  CommandscanbeshiAedintoIRfromTDI.•  Commandsspecifyopera?onsandselec?onofDR.– BYPASS–excludeachipfromscanpath.– EXTEST–testintra-chipinterconnect– SAMPLE–capturechipIOandstoredataonboundaryscanregisters.

–  INTEST–testachipitself.– RUNBIST–supportaself-tes?ng.

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CIS 4930 VLSI Tes.ng and Fault- Tolerant Design Design For...

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