CIRF Circuit IntégréRadio Fréquencehassan/cirf10_lna_lecture.pdfVin Vout M1 M2 Lout M3 R Rref...

CIRFCircuit Intégré Radio Fréquence

Low Noise Amplifier

Hassan AboushadyUniversité Paris VI

Multidisciplinarity of radio design

H. Aboushady University of Paris VI

• M. Perrott, “High Speed Communication Circuits and

Systems”, M.I.T.OpenCourseWare, http://ocw.mit.edu/,

Massachusetts Institute of Technology, 2005.

• D. Leenaerts, J. van der Tang, and C. Vaucher, “Circuit design for RF transceivers”, Kluwer academic publishers, 2001.

References

H. Aboushady University of Paris VI

Heterodyne

Homodyne(Direct conversion)

Low-IF

4

LNA : 1st block of an RF Receiver

Noise Factor :SNRin

SNRoutF =

NF = 10 log10(F)

F1

G1

F2

G2

F3

G3

Si So

5

University of Paris VI

LNA Requirements: Noise

Noise Figure :

( ) ( ) ( )

12121

3

1

21

...

1...

11)1(1

−

−++

−+

−+−+=

n

n

GGG

F

GG

F

G

FFF

Friis Equation :

LNA Requirements to reduce the RF receiver overall Noise Factor:

• Low Noise Factor, F1• High Gain, G1

x(t) y(t)

Vi Vo

α

1,3IPA

...11

2

3,3

2

1

2

1

2

2,3

2

1

2

1,3

2

3

+++≈IPIPIPIP AAAA

βαα

ωω1ω2ωω1ω2

2ω1-ω2 2 ω2 -ω1

∆P

dBmindB

dBm PP

IIP +∆

=2

3

6

β

2,3IPA

γ

3,3IPA


LNA Requirements: Linearity

LNA Requirements to improve the RF receiver overall linearity:

• High AIP3,1• Low αααα1

Vin

Rout

Vout

M1

Cgd

- Parasitic capacitance Cgd between input and output nodes. - Low Gain- Complex Load Impedance

outmv ZgA .=

)1

( 0

par

outoutCj

rRZω

=

17

Common Source Amplifier

D. Haghighitalab, M. Vasilevski & H. Aboushady University of Paris VI

Vin

Vout

M1

M2

Lout- Isolation between input and output nodes- Higher Gain

)1

( 0

0

0 out

par

cascodeout LjCj

rZ ωω

=

18


Common Source Cascode with Inductive Load

Benefits of Cascode

- Real Load Impedance can be obtained

Purpose of Inductive Load

Vin

Vout

M1

M2

Lout

M3

R

Rref

Current Mirror

- The current in M1 is fixed by Rref and the ratio (W1/L1)/(W3/L3).

- R is to increase the impedance seen by the input signal.

19


Biasing

Current Mirror

Vin

Vout

M1

M2

Lout

M3

R

Rref

Ldeg

Lg

- Lg compensates the complex impedance due to Cgs1 .

- Ldeg adjusts the real part of the input impedance to 50 Ω .

20


Matching Input Impedance

Inductive Degeneration

21

Input Impedance

Matching Zin to 50Ω

For a Real Impedance @ ω0

degdeg )(1

)( LC

gLLs

sCsZ

gs

mg

gs

in +++=

degLC

gR

gs

ms =

gsg CLL )(

1

deg

0+

=ω


Ldeg and Lg (1)

22

For different

Ldeg values

ReZ

in

Lg

⇒ReZin

independent of Lg


Ldeg and Lg (2)

23

ReZ

in

ImZ

in

Lg

Lg

⇒Ldeg for:

ReZin=50

Lg for:

ImZin=0


For different

Ldeg values

⇒ReZin

independent of Lg

Ldeg and Lg (2)

24

Techno. 0.35µm

c= -0.4j

γ = 2/3


NF of a MOS Transistor

)()()(

)(

)(

)(

)(

)(

)(

.).(

addedosourceototalo

sourcei

totalo

totaloi

sourceii

totaloo

sourceii

o

i

NNN

NG

N

NGS

NS

NS

NS

SNR

SNRF

+=

====

)(

)(

)(

)()(

)(

)(1

sourceo

addedo

sourceo

addedosourceo

sourceo

totalo

N

N

N

NN

N

NF +=

+==⇒

1) No(added) : Output Reffered Noise due to the LNA.

2) No(source): Output Reffered Noise due to the source.

25


NF Characterization

R

RkTi R 42 =

R

Résistance


Noise Sources

27

R

RkTi R 42 =

R

fgkTi

fgkTi

gsg

dd

∆=

∆=

δ

γ

4

4

2

0

2

Résistance Transistor


Noise Sources

28

R

RkTi R 42 =

R Ls

Rs

Csub

RsubRsub Rs

fgkTi

fgkTi

gsg

dd

∆=

∆=

δ

γ

4

4

2

0

2

Résistance Transistor Inductance


Noise Sources

R

RkTi R 42 =

R Ls

Rs

Csub

RsubRsub Rs

29

fgkTi

fgkTi

gsg

dd

∆=

∆=

δ

γ

4

4

2

0

2

),,,,,.( 22222

RsubRsubRsRsRRggddi HiHiHiHiHiNGfNF =

)(

)(1

sourceo

addedo

N

NF +=

)(addedoN

Resistance Transistor Inductance

)(sourceoN


Noise Sources

I

inI

)(

)()(

sI

sIsH

in

outd =

30


Noise Sources

out

out

out

Vin

Vin

Circuit

Circuit

Circuit

Iin

in

Gain :

Input Impedance:

Noise Factor:

)(

)()(

sVin

sVoutsGain =

)(

)()(

sIin

sVinsZin =

31

)(

)(1

sourceo

addedo

N

NF +=


Characterization

out

1)()2

)()(.)1

=

−=

sV

R

sVsVVsC

in

outinout

=

+−

1

0

)(

)(

01

/1/1

sV

sVsCRR

out

in

+−

1

0

01

/1/1 sCRR

+ sRC11

1

10

01

Gauss-Jordan

sRCsV

sVsGain

in

out

+==

1

1

)(

)()(

32


Characterization Example

– Substitution

– Numerical solution of

the matrix

Solve Matrix

Maxima

GiNaC (C++)

33

– Gain Matrix

– Zin Matrix

– Matrices of Noise

Transfer Functions of

each Noise Source

Create Matrices

Netlist Description

Small Signal Parameters

Zin , Gain , No(added)

Cairo+


Automatic Characterization Procedure

34

Length: Minimum L to reduce parasitic capacitances.

Width: Ids calculated for NFmin.

Layout: Maximum number of fingers to reduce Gate resistance.

Ldeg : Adjusted for Re Zin = 50 ΩΩΩΩ .

Lg : Adjusted for Im Zin = 0 Ω Ω Ω Ω .

Lout : Adjusted for the desired Zout and Gain.


Design Procedure

Transistors

Inductors

⇒ ⇒ ⇒

Circuit Design

Parameters

VIN,i

VOUT,i

Veg,i

IB,i

Li

Temp

Transistors’

Sizes

And Biasing

W1

Vgs1

Wn

.

Vds1

.

Small Signal

Parameters

gm,1

gds,1

gm,n

Cgs,1

Linear Circuit

Performance

Ad0

FT

.

φm

.

Sizing

Biasing

Small Signal

Characterization

Performance

Modeling

[Ramy ISKANDER “Knowledge-aware synthesis for analog integrated circuit

design and reuse” Ph.D. Thesis UPMC,LIP6 2008]

2

di

?2

gi

35

CAIRO+

Techno

Transistors Sizing

NF

min?

Rs f0 Vdd

Ids-min (Wmin,Lmin)

Caracterization of NF , Gain, Zin

No

Yes

Gain Topology

Choose Inductances

Calculate NF

Impedance Matching

Gain

OK?Yes

NoGain Adjustment

Ids++

36


Automatic Sizing Procedure

Techno

Transistors Sizing

NF

min?

Rs f0 Vdd

Ids-min (Wmin,Lmin)

Caractérisation de NF , Gain, Zin

No

Yes

Gain Topology

Choose Inductances

Calculate NF

Impedance Matching

Gain

OK?Yes

NoGain Adjustment

Ids++

37



Techno

Transistors Sizing

NF

min?

Rs f0 Vdd

Ids-min (Wmin,Lmin)


No

Yes

Gain Topology

Choose Inductances

Calculate NF

Impedance Matching

Gain

OK?Yes

NoGain Adjustment

Ids++

50Re

:

deg ≈in

gout

ZpourL

initialesvaleursLetL

38



Techno

Transistors Sizing

NF

min?

Rs f0 Vdd

Ids-min (Wmin,Lmin)


No

Yes

Gain Topology

Choose Inductances

Calculate NF

Impedance Matching

Gain

OK?Yes

NoGain Adjustment

Ids++

39



Techno

Transistors Sizing

NF

min?

Rs f0 Vdd

Ids-min (Wmin,Lmin)


Non

Yes

Gain Topology

Choose Inductances

Calculate NF

Impedance Matching

Gain

OK?Yes

NoGain Adjustment

I++

40



Techno

Transistors Sizing

NF

min?

Rs f0 Vdd

Ids-min (Wmin,Lmin)


No

Yes

Gain Topology

Choose Inductances

Calculate NF

Impedance Matching

Gain

OK?Yes

NoGain Adjustment

Ids++

41



Techno

Transistors Sizing

NF

min?

Rs f0 Vdd

Ids-min (Wmin,Lmin)


No

Yes

Gain Topology

Choose Inductances

Calculate NF

Impedance Matching

Gain

OK?Yes

NoGain Adjustment

Ids++

42



43



Techno

Transistors Sizing

NF

min?

Rs f0 Vdd

Ids-min (Wmin,Lmin)


No

Yes

Gain Topology

Choose Inductances

Calculate NF

Impedance Matching

Gain

OK?Yes

NoGain Adjustment

Ids++

Ldeg for ReZin=50

Lg for ImZin=0

Gain Adjustment

44



Techno

Transistors Sizing

NF

min?

Rs f0 Vdd

Ids-min (Wmin,Lmin)


No

Yes

Gain Topology

Choose Inductances

Calculate NF

Impedance Matching

Gain

OK?Yes

No

Ids++

Gain Adjustment

45



Techno

Transistors Sizing

NF

min?

Rs f0 Vdd

Ids-min (Wmin,Lmin)


No

Yes

Gain Topology

Choose Inductances

Calculate NF

Impedance Matching

Gain

OK?Yes

No

Ids++

Choice of Lout :

)(

.

outout

outmv

LfZ

ZGA

=

−=

Gain Adjustment

46



Techno

Transistors Sizing

NF

min?

Rs f0 Vdd

Ids-min (Wmin,Lmin)


No

Yes

Gain Topology

Choose Inductances

Calculate NF

Impedance Matching

Gain

OK?Yes

No

Ids++

Cairo+

GiNaC

GiNaC

GiNaC

Introduction

Les paramètres de conception

Circuit proposé

Méthode de conception

Caractérisation automatique

Conception automatique

Exemple de conception

47


Matching Input Impedance

Technologie 0.13 um

Vdd 1.2 V

Résistance de source

(Rs)

50 Ω

Fréquence centrale

(f0)

2.4 GHz

Gain ≥ 15 dB

W (um) L (um) Vgs (V) Vds (V) Ids(mA

)M1 48.96 0.13 0.6 0.6 3.3122

M2 48.96 0.13 0.6 0.6 3.3122

M3 5.08 0.13 0.6 0.6 0.33122

R= 100 KΩ , Rref = 1.811 KΩ , Ldeg = 0.3709 nH , Lg = 48.65 nH , Lout = 3 nH48

Spécifications

Résultats de la procédure proposée


Design Example I: A 2.4GHz LNA in 130 nm CMOS

Zin

(Cairo+)

(Ω)

Zin (ELDO)

(Ω)

50.00 49.5749


Estimated and Simulated Input Impedance

Gain (dB) NF (dB)

Cairo+ 19.14 0.774099

ELDO 19.04 0.727277

50


Estimated and Simulated Gain and NF

S11 (

dB

)S

21 (

dB

)

F (Hz)

51

S11 @ 2.4 GHz =-24.24 dB

S21 @ 2.4 GHz = 17.028 dB


Simulated S Parameters

IIP3= - 0.44 dBm

52

Fondamentale

IM3


Simulated IIP3

)))1(

(100log(10)(

2

0)(21

mWdc

lineaire

PF

fSFOM

−=

53

(*) résultats de simulation

[V. Chandrasekhar, C.M. Hung, Y.C. Ho, and K. Mayaram. “A Packaged 2.4GHz LNA in a 0.15umCMOS Process

with 2kV HBM ESD Protection” , ESSCIRC, 2002]

[1]

[2] *

[3]

[4]

[5]

[6]

[Chandrasekhar 2002]

*


Comparison with state of the art

CIRF Circuit IntégréRadio Fréquencehassan/cirf10_lna_lecture.pdfVin Vout M1 M2 Lout M3 R Rref...

Documents

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