circuit_switch

8/7/2019 circuit_switch

1/15

Circuit SwitchingECE 742: High Speed Networks

0 0


2/15

0 0

Crossbar Switch: a single-stage space division switch

1

2

1 2 N

N

N x N

(a) (b)

1

N

1

N

Figure 1: (a) An NN cross-bar switch; (b) The switching array representation

Figure 1 shows an N N cross-bar switch fabric, a typical space division switch. If the (i, j) crosspoint is on, the ith input is connected to the jth output. A cross-bar switch is internally non-blocking. If two or more packets go to the same output, they suffer output blocking. In this single-stage switch, N2 cross-points are required for full connectivity.

1


3/15

Multi-stage Interconnection Networks (MINs)

Builds larger switch fabric from smaller switch elements (e.g., crossbar orbroadcast switches) in a modular fashion.

Connection pattern consists of switch elements arranged in stages in aregular structure.

Examples: Clos network, Benes network, Banyan Network, Batcher-banyannetwork.

nxk

nxk

nxk

mxm

mxm

mxm

kxn

kxn

kxn

1

2

m

1

2

k

1

2

m

N=m n

input lines

N=m n

output lines

Figure 2: Three-stage Clos network: N = mn. Ifk 2n 1, the switch is non-blocking.

2


4/15

Three-stage Clos network

m first-stage n k switches: N input lines are divided into m groups, andconnected to one of the m switches, where n = N/m.

k intermediate-stage m m switches: each first-stage switch has an outputline connecting it to each of the k intermediate-stage switches.

m last-stage k n switches: each intermediate-stage switch has one outputline connecting it to each of the m last-stage switches.

The n input lines of a group (that enter a common first-stage switch) share kpossible paths to any one of the m last-stage switches; that is, the ith path

goes through the ith intermediate-stage switch, i = 1, 2, . . . , k.

Theorem: The three-stage Clos network is internally non-blocking, if and only if

k

2n

1.

When k < 2n 1, there is nonzero probability that a connection request will bedenied. Computation of such blocking probability is not as trivial as it may

appear. We will defer this problem until a later lecture.

3


5/15

Number of stages and crosspoints:

The number of cross-points C(3) of this three-stage nonblocking Clos

network becomes minimum, when n =

N/2, for which

C(3) = 4N(

2N 1) = O(N3/2). If N is very large, the optimal choice of n = N/2 may be still impractical.

Then we factor N = m n with n m. If we replace each of the k( 2n 1) intermediate-stage switches (m m) by

a three-stage non-blocking switch, then we will obtain a five-stagenon-blocking network. In this case the number of cross-points is O(N4/3).

By proceeding further, Clos (1953) a calculated the the number ofcross-points required for the multi-stage interconnection network (MIN).

Use of a greater number of stages results in a greater saving of cross-points,and a large space-division switch may consist of as many as eight stages of

switches. However, the usage factor of cross-points in space division switchesis inherently low.

aC. Clos, A Study of Non-Blocking Switched Networks, Bell Systems Technical Journal, vol.

32, pp. 406-424, March 1953.

4


6/15

Non-symmetric Clos network

nxk

nxk

m

N=m n

input lines output lines

k

1 1 1

m

kxn

kxnN=m n

mxm

mxm

Figure 3: A Clos network with N = mn input lines and N

= m

n

output lines

Suppose that a subset S N is already connected to a subset S N throughthe switch. If a multicast (i.e., a point-to-multipoint) is allowed, |S| |S|.Definition: Strictly non-blocking (SNB). A switching network is strictly

non-blocking (SNB), if a point-to-multipoint connection can be established

between any idle input line i N \ Sand any subset ofN

\ S

, withoutrearranging any of the connections between Sand S. Definition: Rearrangeably non-blocking (RNB). A switching network is

rearrangeably non-blocking (RNB), if a point-to-multipoint connection can be

5


7/15

established between any idle input line i

N \ Sand any subset of

N

\ S, if

rearrangements of existing connections between Sand S are permitted. Theorem (Clos): A three-stage switching network is strictly non-blocking, if

and only if

k n + n 1.

m

mxm

m

nxk kxn

nxk

X

mxm

1mxmnxk

1 1kxn

kxn

YA

k

(X,A)

(A,Y)

Figure 4: Sufficiency of the condition k n+ n 1

6


8/15

The following theorem is attributed to an unpublished work by Slepian.

Theorem (Slepian): A three-stage switching network is rearrangeably

non-blocking, if and only if

k max{n, n},Furthermore, such a rearrangement will never require reconnecting more than

m + m 2 calls.

Paull (1962)a showed that the number of rearrangements can be reduced.

Theorem (Paull): A three-stage switching network is rearrangeably

non-blocking, if and only ifk max{n, n}. Furthermore, the number of circuitsthat need to be rearranged is at most min{m, m} 1.

a

M. C. Paull, Reswitching of Connection Networks, Bell Systems Technical Journal, vol. 41,pp. 833-855, May 1962.

7


9/15

Time Division Switch

Consider a TDM (time division multiplexed) signals, with T time slots perframe. The time domain analog of an N N space division switch is a T Ttime division switch.

1

2

T

1

2TDM signal TDM signal

T

T x T

Figure 5: Time Division Switch (Time Slot Interchanger)

Data in the T slots of the TDM signals are first demultiplexed. Individual datas time slots are switched or permuted.

Data of the resultant T slots are put together (i.e. time-division multiplexed)

and are sent out.

The time division switch is also known as a time slot interchanger (TSI), as

shown schematically in Figure 6.

8


10/15

DDDD1D

D

D

D

D

D1DDDDD

j=f(i)

2 3 4 51

2

34

5

2345

5

14

23

1i

control

Timing signal

TDM signalTDM signal

Translation table(switchin matrix)

Memory

234 5

Figure 6: Implementation of TSI: Sequential-write, random-read

The T slot data in a frame are written into memory sequentially, i.e. data Diis stored in the i-th memory position.

The stored data are read out according to the switching table, j = f(i), i.e.,the data Di should be sent out at the slot j at the output, where j = f(i),

(1 i, j T). Can accomplish the same result by using the inverse mapping at the write-in

9


11/15

stage: write data of slot j into memory position i = f1(j), and then read

them out sequentially. Then the ith slot in the TSI output contains data

Df(i)(= Dj).

DDDD1D

D

D

D

D

D1DDDDD2 3 4 5

TDM signalTDM signalMemory

234 5

control

2345

2

1

Translation table

switchin matrix

j i=f (j)-1

34

51

3

2

4

5

1

Figure 7: Alternative implementation of TSI: random-write, sequential-read

10


12/15

Combination of Time Division and Space Division Switches

A space division switch S and a time division switch T are mathematically

equivalent.

T21

T21

T21

21 T

21 T

21 T

1

m

2

1

2

m

1

2

k

Space switches Time switchesTime switches

x m x m

N= m T N=m T

x

Figure 8: T-S-T switching network

The total number of inputs is N = mT. We can view that the m parallel inputs

as space division multiplexed (SDM) signals. The outputs are space multiplexed

TDM signals, and the total number of outputs is N = mT.

11


13/15

Time multiplexed space (TMS) switch

The k copies of the space switches (m m) in the middle stage of Figure 8 canbe time-shared: physically it is one m m space switch and its connectionpatterns can be set differently for different time slots. Such a space switch is

called a time multiplexed space (TMS) switch.

T21

T21

T21

21 T

21 T

21 T

1

m

2

1

2

m

Time switches

x

N= m T N=m T

m x m

Time switches

TMS switch

x

Figure 9: A T-S-T switching network with an TMS (time multiplexed space) switch

in the middle stage

12


14/15

Theorem: Non-blocking T-S-T network. The T-S-T switching network of

Figure 8 is non-blocking, if and only ifk T + T 1, and is rearrangeablynon-blocking, if and only ifk max{T, T}. The number of circuits that need tobe rearranged is at most min{m, m} 1.

S-T-S Network:

T21

T21

T21

1

221 T

21 T

21 T

1

2TMS TMS

k x m

T x T

k

TSIs

m x k

m

Figure 10: An S-T-S switching network

The first-stage is an m k TMS switch; the middle stage is a k array of TSIs(T T); and the last stage is a k m TMS switch.

13


15/15

Theorem: Non-blocking S-T-S network. The S-T-S switching network of

Figure 10 is non-blocking, if and only ifk m + m 1, and is rearrangeablynon-blocking, if and only ifk max{m, m}. The number of circuits that needto be rearranged is at most min{T, T} 1.

14

circuit_switch

Documents

Transcript of circuit_switch