Research highlighted in this presentation was supported by CHREC members and by the I/UCRC Centers Program

of the National Science Foundation under Grant Nos. EEC-0642422 and IIP-1161022.

28th Annual AIAA/USU Conference on Small Satellites, 05AUG14

Investigators and Students

Dylan Rudolph, Christopher Wilson, Jacob Stewart, Patrick Gauvin,

Alan George, Herman Lam, Gary Crum, Mike Wirthlin, Alex Wilson, Aaron Stoddard

Research Partners

University of Florida (lead), NASA Goddard, Brigham Young University,

NASA Kennedy, Honeywell, Space Micro, and growing!

CHREC Space Processor A Multifaceted Hybrid Architecture for Space Computing

Outline

• Brief Background

• Major Challenges for Space Computing

• CSP the Concept

• Hardware Architecture

• Flight Software

• Conclusions

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CSP Acknowledgements

3 See www.chrec.org for more info

• CSP is a research project at CHREC

o NSF Center for High-Performance

Reconfigurable Computing (CHREC)

• Founded in 2007

• Comprised of 4 university sites and

over 30 industry and government partners

• CSP is a collaborative CHREC effort

o Original partners:

• University of Florida (lead), NASA Goddard,

and Brigham Young University

o Additional partners:

• NASA Kennedy, Honeywell, Space Micro,

L-3 CE, NASA Johnson, NASA Ames, Xilinx,

and growing!

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Goddard Code 587 Science Data Processing Branch

Advanced Avionics and Architectures Group

• Overall Mission Objective: o “To enable a new class of future Goddard missions by developing

technology for small spacecraft architectures, mission concepts, component subsystem hardware, and deployment methods.”

o Provide strong science rationale for using small spacecraft platforms & constellations

• Two primary application areas o Short-term demo/tests (months)

o Science Missions (1 to 3+ years, orbits other than LEO)

• Key Platforms o Scalable components for 3U, 6U, 12U, SmallSat

o Success with SpaceCube v1, SpaceCube v1.5, SpaceCube v2, SpaceCube Mini and now CSPv1

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Featured Technology

• Field Programmable Gate Array (FPGA) o Large amount of logic resources and specialized

design units connected with a complex and configurable routing network

o Lower frequency and power over conventional CPU

o Massive algorithm parallelism for immense speedup

• System-on-Chip (SoC) o Integrated Circuit that combines many

processing technologies into a single chip

o Xilinx Zynq 7020 • Dual ARM Cortex-A9 processors

• NEON SIMD engines

• Low-power 28nm Artix-7 FPGA

o Some applications are control-flow oriented and better suited for CPUs

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Major Challenges for Space

• Research focus on Advanced Space Computing o New concepts, methods, and technologies to enable

and deploy high-performance computing in space

• Why is it necessary and important? o Escalating demands for sensor-data processing

• Downlink bandwidth to Earth is extremely limited

• Sensor data rates are dramatically increasing

• Post processing is not as viable

o Escalating demands for autonomous processing & control • Autonomy requires high-speed

computing for decision-making

• Severe propagation delays for human in-the-loop for commands

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Space Computing

Requirements

• Embedded space environments have strict requirements and restrictions o Performance (throughput and real-time)

o Size, Weight, Power, and Cost (SWAP-C)

o Reliability (device lifetime and radiation effects)

• Single-Event Effects

• Total Ionizing Dose

• Next-generation satellites and spacecraft will require high-performance processing o Traditional radiation-hardened general-purpose

processors unable to keep up

• Honeywell RHPPC: .08 GOPS*

• BAE Systems RAD750: .266 GOPS*

• Zynq 7020: 324.15 GOPS*

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*GOPS for 8-bit Integer Operations

c/o Device Metrics

CHREC Space Processor

Concept • Goal: Develop CSP as new

approach for space computing

• Multifaceted hybrid space computer o Hybrid system (COTS +

RadHard technology)

o Hybrid processor (multicore + FPGA subsystems)

• Unprecedented computing agility for space o Static & dynamic optimization of

performance, power, & reliability

o COTS technology featured, augmented by RadHard & FTC

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NAND Flash

Power Circuit

Reset Circuit

Watchdog

RSA Reliable Bootstrap

Zynq-7020 SoC

ECC

ADDAM Middleware

FPGA Scrubbing Internal

Watchdog

Redundancy

DDR3 SDRAM

COTS = Commercial off the Shelf

RadHard = Radiation Hardened FTC= Fault-Tolerant Computing

CSPv1 Hardware Design

• CSPv1: New family of small flight-ready

processing boards

• Current status of CSPv1 design:

Completed, verified, & in production

o Completed revisions, manufacturing,

assembly of All-COTS and Hybrid CSPv1

o Confirmed functionality of evaluation board

interfaces and associated HDL design cores

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• Zynq 7020 (ARM dual-core Cortex-A9 + Artix-7 FPGA)

• (1-4) GB NAND Flash • (256 MB–1 GB) DDR3 • Dedicated Watchdog Unit • Internal Power Regulation

• 26 Configurable ARM GPIO Pins

• 12 Single-Ended FPGA I/O Pins

• 24 High-Speed Differential Pairs

CSPv1 Features

CSPv1 Desktop Testbed

• Many-in-One Design o Both COTS and Hybrid options

o Selective population scheme

CSPv1 Dual Format

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COTS Board (COTS+FTC) Hybrid Board (COTS+RadHard+FTC)

COTS+RH+FTC on CSPv1

COTS

• Zynq-7020 hybrid SoC

o Dual ARM A9/Neon cores

o Artix-7 FPGA fabric + hard IP

• DDR3 memory

11 Reference Slide

RadHard

• NAND flash

• Power circuit

• Reset circuit

• Watchdog unit

FTC = Fault-Tolerant Computing o Variety of mechanisms

• External watchdog unit to monitor Zynq health and reset as needed

• RSA-authenticated bootstrap (primary, secondary) on NAND flash

• ECC memory controller for DDR3 within Zynq

• ADDAM middleware with message, health, and job services

• FPGA configuration scrubber with multiple modes

• Internal watchdogs within Zynq to monitor behavior

• Optional hardware, information, network, software, and time redundancy

CSPv1 System Description

12 Reference Slide

• Requires 3V3 and 5V0, other

voltages generated on-board

o 1.7 – 3.5 W depending on

maximum load state

• 160-pin Samtec Searray

connector (no other I/O)

o 60 High-Speed FPGA I/O pins

o 26 High-Speed ARM I/O pins

• Watchdog circuit based

around Intersil supervisor

• Other information:

o 50-60 grams loaded

o 1U form factor (10x10 cm)

o 62 mil thickness, 12-layer PCB

o 2x256MB DDR3 RAM

Flight Software

o Integrate system using cFE/CFS

framework for flight systems

o Support key interfaces desirable

for aerospace applications

(Camera Link, SpaceWire)

o Key Scrubbing Modes (Frame

-ECC, Blind Scrub, Readback)

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FPGA Fabric

FPGA Cores

Communication

Interfaces

Partial Reconfiguration

Region

FPGA Cores

Processing System

Wumbo GNU/Linux

Reliable Bootstrap

Kernel

Modules Core Flight Executive

Comm.

Interfaces

Partial

Reconfig.

Controller

Hardware

Accelerated

Applications

Aerospace

Middleware

Applications AXI-4

Bus

Please consult CSP @ MAPLD14 Conference

for more detailed software discussion

• Goal: Develop flight platform supporting hybrid

computing and adapted for a hazardous environment

• Highlighted Features:

o Provide reliable bootstrap

with redundant boot images

o Minimal OS: Wumbo GNU/Linux

o Fluid processor/FPGA comm.

Core Flight Executive

• Integrate with NASA Goddard’s reusable

flight software framework

o Open source version available at SourceForge

o Perform local device management, software

messaging, & event generation

• Core Components

o Core Flight Executive (cFE): Mission-independent software services

o Core Flight System (CFS): Applications and libraries running on cFE

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Software Bus

cFE Core Stored

Commands Health &

Safety Scheduler

File

Manager

Other

Apps

Watchdog Camera

Support Time Sync

Image

Self

Check

Scrubber

PR Error

Logging SpaceWire

cFE Core

CFS Apps

Mission Apps

Core Flight System

NASA Missions for CSPv1

• Two confirmed for NASA Goddard o CSP featured as new technology for space computing

• NASA technology mission o STP-H5/ISEM on ISS – late 2014 delivery

o Two CSPv1 computers working in tandem

o SpaceWire, Camera Link, reconfiguration

• NASA science mission o CeREs Cubesat – early 2015 delivery to NASA

o Heliophysics experiment in LEO

o One CSPv1 computer for on-board processing

• Additional missions in planning o e.g., EPIC (Earth Photosynthesis Imaging Cluster) satellites

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Artist Illustrations (c/o NASA)

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Conclusions

• Major challenges lie ahead o Escalating app demands in harsh environment

o Tightening constraints of platform, budget, process

o Necessitates adeptly doing more with less

• CHREC Space Processor o Focus upon reconfigurable space computing

• Adaptive (performance, reliability, power) for mission needs

o Focus upon multifaceted hybrid computing • Agile mix of COTS + RadHard + FTC; fixed & reconfigurable

o Focus upon scalable building blocks • Address needs of small, large, & clustered spacecraft

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Questions?

More information?

Dr. Alan D. George (PI), Professor of ECE and Director NSF Center for High-performance Reconfigurable Computing (CHREC) University of Florida, Dept. of Electrical and Computer Engineering Room 327, Larsen Hall, 968 Center Drive, POB 116200Gainesville, FL 32611-6200 Office: (352)392-5225, Fax: (352)392-8671, Lab: (352)392-9038 Email: ageorge@ufl.edu or george@chrec.org

Gary Crum, Aerospace Technologist - Data Systems Code 587 - Science Data Processing Branch NASA Goddard Space Flight Center Building 23, Room W315 Greenbelt, MD 20771 Office: (301) 286-3713 Email: gary.a.crum@nasa.gov

Dr. Mike J. Wirthlin, Professor of ECE

NSF Center for High-performance Reconfigurable Computing (CHREC) 459 Clyde Building, Brigham Young University, Provo, Utah 84602 Office: 801-422-7601 Email: wirthlin@ee.byu.edu

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