Chip Submission 491 599 Report

8/9/2019 Chip Submission 491 599 Report

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For Detailed VLSI Lab information:

http://analog.ece.utk.edu/ece491.htm

Final Project

Designing a 4-bit Counter or Flip-Flop

The final design project will require you to design a moderately comple VLSI design

circuit! For this class we choose to design a Flip"flop for the #ndergrad student and a $"

bit counter for %raduated Student! This project will be done individually!

Grad Student: Design a $"bit &ounter!

Undergrad : Design a flip"flop '(")* T or D flip"flop+ that has a &loc,ed Input withthe option of Set-.eset* &lear or /nabled!

0ou need tojustify in your presentation and .eport* why you choose a particular typeof flip"flop or counter! Grading will be done according to the quality of design!

Grading: This project will carry 20% of the whole course!

1roject grading is subdi2ided as follows:

34 5 1roject 1resentation34 5 .eport 6riting

47 5 Simulation 8 quality of project

977 5 Total

Follow the #T) &adence tutorial to draw a schematic of all the basic gates using the

ami7 library! #se the Tutorial lin,

http:--analog!ece!ut,!edu-&adence-ut,;schematic!htm

I"7!micron process for this final project!

=ssume width* for

Length of the transistor will be 7! micron!

1ic, up the width of p"mos and n"mos! 0ou need to justify in the report regarding the

width!
http://analog.ece.utk.edu/ece491.htmhttp://analog.ece.utk.edu/ece491.htm


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&reating the Symbol* http:--analog!ece!ut,!edu-&adence-create;symbol!htm

Simulationg by Spectra http:--analog!ece!ut,!edu-&adence-spectre!htm

LVS geneation http:--analog!ece!ut,!edu-&adence-LVS!htm

Follow the following lin, to get a good eample of the whole design:http:--2lsi9!engr!ut,!edu-?nislam-main!htm

0ou are required to do the following for the final project:

9! /nter a 9"bit fet"le2el schematic using &adence &omposer and perform pre"layout

simulations

3! #se Virtuoso to produce a manual layout from the &omposer schematic that conformsto the height format 'any height+* perform a D.& chec, and post"layout simulations

using Spectre!

@! Students will run all simulations and generate LVS!

$! .ise time* Fall time* 1ropagation delay will also be calculated! =dd capacitance to your

output! Vary the &apacitance to get different delay!

Submit the plot of delay vs Load capacitance Ause your fa2orite plotting tool*>atlab or /celB !

4! 1repare the final report by capturing gif files to illustrate the layouts and simulations!

Include a narrati2e description of your project!

! Is there any application of your flip"flop or counterC %i2e details in your report!

Presentation will include all the simulation results! .ise time* Fall time*1ropagation delay* plot of delay 2s Load will also include in your presentation slide!

SAMPL !P"!#:

$. "%jecti&e:

The objecti2e of this project is to design a $"bit counter and implement it with the help of

&adence 'custom I& design tool+ following necessary steps and rules dependent on

selected process technology!

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$$. Selection o' counter to %e de(igned:

In my project I ha2e designed a $"bit synchronous counter with serial carry loo, ahead

and synchronous reset! Some salient features and ad2antages ha2e inspired me to go for

this type of counter* which are gi2en below"

Synchronous counter is considered as one of the most popular and widely used

counter!

Since same cloc, signal is gi2en to all the fundamental bloc,s 'Flip Flop+ of the

counter* no interrupt can occur in the middle of a state transition!

It pro2ides low propagation delay in comparison to asynchronous counter!

The output le2el of the counter is free from glitch* which ensures us about the

reliability of digital logic control!

$$$. Selection o' Flip 'lop:

Flip"flop is the fundamental building bloc, of counter! So* wise selection of flip flop is a

2ital point in designing a counter! Toggling operation of T "flip flop is 2ery efficient in

designing synchronous counter! ut I ha2e decided to design a () flip flop due to

following reasons"

() flip"flop is the most 2ersatile of basic flip"flops!

oth T and D flip flop can be easily generated from it!

6e can easily implement set and reset logic of the counter by using set and reset

mode of () flip"flop!

$V. )e(ign Step(:

@


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&adence is one of the most popular* efficient and commercial custom I& design tool!

There are some sequential steps that we ha2e to follow strictly for fruitful I& design!

These steps are mentioned below"

Figure 1: Flowchart of design steps

V. *+ Filp Flop:

$

Design Specification

Schematic Capture

Create Symbol

Simulation

Layout

DRC- Design rule Check

Extraction

LVS - Layout vs Schematic

Check

Post layout Simulation


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>aster sal2e edge triggered flip flop is more preferable in I& design due to its reliable

output! The characteristics table of () flip"flop is:

#a%le 1: Truth table of () flip flop

( ) En97 7 En7 9 7

9 7 9

9 9 EnG

Schematic:

Figure ,: Schematic diagram of () flip flop

>aster"sla2e cross couple


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negligible in case of digital circuit in comparison to the effect produced by load

capacitance! To implement synchronous reset logic 9 =


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#a%le ,: Truth table of $ bit synchronous up counter!

State(0ount

) 0 A

7 7 7 7 7

7 7 7 9 9

7 7 9 7 3

7 7 9 9 @

7 9 7 7 $

7 9 7 9 4

7 9 9 7

7 9 9 9 J

9 7 7 7 K

9 7 7 9

9 7 9 7 97

9 7 9 9 99

9 9 7 7 93

9 9 7 9 9@

9 9 9 7 9$

9 9 9 9 94

=ccording to the truth table* it can be noted that = must change state with e2ery input

cloc, pulse! This can be easily implemented by using a T flip"flop! ut e2en with () flip"

flops* all we need to do here is to connect both the ( and ) inputs of this flip"flop to logic

9 in order to get the correct acti2ity! must change state only when output = is a logic 9*

but not when = is a logic 7! So* if we connect output = to the ( and ) inputs of flip"flop

* we will see output beha2ing correctly! =gain* & must change state only when both =

and are logic 9! 6e canMt use only output as the control for flip"flop &N that will allow

& to change state when the counter is in state 3* causing it to switch directly from a count

of 3 to a count of J* and again from a count of 97 to a count of 94 O not a good way to

count! Therefore we will need a two"input =


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of D will change only when the logic le2el of =* and & are high! So we can use same

method for D flip flop!

=n additional pin for serial carry loo, ahead is implemented for cascading purpose!

Sometimes we may need to construct a Kbit synchronous counter by using two $ bit

counter! Then we will need the serial carry bit generated from pre2ious counter!

Schematic:

Figure : Schematic diagram of $ bit synchronous counter

Simulated waveform from schematic at 2!"# cloc$ fre%uency:

K


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Figure 2: Simulated wa2e shape from schematic

Layout:

The layout of the counter has been tried to ma,e as small as possible using fewinterconnection! Four flip flops are placed at four corners and @ and gates are placed in

the middle! I ha2e used up to metal3 layer for interconnection! The layout would ha2e

been more compact if I would use metal@ layer! The final sie of the layout is 99$!$4 m

by K@ m* which can be considered as a usual sie of a $bit counter!


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Figure 3: &adence layout of $ bit counter

&'tracted Layout:

Figure : /tracted layout of $ bit counter

97


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Simulated waveform from e'tracted layout at (!"# cloc$ fre%uency:

Figure 9: 6a2eform of counter at 9 >P cloc,!

Simulated waveform from e'tracted layout at (!"# cloc$ fre%uency with )eset:

Figure 15: 6a2eform of counter at 9 >P cloc, with reset operation!

99


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V$$. Some 6treme 0a(e(:

Simulated waveform from e'tracted layout at 2!"# cloc$ fre%uency:

Figure 11: 6a2eform of counter at 377 >P cloc,

Simulated waveform from e'tracted layout at (!"# cloc$ fre%uency with 4pF load:

Figure 1,: 6a2eform of counter at 97 >P cloc, with $pf load capacitance

93


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V$$$. Mea(urement o' !i(e #ime7 Fall #ime and Propagation )ela:

@7Q?J7Q method is used to measure the rise time and fall time! Hn the other hand

47Q?47Q method is used in case of measuring propagation delay! =t first these

parameters are measured with out load* which represent the effect of parasitic

capacitance! =fterward* same capaciti2e load is applied to the output node of each flip

flop to analye the loading effect!

!easured data at different cloc$ fre%uencies:

#a%le -: .ise time* fall time and delay at different output nodes!

!i(e #ime 8p( Fall #ime 8p( )ela 8p(

'clock8M; = & D = & D = & D

9 @3!$9 339!33 97!3 9J! 337!J3 94J!3J 9@@!9 9@!4 @9!J9 433! $K!K $4!@

97 @3@!K@ 39J!$ 9K!$4 9!$K 39J! 944!4 9@3!$ 9@$!4J 3K!4K 433! $K!3@ $4!9

47 @3!$K 39K!$9 9K!9@ 94!4 334!4 944!7K 9@3!K 9@$!39 @9!J$ 433!$ $K!J $4!3

977 @3$!$ 39K!$$ 9K!@@ 94!J 39K!K@ 94$!@ 9@@!7$ 9@$!J@ 3K!44 43@!7@ $KK!K $4!K

!easured data at different capacitive loads with (!"# cloc$ fre%uency:

#a%le 4: .ise time* fall time and delay at different output nodes in loaded condition!!

!i(e #ime8n( Fall #ime 8n( )ela 8n(

0load8pF= & D = & D = & D

9 @!9 @!7 @!7@ @!74 @!$3 @!@$ @!@3 @!@9 $!K$ $!J $! $!J3

3 4!K4 4!J3 4!J@ 4!J4 !4J !$ !49 !49 K!3 K!J K!J K!JJ

@ K!4@ K!$9 K!@J K!$3 !J ! !K !J 93!4 93!K9 93!K9 93!K@

$ 99!39 99!7 99!7@ 99!73 93!4 93!KK 93!K 93!K 9!J 9!K@ 9!K9 9!K4

=bo2e tables show the loading effect on the output node of the counter! There is

negligible 2ariation in rise time* fall time and propagation delay* if we increase the cloc,

9@


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frequency at no load condition! ut there is almost linear increment of these 2alues with

the increase of capaciti2e load!

Following figures show the 2ariation of rise time* fall time and propagation delay with

frequency at no load condition:

Rise Time without Load

!

"

"!

#

#!

$

$!

" " ! "

Clock Frequency (MHz)

T

ime(ps)

%

&

C

D

Figure 1-: Variation of rise time with frequency

Fall Time without Load

!

"

"!

#

#!

" " ! "


Time(ps) %

&

C

D

Figure 14: Variation of fall time with frequency

9$


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Propaation !elay without Load

"

#

$

'

!

(

)

" " ! "


Time(ps) %

&

C

D

Figure 1: Variation of propagation delay with frequency

Following figures show the 2ariation of rise time* fall time and propagation delay with

load capacitance at 97>P cloc, frequency:

Rise Time with Load

#

'

(

*

"

"#

" # $ '

Load Capacitance (pF)

Time(ns) %

&

C

D

Figure 12: Variation of rise time with load capacitance!

94


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Fall Time without Load

#

'

(

*

"

"#

"'

" # $ '


Time(ns) %

&

C

D

Figure 13: Variation of fall time with load capacitance!

Propaation !elay with Load

#

'

(

*

"

"#

"'

"(

"*

" # $ '


Tim

e(ns) %

&

C

D

Figure 1: Variation of propagation delay with load capacitance!

Though there are slight 2ariations in rise time fall time and propagation delay among four

output nodes* they show eactly same beha2ior at loaded condition! So* parasitic

capacitance has negligible effect in comparison to load capacitance!

$


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&ounter can be considered as a heart of different digital and analog circuit! There are 2ast

applications of counter in the field of electronics! Hnly few of them are mentioned below"

Some times we need different cloc, frequencies for the operation of different

parts of a large circuit! In that case counter can be efficiently used as a frequency

di2ider! From a $ bit synchronous counter we can get four different frequencies

with a multiple of two!

Digital counter acts as a ,ey part in the implementation of time dependent digital

logic control circuit! &offee 2ending machine* microwa2e o2en etc!" are some

2ery good eample of such ,ind of circuits

Laout o' the Student(

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Laout 11

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Laout 1-

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Chip Submission 491 599 Report

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