h d lChip Macro ModelsEnabling 3D‐IC and IC‐Package‐PCB Co analysisPCB Co‐analysis

Ji Zheng, Ph.D.Director of Chip‐Package‐System

© 2011 ANSYS, Inc. August 25, 20111

Apache Design, a wholly‐owned subsidiary of ANSYS

Chip‐Package‐System (CPS) Solutions

Power IntegrityPower Integrity

Signal IntegritySignal Integrity

EMI/EMC

Thermal Integrity

© 2011 ANSYS, Inc. August 25, 20112

On‐die Power Ground Network

Vdd Pad

L RRCdevRpg

Cpg

L

Cmacro

Rmacro

Cdecap

Rdecap

Rload

Rpg

Cload Cload

macrodecapVss Pad

Non-switching instanceOutput: 1->1

Switching instance

© 2011 ANSYS, Inc. August 25, 20113

Chip Power Model (CPM)

CHIP DATA

Layout (Early or Sign‐off)

Library

CHIP ANALYSIS

DynamicStatic Dynamic 

VCD

Dynamic Smart 

VectorLess

Static (Iavg, R)Frequency domain (RLC)Modes

Chip Power Model

© 2011 ANSYS, Inc. August 25, 20114

Time‐domain (I(t), RLC)

Accuracy / Self‐consistency Correlation

VDD CurrentVDD Current

CPM‐SPICERedHawk™

VSS Current

© 2011 ANSYS, Inc. August 25, 20115

Enabling Global PDN Analysis

CPM

System ACSimulation

Package/PCB DC Analysis

© 2011 ANSYS, Inc. August 25, 20116

Decap Planning System TransientSimulation

Enabling 3D‐IC Power Integrity Analysis

Higher Voltage Drop in the Center Due to

Memory Die

Voltage Drop Map of Single Logic Die

© 2011 ANSYS, Inc. August 25, 20117

SiP Multi‐die Power Integrity

© 2011 ANSYS, Inc. August 25, 20118

Enabling PDN Emission Simulation for EMI

Measurement Correlation for Conducted Emission

Radiated EmissionConducted Emission

Original Design

© 2011 ANSYS, Inc. August 25, 20119 With Added Decaps

I/O Sub‐system Noise and Timing

DDR Circuit DesignDesign(SPICE Netlist)

RDL Design

IO Ring Place & R t

DDR Subsystem

Design(GDS / DEF)

Route(DEF / GDS

/ LEF)

Subsystem Sign-off

Package Design

SoC Core Physical Design

(S / RLCK)

PCB &

yDesign

(CPM)

© 2011 ANSYS, Inc. August 25, 201110

Decaps(S / RLCK)

Chip Signal Model (CSM)

vsso

CSM

vddcModels non‐linear I/O behavior & P/G parasitics

Speed‐up DDR system simulationEnables DDR C‐P‐B co‐verification

vddc

vddo

vsso

CSM

vddc vddo

© 2011 ANSYS, Inc. August 25, 201111

Correlation with full transistor modelCorrelation with full transistor model

Non‐linear I/O Macro‐Model

• Chip Signal Model (CSM) employs proprietary l / d l hnon‐linear I/O macro‐model to represent the 

complex I/O devices

• Non‐linear I/O macro‐modelhi i l l• Achieves transistor‐level accuracy

• Preserves power / ground noise fluctuation impact on signal timing and noiseon signal timing and noise

• Significantly reduces circuit complexity

© 2011 ANSYS, Inc. August 25, 201112

I/O Cell Black Box Model

( , )i f u ( , )i f u

Xtor Cell I/O Cell Model

[ ; ; ; ]u Vin Vout Vdd Vss

• Model input: u (input, output and power/ground voltage)

• Model output: i (Iout or Idd or Iss, current at P/G or output pin)

• Parametric model: f (composition of artificial Neutral Network and Local Linear State Space)

© 2011 ANSYS, Inc. August 25, 201113

• Model parameters: θ (coefficients parametric model)

Enabling Fast and High Capacity SSO Analysis

5 Transistor w/ 27bit IBIS Power Noise Aggressor Model

32bit CSM

32bit All Transistor Upper waveform:   Victim netMiddle waveform:  Power netLower waveform:   Ground net

Run Time (s) VDD Swing (V) # Nodes # Elements # MosfetsAll-Transistor 12000 0.24 1021805 1701143 113088

All CIOM 1750 0 239 7328 7805 0

5 Transistor w/ 27bit IBIS  Power Noise Aggressor Model

© 2011 ANSYS, Inc. August 25, 201114

All-CIOM 1750 0.239 7328 7805 0

Transistors + IBIS 4070 0.38 160073 266336 17670

Thermal – A Key to 3D‐IC Reliability

• Leakage Power

• Electromigrationg

• TSV Design• TSV Design

• Active Device Integration in Silicon Interposer

© 2011 ANSYS, Inc. August 25, 201115

Chip Thermal Model (CTM)

Power Density map over temperature

Tile based metal density per layer from die physical geometry and dielectric (P d Si l ti )

© 2011 ANSYS, Inc. August 25, 201116

(Power and Signal routing)

Enabling Chip‐Package Thermal Co‐analysis

P k L tChi Th l M d l Package LayoutSentinel-TI Analysis

Chip Thermal Model(RedHawk/Totem)

Package/PCB Temperature Map

© 2011 ANSYS, Inc. August 25, 201117

Enables temperature dependent power and EM calculations

Enables temperature dependent power and EM calculations

8/25/2011, 17

Die Temperature Map

Enabling Thermal Co‐analysis for 3D‐IC

Memory

Logic

Bumps, Micro-bumps, and TSVs

© 2011 ANSYS, Inc. August 25, 201118