CHIP_FINISH_ICC.TCL

The purpose of this script is to execute the following chip finishing steps:

Antenna Fixing against the plasma effect. Critical area reduction by executing timing driven detail route wire

spreading and widening. Redundant VIA insertion. Standard Cell Filling.

A few of the important variables used in this script are:

ICC_FIX_ANTENNA: [BOOLEAN TRUE/FALSE] Instructs chip finish script to run antenna fixing or not.

ANTENNA_RULES_FILE: Defines the technology specific antenna rules to be used as constraints to fix antenna variables.

ICC_REDUCE_CRITICAL_AREA: [BOOLEAN TRUE/FALSE] Defines whether to run detail route wire spreading to fix critical area yield violations.

ADD_FILLER_CELL: [BOOLEAN TRUE/FALSE] To define whether you want to run cell filler commands.

FILLER_CELL_METAL: List of filler cells which contain metal. FILLER_CELL: List of filler cells without metal.

Preventing Antenna Problems:

In chip manufacturing gate oxide can be easily damaged by electro-static discharge. The static charge that is collected on wires during the multi-level metallization process can damage the device or lead to a total chip failure. The phenomenon of an electro-static charge being discharged into the device is referred to as either Antenna or Charge-collecting antenna problems.

To prevent antenna problems, ICC verifies that the metal antenna area divided by the input pin gate area is less that max antenna ratio given by: (antenna-area)/ (gate-area) < (max-antenna-ratio).

Critical Area:

Critical Area is a region of design where, if the center of a random particle defect falls there, the defect will cause circuit failure, thereby reducing yield.

To reduce the critical areas in a design the ICC tool provides options to increase the average distance between wires and average width of wires known as Metal Spreading and Metal Widening respectively.

Standard Cell Fillers:

Usually the standard cell rows in a layout have spaces between successive standard cells. To maintain the continuity of wells in the layout, we can add standard cell fillers in between them. These filler cells are physical only cells and are usually non-logic cells which may or may not contain metal in them. The filler cells which contain metal are used by the tool only if they are DRC clean and would not cause any violations when placed in between two standard cells.

The detail flow of the script is as follows:

Open Milky Way lib & detail route optimized cell

Source settings scripts

Common optimization Common SI settings

Different types of Filler cells that can be used in the PD flow as and when required are discussed below.

Source settings scripts

Spare Cells: Spare Cells are used in the freeze silicon ECO flow. They accommodate late arriving design changes. They are inserted before or after placement and are used when the placement is fixed. With spare cells, you can perform simple logic changes by updating only one or a few metal and via masks, thereby saving the considerable expense of generating a whole new set of silicon-layer masks. They are most useful when they are physically near the location of the logic that needs to be changed. Therefore, spare cells need to be dispersed across the chip rather than gathered in one or several tight locations.To add spare cells you can:

1. Manually instantiate and place spare cells into the verilog netlist before reading the netlist into ICC.

2. Use insert_spare_cells command: Here a specified number of lib cells are placed into a legally placed design. They do not affect existing placement.

Tie Cells: These are special purpose std cells whose output is constant high or constant low and is used to hold the input of another cell at the given constant value. Tie cell optimization refers to using a single tie cell to hold as many inputs as possible at a given logic level while meeting specified max fan-out & max capacitance constraints.

End Cap Cells: After placing std cells and before routing, you can add end cap cells at both ends of a cell row. Typically an end cap cell is a non-logic cell that serves a certain purpose for the row such as providing a decoupling capacitor for the power rail. ICC accepts any std cell as an end cap cell so be sure to specify a suitable end cap cell.To insert end caps use add_end_cap command & also specify the cell to use for end cap. By default, the command places the specified lib cells in their

default orientation at both ends of the horizontal cell rows without considering padding, blockages (hard and soft), or keep-outs.

Well filler cells: After routing is complete, you can fill small gaps that violate the spacing rule for the well layer with well filler cells. You can fill gaps between cells in the same row or between rows. To insert well fillers you can use the command insert_well_filler, by default, only the gaps between standard cells within a row are filled.

Pad filler cells: After routing is complete you can fill gaps in the pad ring with instances of pad filler cells. These are dummy pad cells that you can use to control the pad spacing & complement the n-well taps in pads. The command that can be used to insert pad filler cells is insert_pad_filler.

Tap cells: Tap cells are special non-logic cells with well & substrate ties. These are typically used when most or all of the std cells in the library contain no substrate or well taps. Generally, the design rules specify the max distance between every transistor in a std cell & a well or the substrate ties.Taps can be inserted in a design before or after placement.

1. Before placement to ensure that the placement complies with the max diff to tap limit.

2. After placement to fix max diff to tap violations.