Simultaneous Layout Migration and Decomposition

for Double Patterning TechnologyChin-Hsiung Hsu, Yao-Wen Chang, and Sani Rechard Nassif

From ICCAD09

OutlineINTRODUCTIONPROBLEM FORMULATIONSIMULTANEOUS LAYOUT MIGRATION AND

DECOMPOSITION FLOWPotential DPT-Conflict Graphs and Pattern

SplittingDPT-aware Constraint GraphsBasic ILP FormulationILP Problem-Size ReductionDPT-aware Standard Cells

EXPERIMENTAL RESULTS

INTRODUCTIONDouble patterning

technology (DPT) and layout migration (LM) are crucial technologies for chip manufacturing in the nanometer era.

Due to their interplay, it is necessary to consider the effects of the two technologies simultaneously to obtain a better design flow for manufacturability enhancement.

Sub-pattern geometric closeness

OutlineINTRODUCTIONPROBLEM FORMULATIONSIMULTANEOUS LAYOUT MIGRATION AND

DECOMPOSITION FLOWPotential DPT-Conflict Graphs and Pattern

SplittingDPT-aware Constraint GraphsBasic ILP FormulationILP Problem-Size ReductionDPT-aware Standard Cells

EXPERIMENTAL RESULTS

PROBLEM FORMULATION( SMD problem)Input: original layout L ,double-patterning

spacing Sd minimum overlap length lo for splitting patterns

Output: decomposed and migrated layout L*Objective: minimize # of stitch ,area of

layout and the sub-pattern geometric closeness

Constraint: design rule constraints ,DPT constraints and minimum-overlap-length constraints.

OutlineINTRODUCTIONPROBLEM FORMULATIONSIMULTANEOUS LAYOUT MIGRATION AND

DECOMPOSITION FLOWPotential DPT-Conflict Graphs and Pattern

SplittingDPT-aware Constraint GraphsBasic ILP FormulationILP Problem-Size ReductionDPT-aware Standard Cells

EXPERIMENTAL RESULTS

SIMULTANEOUS LAYOUT MIGRATION AND DECOMPOSITION FLOW

Potential DPT-Conflict Graphs and Pattern SplittingIn traditional DPT-conflict graph, a node is

introduced to represent a tile, and two tiles are connected by an edge if their spacing is smaller than Sd. Not suitable for this SMD problem

Potential DPT-Conflict Graphs and Pattern SplittingThis paper construct an edge between two

adjacent tiles even if their spacing is larger than Sd.

DPT-aware Constraint GraphsGeneral edges

Inter-layer constraint (ex: a contact is covered by a metal)

Intra-layer constraint (ex: the minimum width and minimum spacing)

DPT-aware minimum-overlap-length constraints (ex: two tile should overlap with each other for a certain length

at the junction for a stitch)

Optional edges (two tiles can be separated along either the x- or y-

direction and at least one separation constraint is satisfied)

DPT edges(If two tiles are connected by a DPT edge, their spacing

needs be at least Sd only if they are on the same mask)

Basic ILP Formulation

Boundary constraints

DRC constraints

DPT constraints

Stitch constraints

A

C

B

A

B

Cd1 d2

D

D

Horizontal Constraint Graph

Stitch

ds

Distance(ti,tj)<=ds

Linearization

<=0

= 0

Linearization

Linearization

ILP Problem-Size Reduction

If a tile is connected and can be pseudo-colored with a different color without inducing a stitch, the tile and the connecting edge are included into the subgraph.

ILP Problem-Size Reduction

reduces the ILP variables by 44.7%, the ILP constraints by 58.2%, andthe DPT edges by 79.9% on average

DPT-aware Standard Cells

DPT-aware Standard Cells

OutlineINTRODUCTIONPROBLEM FORMULATIONSIMULTANEOUS LAYOUT MIGRATION AND

DECOMPOSITION FLOWPotential DPT-Conflict Graphs and Pattern

SplittingDPT-aware Constraint GraphsBasic ILP FormulationILP Problem-Size ReductionDPT-aware Standard Cells

EXPERIMENTAL RESULTS

EXPERIMENTAL RESULTS

Testcases form UMC 90nm Free libraryand two artificial casesTesting process is 32nmDPT spacing is 64nm(112nm) for poly(metal)

EXPERIMENTAL RESULTS