Cherry Trail SoC Trail SoC... · 2020. 8. 20. · Document Number: 539071 Cherry Trail SoC External...

Document Number: 539071

Cherry Trail SoCExternal Design Specification (EDS) (Volume 1 of 2)

For Volume 2 of 2 refer Document ID: 543698

June 2014

Revision 1.2

Intel Confidential

2 Intel Confidential 539071

INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.A “Mission Critical Application” is any application in which failure of the Intel Product could result, directly or indirectly, in personal injury or death. SHOULD YOU PURCHASE OR USE INTEL'S PRODUCTS FOR ANY SUCH MISSION CRITICAL APPLICATION, YOU SHALL INDEMNIFY AND HOLD INTEL AND ITS SUBSIDIARIES, SUBCONTRACTORS AND AFFILIATES, AND THE DIRECTORS, OFFICERS, AND EMPLOYEES OF EACH, HARMLESS AGAINST ALL CLAIMS COSTS, DAMAGES, AND EXPENSES AND REASONABLE ATTORNEYS' FEES ARISING OUT OF, DIRECTLY OR INDIRECTLY, ANY CLAIM OF PRODUCT LIABILITY, PERSONAL INJURY, OR DEATH ARISING IN ANY WAY OUT OF SUCH MISSION CRITICAL APPLICATION, WHETHER OR NOT INTEL OR ITS SUBCONTRACTOR WAS NEGLIGENT IN THE DESIGN, MANUFACTURE, OR WARNING OF THE INTEL PRODUCT OR ANY OF ITS PARTS.Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined”. Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The information here is subject to change without notice. Do not finalize a design with this information.The products described in this document may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request.Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.*Other names and brands may be claimed as the property of others.Copyright © 2013-2014, Intel Corporation. All rights reserved.


Contents

1 Introduction ............................................................................................................211.1 Cherry Trail SoC Packages .................................................................................. 221.2 Terminology ..................................................................................................... 251.3 Feature Overview .............................................................................................. 26

1.3.1 Processor Core....................................................................................... 261.3.2 System Memory Controller....................................................................... 261.3.3 Display Controller ................................................................................... 271.3.4 Graphics and Media Engine ...................................................................... 271.3.5 Image Signal Processor ........................................................................... 271.3.6 Power Management ................................................................................ 271.3.7 PCI Express* ......................................................................................... 281.3.8 USB Controller ....................................................................................... 281.3.9 Low Power Engine (LPE) Audio Controller................................................... 281.3.10 Storage................................................................................................. 291.3.11 Intel® Trusted Execution Engine (Intel® TXE) ........................................... 291.3.12 Serial I/O (SIO) ..................................................................................... 291.3.13 Platform Control Unit (PCU) ..................................................................... 291.3.14 Gaussian Mixture Modeling (GMM)* .......................................................... 291.3.15 Intel®Sensor Hub................................................................................... 301.3.16 Package ................................................................................................ 30

2 Physical Interfaces .................................................................................................. 312.1 Pin States through Reset .................................................................................... 312.2 System Memory Controller Interface Signals ......................................................... 33

2.2.1 DDR3L-RS ............................................................................................. 332.2.2 LPDDR3 ................................................................................................ 35

2.3 USB Controller Interface Signals.......................................................................... 362.3.1 USB2.0 Interface Signals......................................................................... 362.3.2 USB HSIC Interface Signals ..................................................................... 372.3.3 USB3.0 Interface Signals......................................................................... 37

2.4 Integrated Clock Interface Signals ....................................................................... 392.5 Display - Digital Display Interface (DDI) Signals .................................................... 392.6 MIPI DSI Interface Signals.................................................................................. 402.7 MIPI Camera Serial Interface (CSI) and ISP Interface Signals.................................. 412.8 PCI Express Signals ........................................................................................... 422.9 Low Power Engine (LPE) for Audio (I2S) Interface Signals ....................................... 422.10 Storage Interface Signals ................................................................................... 43

2.10.1 Storage Controller (eMMC, SDIO, SD) ....................................................... 432.11 High Speed UART Interface Signals...................................................................... 442.12 I2C Interface Signals.......................................................................................... 452.13 NFC I2C Interface Signals ................................................................................... 462.14 PCU- Fast Serial Peripheral Interface (SPI) Signals................................................. 462.15 PCU - Real Time Clock (RTC) Interface Signals ...................................................... 472.16 PCU - Low Pin Count (LPC) Bridge Interface Signals ............................................... 472.17 PCU - Power Management Controller (PMC) Interface Signals .................................. 482.18 Serial Peripheral Interface (SPI) Signals ............................................................... 492.19 JTAG Interface Signals ....................................................................................... 492.20 Integrated Sensor Hub Interface Signals............................................................... 492.21 PWM Interface Signals ....................................................................................... 502.22 Miscellaneous Signals......................................................................................... 51


2.23 Hardware Straps................................................................................................512.24 SoC RCOMP List.................................................................................................532.25 GPIO Muxing.....................................................................................................54

3 Processor Core.........................................................................................................913.1 Features...........................................................................................................91

3.1.1 Intel® Virtualization Technology (Intel® VT) ...............................................913.1.2 Security and Cryptography Technologies....................................................933.1.3 Power Aware Interrupt Routing.................................................................94

3.2 Platform Identification and CPUID ........................................................................943.3 References........................................................................................................94

4 SoC Transaction Router............................................................................................964.1 Register Map.....................................................................................................96

5 Integrated Clock ......................................................................................................97

6 Power Up and Reset Sequence .................................................................................996.1 SoC System States ............................................................................................99

6.1.1 System Sleeping States Control (S-states) .................................................996.2 Power Up Sequences ..........................................................................................99

6.2.1 RTC Power Well Transition (G5 to G3 States Transition) ...............................996.2.2 G3 to S4/S5.........................................................................................1006.2.3 S4/S5 to S0 .........................................................................................101

6.3 Power Down Sequences....................................................................................1026.3.1 S0 to S4/S5 Sequence...........................................................................1026.3.2 S4/S5 to S0 (Exit Sleep States) ..............................................................1046.3.3 Enter S0ix ...........................................................................................1056.3.4 Exit S0ix..............................................................................................1056.3.5 Handling Power Failures.........................................................................108

6.4 Reset Behavior ................................................................................................108

7 Thermal Management ............................................................................................1107.1 CPU Thermal Management Registers ..................................................................1107.2 Thermal Sensors..............................................................................................110

7.2.1 DTS Timing..........................................................................................1117.3 Hardware Trips................................................................................................112

7.3.1 Catastrophic Trip (THERMTRIP)...............................................................1127.4 SoC Programmable Trips ..................................................................................112

7.4.1 Aux3 Trip ............................................................................................1127.4.2 Aux2, Aux1, Aux0 Trip...........................................................................112

7.5 Platform Trips .................................................................................................1137.5.1 PROCHOT#..........................................................................................1137.5.2 EXTTS.................................................................................................1137.5.3 sVID ...................................................................................................113

7.6 Dynamic Platform Thermal Framework (DPTF) .....................................................1137.7 Thermal Status................................................................................................114

8 Power Management ...............................................................................................1158.1 Power Management Features.............................................................................1158.2 Power Management States Supported.................................................................115

8.2.1 System States......................................................................................1158.2.2 Interface State Combinations .................................................................1178.2.3 Integrated Graphics Display States .........................................................1188.2.4 Integrated Memory Controller States.......................................................118

8.3 Processor Core Power Management ....................................................................119


8.3.1 Enhanced Intel SpeedStep® Technology .................................................. 1198.3.2 Dynamic Cache Sizing* ......................................................................... 1198.3.3 Low-Power Idle States .......................................................................... 1208.3.4 Processor Core C-States Description ....................................................... 1218.3.5 Package C-States* ............................................................................... 1228.3.6 Graphics, Video and Display Power Management....................................... 124

8.4 Memory Power Management ............................................................................. 1258.4.1 Disabling Unused System Memory Outputs .............................................. 1258.4.2 DRAM Power Management and Initialization ............................................. 126

9 System Memory Controller..................................................................................... 1289.1 Signal Descriptions .......................................................................................... 128

9.1.1 DDR3L-RS Interface Signals .................................................................. 1289.1.2 LPDDR3 Interface Signals ...................................................................... 1319.1.3 ECC Support ........................................................................................ 132

9.2 Features ........................................................................................................ 1339.2.1 System Memory Technology Supported ................................................... 1339.2.2 CO-POP package Configuration............................................................... 134

9.3 Register Map .................................................................................................. 136

10 Graphics, Video and Display................................................................................... 13810.1 Features ........................................................................................................ 13810.2 SoC Graphics Display ....................................................................................... 138

10.2.1 Primary Planes A,B and C ...................................................................... 13910.2.2 Video Sprite Planes A, B, C, D, E and F.................................................... 13910.2.3 Cursors A, B and C ............................................................................... 139

10.3 Display Pipes .................................................................................................. 13910.4 Display Physical Interfaces................................................................................ 139

10.4.1 Digital Display Interfaces....................................................................... 14110.5 References ..................................................................................................... 14810.6 3D Graphics and Video ..................................................................................... 14810.7 Features ........................................................................................................ 149

10.7.1 3D Engine Execution Units ..................................................................... 14910.7.2 3D Pipeline .......................................................................................... 14910.7.3 Video Engine........................................................................................ 150

10.8 VED (Video Encode/Decode) ............................................................................. 15010.8.1 Features ............................................................................................. 150

10.9 Register Map .................................................................................................. 151

11 PCI Express 2.0 ..................................................................................................... 15211.1 Signal Descriptions .......................................................................................... 15211.2 Features ........................................................................................................ 153

11.2.1 Root Port Configurations........................................................................ 15311.2.2 Interrupts and Events ........................................................................... 15411.2.3 Power Management .............................................................................. 155

11.3 References ..................................................................................................... 15511.4 Register Map .................................................................................................. 155

12 MIPI-Camera Serial Interface (CSI) and ISP ......................................................... 15612.1 Signal Descriptions .......................................................................................... 15612.2 Features ........................................................................................................ 157

12.2.1 Imaging Capabilities ............................................................................. 15812.2.2 Simultaneous Acquisition....................................................................... 15812.2.3 Primary Camera Still Image Resolution.................................................... 15912.2.4 Burst Mode Support .............................................................................. 159


12.2.5 Continuous Mode Capture ......................................................................15912.2.6 Secondary Camera Still Image Resolution ................................................15912.2.7 Primary Camera Video Resolution ...........................................................15912.2.8 Secondary Camera Video Resolution........................................................15912.2.9 Bit Depth.............................................................................................159

12.3 Imaging Subsystem Integration.........................................................................16012.3.1 CPU Core.............................................................................................16012.3.2 Imaging Signal Processor (ISP)...............................................................160

12.4 Functional Description ......................................................................................16212.4.1 Preview Mode.......................................................................................16212.4.2 Image Capture .....................................................................................16212.4.3 Video Capture ......................................................................................16212.4.4 ISP Overview .......................................................................................16212.4.5 Memory Management Unit (MMU) ...........................................................163

12.5 MIPI-CSI-2 Receiver.........................................................................................16312.5.1 MIPI-CSI-2 Receiver Features.................................................................165

12.6 Register Map...................................................................................................166

13 SoC Storage ...........................................................................................................16713.1 SoC Storage Overview......................................................................................167

13.1.1 Storage Control Cluster (eMMC, SDIO, SD) ..............................................16713.2 Signal Descriptions ..........................................................................................16713.3 Features.........................................................................................................169

13.3.1 SDIO/SD Interface Features...................................................................16913.3.2 eMMC Interface Features .......................................................................17013.3.3 Storage Interfaces overview...................................................................170

13.4 References......................................................................................................17213.5 Register Map...................................................................................................172

14 USB Controller Interfaces ......................................................................................17314.1 SoC Supports ..................................................................................................17314.2 Signal Descriptions ..........................................................................................17314.3 USB 3.0 xHCI (Extensible Host Controller Interface) .............................................175

14.3.1 Features of USB 3.0 Host.......................................................................17514.3.2 Features of USB HSIC ...........................................................................176

14.4 USB 3.0 xDCI (Extensible Device Controller Interface) ..........................................17614.5 References......................................................................................................176

14.5.1 Host Controller Specifications .................................................................17614.6 Register Map...................................................................................................177

15 Low Power Engine (LPE) for Audio (I2S) ................................................................17815.1 Signal Descriptions ..........................................................................................17815.2 Features.........................................................................................................178

15.2.1 Audio Capabilities .................................................................................18015.3 Clocks ............................................................................................................180

15.3.1 Clock Frequencies .................................................................................18015.3.2 38.4 MHz Clock for LPE..........................................................................18115.3.3 Calibrated Ring Osc (50/100 MHz) Clock for LPE: ......................................18115.3.4 Cache and CCM Clocking........................................................................181

15.4 SSP (I2S) .......................................................................................................18115.4.1 Introduction.........................................................................................18115.4.2 SSP Features .......................................................................................182

16 Intel® Trusted Execution Engine (Intel® TXE)........................................................18316.1 Features.........................................................................................................183


16.1.1 Security Feature................................................................................... 18316.1.2 The TXE interaction with NFC ................................................................. 184

17 Intel® Sensor Hub ................................................................................................. 18617.1 Signal Descriptions .......................................................................................... 18617.2 Features ........................................................................................................ 186

17.2.1 Hardware Overview .............................................................................. 186

18 Serial IO (SIO) Overview....................................................................................... 18818.1 Register Map .................................................................................................. 18818.2 SIO - Serial Peripheral Interface (SPI)................................................................ 189

18.2.1 Signal Descriptions ............................................................................... 18918.2.2 Features ............................................................................................. 189

18.3 SIO - I2C Interface .......................................................................................... 19318.3.1 Signal Descriptions ............................................................................... 19318.3.2 NFC I2C Interface Signals ...................................................................... 19318.3.3 Features ............................................................................................. 194

18.4 NFC I2C ......................................................................................................... 19618.4.1 References .......................................................................................... 19618.4.2 Register Map ....................................................................................... 196

18.5 SIO - High Speed UART.................................................................................... 19718.5.1 Signal Descriptions ............................................................................... 19718.5.2 Features ............................................................................................. 19818.5.3 Use .................................................................................................... 200

18.6 SIO - Pulse Width Modulation (PWM).................................................................. 20218.6.1 Signal Descriptions ............................................................................... 20218.6.2 Features ............................................................................................. 202

19 Platform Controller Unit (PCU) Overview ............................................................... 20519.1 Features ........................................................................................................ 205

19.1.1 BIOS/EFI Top Swap .............................................................................. 20519.2 Register Map .................................................................................................. 20619.3 PCU - Power Management Controller (PMC)......................................................... 207

19.3.1 Signal Descriptions ............................................................................... 20719.3.2 Features ............................................................................................. 20919.3.3 References .......................................................................................... 216

19.4 PCU - Fast Serial Peripheral Interface (SPI)......................................................... 21719.4.1 Signal Descriptions ............................................................................... 21719.4.2 Features ............................................................................................. 218

19.5 PCU - Universal Asynchronous Receiver/Transmitter (UART).................................. 22119.5.1 Signal Descriptions ............................................................................... 22119.5.2 Features ............................................................................................. 22119.5.3 Use .................................................................................................... 22419.5.4 UART Enable/Disable ............................................................................ 22419.5.5 IO Mapped Registers............................................................................. 224

19.6 Register Map .................................................................................................. 22519.7 PCU - Intel Legacy Block (iLB) Overview ............................................................. 226

19.7.1 Signal Descriptions ............................................................................... 22619.7.2 Features ............................................................................................. 22619.7.3 Use .................................................................................................... 228

19.8 PCU - iLB - Low Pin Count (LPC) Bridge .............................................................. 22919.8.1 Signal Descriptions ............................................................................... 22919.8.2 Features ............................................................................................. 23019.8.3 Use .................................................................................................... 235


19.8.4 References...........................................................................................23619.9 PCU - iLB - Real Time Clock (RTC)......................................................................237

19.9.1 Signal Descriptions ...............................................................................23719.9.2 Features..............................................................................................23819.9.3 Interrupts............................................................................................23819.9.4 References...........................................................................................24019.9.5 IO Mapped Registers .............................................................................24019.9.6 Indexed Registers.................................................................................240

19.10 PCU - iLB - 8254 Timers ...................................................................................24219.10.1Signal Descriptions ...............................................................................24219.10.2Features..............................................................................................24219.10.3Use.....................................................................................................243

19.11 PCU - iLB - High Precision Event Timer (HPET) .....................................................24619.11.1Features..............................................................................................24619.11.2References...........................................................................................24819.11.3Memory Mapped Registers .....................................................................248

19.12 PCU - iLB - GPIO..............................................................................................24919.12.1Signal Descriptions ...............................................................................24919.12.2Features..............................................................................................24919.12.3Use.....................................................................................................24919.12.4GPIO Registers .....................................................................................250

19.13 PCU - iLB - Interrupt Decoding and Routing.........................................................25119.13.1Features..............................................................................................251

19.14 PCU - iLB - IO APIC..........................................................................................25319.14.1Features..............................................................................................25319.14.2Use.....................................................................................................25419.14.3References...........................................................................................25419.14.4Memory Mapped Registers .....................................................................25519.14.5Indirect I/O APIC Registers ....................................................................255

19.15 PCU - iLB - 8259 Programmable Interrupt Controllers (PIC) ...................................25619.15.1Features..............................................................................................25619.15.2IO Mapped Registers .............................................................................263

20 Electrical Specifications .........................................................................................26520.1 Absolute Maximum and Minimum Specifications ...................................................26520.2 Thermal Specifications......................................................................................26520.3 Storage Conditions...........................................................................................266

20.3.1 Post Board-Attach.................................................................................26720.4 Voltage and Current Specifications .....................................................................267

20.4.1 VCC and VNN Voltage Specifications........................................................26920.5 Crystal Specifications .......................................................................................26920.6 DC Specifications .............................................................................................270

20.6.1 Display DC Specification ........................................................................27120.6.2 MIPI-Camera Serial Interface (CSI) DC Specification .................................27820.6.3 SDIO DC Specification ...........................................................................27820.6.4 SD Card DC Specification .......................................................................27820.6.5 eMMC 4.51 DC Specification ...................................................................28020.6.6 JTAG DC Specification ...........................................................................28020.6.7 DDR3L-RS Memory Controller DC Specification .........................................28220.6.8 LPDDR3 Memory Controller DC Specification.............................................28220.6.9 USB 2.0 Host DC Specification ................................................................28320.6.10USB 3.0 DC Specification .......................................................................28520.6.11LPC DC Specification .............................................................................286


20.6.12SPI DC Specification ............................................................................. 28720.6.13Power Management/Thermal (PMC) & RTC DC Specification ....................... 28720.6.14SVID DC Specification ........................................................................... 28920.6.15GPIO DC Specification ........................................................................... 29020.6.16SIO - I2C DC Specification ..................................................................... 29020.6.17SIO - UART DC Specification .................................................................. 29120.6.18I2S (Audio) DC Specification .................................................................. 29120.6.19PCI Express DC Specification.................................................................. 291

20.7 AC Specifications............................................................................................. 29220.7.1 Platform Clocks AC Specification............................................................. 29320.7.2 SVID AC Specification ........................................................................... 29320.7.3 DDR3L-RS Memory Controller AC Specification ......................................... 29420.7.4 LPDDR3 Memory Controller AC Specification............................................. 30020.7.5 Display AC Specifications....................................................................... 30620.7.6 MIPI-Camera Serial Interface (CSI) AC Specification ................................. 31320.7.7 SD Card AC Specification....................................................................... 31520.7.8 SDIO AC Specification ........................................................................... 32120.7.9 eMMC 4.51 AC Specification .................................................................. 32420.7.10USB 2.0 Host AC Specification................................................................ 32720.7.11USB 2.0 HSIC AC Specification ............................................................... 33120.7.12USB 3.0 AC Specification ....................................................................... 33220.7.13USB SSIC AC Specification..................................................................... 33320.7.14I2S (Audio) AC Specification................................................................... 33320.7.15PMC - Suspended Clock AC Specification.................................................. 33420.7.16SPI AC Specification.............................................................................. 33520.7.17PCU- Fast SPI AC Specification ............................................................... 33520.7.18PCU - LPC AC Specification .................................................................... 33620.7.19I2C AC Specification.............................................................................. 33720.7.20UART AC Specification........................................................................... 34220.7.21JTAG AC Specification ........................................................................... 34220.7.22PCI Express AC Specification.................................................................. 34420.7.23General AC Timing Diagrams.................................................................. 346

21 Ballout and Ball Map .............................................................................................. 35021.1 Ballout ........................................................................................................... 35021.2 SoC VMS-T3 Pin List Location............................................................................ 35721.3 SoC MSP-T4 Pin List Location ............................................................................ 36521.4 SoC Co-POP Pin List Location ............................................................................ 385

22 Package Information ............................................................................................. 40722.1 SoC Attributes ................................................................................................ 40722.2 Package Diagrams ........................................................................................... 408

FiguresFigure 1SoC Block Diagram.............................................................................................. 24Figure 2RTC Power Well Timing Diagrams ........................................................................ 100Figure 3S4/S5 to S0 (Power Up) Sequence....................................................................... 102Figure 4S0 to S4/S5 (Power Down) Sequence................................................................... 104Figure 5S0 to S0ix Entry and Exit Sequence ..................................................................... 107Figure 6DTS Mode of Operation ...................................................................................... 112Figure 7Platform level thermal Management HW Layout..................................................... 114Figure 8Idle Power Management Breakdown of the Processor Cores..................................... 120Figure 9Co-POP Overview Block Diagram ......................................................................... 135


Figure 10Display Pipe to Port Mapping [MSP-T4] ...............................................................140Figure 11Display Pipe to Port Mapping [VMS-T3] ...............................................................141Figure 12Sub-Display Connection ....................................................................................144Figure 13HDMI Overview ...............................................................................................146Figure 14DisplayPort* Overview......................................................................................147Figure 153D Graphics Block Diagram ...............................................................................148Figure 16PCIe* 2.0 Lane 0 Signal Example.......................................................................153Figure 17Camera Connectivity ........................................................................................157Figure 18Image Processing Components ..........................................................................160Figure 19MIPI-CSI Bus Block Diagram .............................................................................164Figure 20SD Memory Card Bus Topology..........................................................................171Figure 21SDIO Device Bus Topology................................................................................171Figure 22eMMC Interface ...............................................................................................172Figure 23xHCI Port Mapping ...........................................................................................175Figure 24SPI Slave........................................................................................................190Figure 25Clock Phase and Polarity ...................................................................................191Figure 26Data Transfer on the I2C Bus.............................................................................195Figure 27START and STOP Conditions ..............................................................................196Figure 28SIO - I2C Register Map .....................................................................................196Figure 29UART Data Transfer Flow ..................................................................................198Figure 30PWM Signals ...................................................................................................202Figure 31PWM Block Diagram .........................................................................................203Figure 32LPC Interface Diagram......................................................................................230Figure 33Detailed Block Diagram.....................................................................................253Figure 34MSI Address and Data ......................................................................................254Figure 35Definition of Differential Voltage and Differential Voltage Peak-to-Peak....................276Figure 36Definition of Pre-emphasis ................................................................................276Figure 37 eMMC 4.51 DC Bus Signal Level ........................................................................280Figure 38Definition of VHYS in Table 169..........................................................................290Figure 39SVID Timing Diagram.......................................................................................294Figure 40DDR3L-RS DQ Setup/Hold Relationship to/from DQSP/DQSN (Read Operation) ........296Figure 41DDR3L-RS DQ and DM Valid before and after DQSP/DQSN (Write Operation) ...........297Figure 42DDR3L-RS Write Pre-amble Duration ..................................................................297Figure 43DDR3L-RS Write Post-amble Duration.................................................................297Figure 44DDR3L-RS Command Signals Valid before and after CK Rising Edge........................297Figure 45DDR3L-RS CKE Valid before and after CK Rising Edge ...........................................298Figure 46DDR3L-RS CS_N Valid before and after CK Rising Edge .........................................298Figure 47DDR3L-RS ODT Valid before CK Rising Edge ........................................................298Figure 48DDR3L-RS Clock Cycle Time ..............................................................................298Figure 49DDR3L-RS Skew between System Memory Differential Clock Pairs (CKP/CKN)..........299Figure 50DDR3L-RS CK High Time...................................................................................299Figure 51DDR3L-RS CK Low Time ...................................................................................299Figure 52DDR3L-RS DQS Falling Edge Output Access Time to CK Rising Edge........................299Figure 53DDR3L-RS DQS Falling Edge Output Access Time From CK Rising Edge ...................300Figure 54DDR3L-RS CK Rising Edge Output Access Time to the 1st DQS Rising Edge..............300Figure 55LPDDR3 DRAM_DQ Setup/Hold Relationship to/from DRAM_DQSP/DQSN (Read

Operation).............................................................................................................302Figure 56LPDDR3 DRAM_DQ and DRAM_DM Valid before and after DRAM_DQSP/DQSN (Write

Operation).............................................................................................................302Figure 57LPDDR3 Write Pre-amble Duration .....................................................................302Figure 58LPDDR3 Write Post-amble Duration ....................................................................303Figure 59LPDDR3 Command Signals Valid before and after CK Rising Edge ...........................303Figure 60LPDDR3 DRAM_CKE Valid before and after CK Rising Edge ....................................303


Figure 61LPDDR3 DRAM_CS# Valid before and after CK Rising Edge.................................... 304Figure 62LPDDR3 DRAM_ODT Valid before CK Rising Edge ................................................. 304Figure 63LPDDR3 Clock Cycle Time ................................................................................. 304Figure 64LPDDR3 Skew between System Memory Differential Clock Pairs (DRAM_CKP/CKN)... 305Figure 65LPDDR3 CK High Time...................................................................................... 305Figure 66LPDDR3 CK Low Time....................................................................................... 305Figure 67LPDDR3 DRAM_DQS Falling Edge Output Access Time to CK Rising Edge................. 305Figure 68LPDDR3 DRAM_DQS Falling Edge Output Access Time From CK Rising Edge ............ 306Figure 69LPDDR3 CK Rising Edge Output Access Time to the 1st DRAM_DQS Rising Edge....... 306Figure 70Eye Diagram mask for HDMI ............................................................................. 307Figure 71MIPI DSI to Data Clock Timings......................................................................... 312Figure 72Turnaround Procedure...................................................................................... 313Figure 73Input Glitch Rejection of Low-Power Receivers..................................................... 314Figure 74MIPI-CSI Clock Definition.................................................................................. 314Figure 75MIPI-CSI Data to Clock Timing Definitions........................................................... 315Figure 76SD Card Timing Diagram (DDR50) ..................................................................... 317Figure 77SD Card Output Timing Diagram (SDR25)........................................................... 318Figure 78SD Card Input Timing Diagram (SDR12) ............................................................. 318Figure 79SD Card Input Timing Diagram (Default) ............................................................ 319Figure 80SD card Output Timing Diagram (Default)........................................................... 320Figure 81SD Card Input Timing Diagram (High Speed) ...................................................... 321Figure 82SD card Output Timing Diagram (High Speed)..................................................... 321Figure 83SDIO Timing Diagram (DDR50) ......................................................................... 323Figure 84SDIO Output Timing Diagram (SDR25) ............................................................... 323Figure 85SDIO Output Timing Diagram (SDR12) ............................................................... 324Figure 86SDIO Input Timing Diagram (SDR12/25) ............................................................ 324Figure 87eMMC 4.51 Output Timing Diagram (High Speed Mode) ........................................ 326Figure 88eMMC 4.51 DDR Timings .................................................................................. 326Figure 89eMMC 4.51 Input Timing Diagram (High Speed Mode) .......................................... 326Figure 90eMMC 4.51 Clock Signal Timing Diagram (HS200 Mode) ....................................... 327Figure 91eMMC 4.51 Input Timing Diagram (HS200 Mode)................................................. 327Figure 92USB Rise and Fall Times ................................................................................... 330Figure 93USB Full Speed Load........................................................................................ 330Figure 94USB Differential Data Jitter for Low/Full- Speed ................................................... 330Figure 95USB Differential-to-EOP Transition Skew and EOP Width for Low/Full-Speed ............ 331Figure 96Valid Delay from Rising Clock Edge .................................................................... 337Figure 97Float Delay ..................................................................................................... 337Figure 98Setup and Hold Times ...................................................................................... 337Figure 99Definition of Timing for F/S-Mode Devices on I2C Bus ........................................... 339Figure 100Definition of Timing for High Speed-Mode Devices on I2C Bus .............................. 341Figure 101UART Timing Diagram .................................................................................... 342Figure 102JTAG Timing Diagram..................................................................................... 343Figure 103JTAG Valid Delay Timing Waveform .................................................................. 344Figure 104Test Reset (JTAG_TRST#), Async GTL Input and PROCHOT# Timing Waveform...... 344Figure 105PCI Express* Transmitter Eye.......................................................................... 345Figure 106PCI Express* Receiver Eye.............................................................................. 346Figure 107Clock Cycle Time ........................................................................................... 346Figure 108Clock Timing ................................................................................................. 347Figure 109Valid Delay from Rising Clock Edge .................................................................. 347Figure 110Setup and Hold Times .................................................................................... 347Figure 111Float Delay ................................................................................................... 347Figure 112Pulse Width................................................................................................... 348Figure 113Output Enable Delay ...................................................................................... 348


Figure 114Differential Clock Waveform (Measured Single-ended).........................................348Figure 115Differential Clock Waveform (Using Differential Probe for Measurement) ................349Figure 116Ballout - DDR3L-RS (VMS-T3) Top View Part A...................................................351Figure 117Ballout - DDR3L-RS (VMS-T3) Top View Part B...................................................352Figure 118Ballout LPPDR3 (MSP-T4) Top View Part A .........................................................353Figure 119Ballout LPPDR3 (MSP-T4) Top View Part B .........................................................354Figure 120Ballout - Co-POP Part A...................................................................................355Figure 121Ballout - Co-POP Part B...................................................................................356Figure 122Package Mechanical Drawing for VMS-T3 (Part 1) ...............................................409Figure 123Package Mechanical Drawing for VMS-T3 (Part 2) ...............................................410Figure 124Package Mechanical Drawing for MSP-T4 (Part 1) ...............................................411Figure 125Package Mechanical Drawing for MSP-T4 (Part 2) ...............................................412Figure 126Package Mechanical Drawing for Co-POP (Part 1)................................................413Figure 127Package Mechanical Drawing for Co-POP (Part 2)................................................414

TablesTable 1Cherry Trail SoC Packages .....................................................................................22Table 2Package Attributes................................................................................................30Table 3Platform Power Well Definitions ..............................................................................31Table 4Buffer Type Definitions ..........................................................................................31Table 5Default Buffer State Definitions...............................................................................33Table 6DDR3L-RS System Memory Signals .........................................................................34Table 7LPDDR3 System Memory Signals ............................................................................35Table 8USB2.0 Interface Signals .......................................................................................36Table 9USB 2.0 HSIC Interface Signals ..............................................................................37Table 10USB 3.0 Interface Signals ....................................................................................37Table 11USB SSIC Interface Signals ..................................................................................38Table 12Integrated Clock Interface Signals.........................................................................39Table 13Digital Display Interface Signals ............................................................................39Table 14MIPI DSI Interface Signals ...................................................................................40Table 15MIPI CSI Interface Signals ...................................................................................41Table 16PCIe Signals and Clocks .......................................................................................42Table 17LPE Interface Signals...........................................................................................42Table 18Storage Controller (eMMC, SDIO, SD) Interface Signals ...........................................43Table 19High Speed UART Interface Signals .......................................................................44Table 20I2C Interface Signals ...........................................................................................45Table 21NFC I2C Interface Signals.....................................................................................46Table 22PCU- Fast Serial Peripheral Interface (SPI) Signals ..................................................46Table 23PCU - Real Time Clock (RTC) Interface Signals ........................................................47Table 24PCU - LPC Bridge Interface Signals ........................................................................47Table 25PCU - Power Management Controller (PMC) Interface Signals....................................48Table 26Serial Peripheral Interface (SPI) Signals.................................................................49Table 27JTAG Interface Signals.........................................................................................49Table 28Integrated Sensor Hub Interface Signals ................................................................49Table 29PWM Interface signal ...........................................................................................50Table 30Miscellaneous Signals and Clocks ..........................................................................51Table 31Straps ...............................................................................................................51Table 32RCOMP’s List ......................................................................................................53Table 33Multiplexed Functions - MSP T4 SoC ......................................................................54Table 34Multiplexed Functions - VMS T3 SoC ......................................................................67Table 35Multiplexed Functions - CoPOP SoC........................................................................77


Table 36SoC Clock Inputs ................................................................................................ 97Table 37SoC Clock Outputs .............................................................................................. 97Table 38RTC Power Well Timing Parameters ..................................................................... 100Table 39S4/S5 to S0 Cause of Wake Events ..................................................................... 105Table 40S0ix Cause of Wake Events ................................................................................ 106Table 41Types of Resets ................................................................................................ 108Table 42Temperature Reading Based on DTS ................................................................... 110Table 43General Power States for System........................................................................ 115Table 44Cause of Sx wake events ................................................................................... 116Table 45SoC Sx-States to SLP_S*# ................................................................................ 116Table 46ACPI PM State Transition Rules........................................................................... 117Table 47G, S and C State Combinations........................................................................... 117Table 48SoC Graphics Adapter State Control .................................................................... 118Table 49Main Memory States ......................................................................................... 118Table 50D, S and C State Combinations........................................................................... 118Table 51Processor Core/ States Support .......................................................................... 121Table 52Coordination of Core/Module Power States at the Package Level ............................. 123Table 53Memory Channel 0 DDR3L-RS Signals ................................................................. 128Table 54Memory Channel 1 DDR3L-RS Signals ................................................................. 129Table 55Memory Channel 0 LPDDR3 Signals..................................................................... 131Table 56Memory Channel 1 LPDDR3L-RS Signals .............................................................. 132Table 57ECC Signals and Memory Channel 1 Signal Muxing ................................................ 132Table 58ECC Signals ..................................................................................................... 133Table 59Supported LPDDR3 DRAM Devices....................................................................... 135Table 60Supported DDR3L-RS DRAM Devices ................................................................... 136Table 61Supported LPDDR3 Memory Size Per Rank ........................................................... 136Table 62Supported DDR3L-RS Memory Size Per Rank........................................................ 136Table 63 SoC Display Configuration................................................................................. 141Table 64Display Physical Interfaces Signal Names ............................................................. 142Table 65Display Physical Interfaces Signal Names (2 of 2) ................................................. 142Table 66Hardware Accelerated Video Decode/Encode Codec Support ................................... 151Table 67Signals............................................................................................................ 152Table 68Possible Interrupts Generated From Events/Packets .............................................. 154Table 69Interrupt Generated for INT[A-D] Interrupts......................................................... 154Table 70CSI Signals...................................................................................................... 156Table 71GPIO Signals.................................................................................................... 156Table 72Imaging Capabilities.......................................................................................... 158Table 73eMMC Signals................................................................................................... 167Table 74SDIO Signals ................................................................................................... 168Table 75SD Signals....................................................................................................... 168Table 76USB SSIC Signals ............................................................................................. 173Table 77USB Signals ..................................................................................................... 174Table 78HSIC Signals.................................................................................................... 174Table 79LPE Signals ...................................................................................................... 178Table 80Clock Frequencies............................................................................................. 180Table 81ISH Signals...................................................................................................... 186Table 82SPI Interface Signals......................................................................................... 189Table 83SPI Modes ....................................................................................................... 192Table 84I2C[6:0] Signals............................................................................................... 193Table 85NFC I2C Interface Signals .................................................................................. 193Table 86UART 1 Interface Signals ................................................................................... 197Table 87UART 2 Interface Signals ................................................................................... 197Table 88Baud Rates Achievable with Different DLAB Settings.............................................. 199


Table 89Example PWM Output Frequency and Resolution ...................................................203Table 90PMC Signals .....................................................................................................207Table 91Transitions Due to Power Failure .........................................................................209Table 92Transitions Due to Power Button .........................................................................210Table 93System Power Planes ........................................................................................212Table 94Causes of SMI and SCI ......................................................................................214Table 95INIT_N Assertion Causes....................................................................................216Table 96SPI Signals ......................................................................................................217Table 97UART Signals....................................................................................................221Table 98Baud Rate Examples..........................................................................................222Table 99Register Access List...........................................................................................225Table 100iLB Signals .....................................................................................................226Table 101NMI Sources...................................................................................................228Table 102LPC Signals ....................................................................................................229Table 103SERIRQ, Stop Frame Width to Operation Mode Mapping .......................................233Table 104SERIRQ Interrupt Mapping ...............................................................................234Table 105RTC Signals ....................................................................................................237Table 106Register Bits Reset by RTC_RST_N Assertion.......................................................239Table 107I/O Registers Alias Locations.............................................................................240Table 108RTC Indexed Registers.....................................................................................240Table 109Counter Operating Modes .................................................................................243Table 1108254 Interrupt Mapping ...................................................................................247Table 111Interrupt Controller Connections .......................................................................256Table 112Interrupt Status Registers ................................................................................257Table 113Content of Interrupt Vector Byte .......................................................................258Table 114I/O Registers Alias Locations.............................................................................263Table 115Thermal Specifications .....................................................................................266Table 116Storage Conditions Prior to Board Attach ............................................................266Table 117SoC Power Rail DC Specs and Max Current .........................................................267Table 118VCC and VNN DC Voltage Specifications .............................................................269Table 119ILB RTC Crystal Specification ............................................................................269Table 120Integrated Clock Crystal Specification ................................................................270Table 121Display Port DC specification.............................................................................271Table 122HDMI DC specification......................................................................................272Table 123Embedded Display Port DC Specification.............................................................272Table 124DDI AUX Channel DC Specification.....................................................................273Table 125Embedded Display Port AUX Channel DC Specification ..........................................274Table 126DDC Signal DC Specification (DCC_DATA, DDC_CLK) ...........................................275Table 127DDC Misc Signal DC Specification (HPD, BKLTCTL, VDDEN, BKLTEN) ......................275Table 128MIPI DSI DC Specification ................................................................................277Table 129MIPI HS-RX/MIPI LP-RX Minimum, Nominal, and Maximum Voltage Parameters .......278Table 130SDIO DC Specification......................................................................................278Table 131SD Card DC Specification .................................................................................279Table 132 eMMC 4.51 DC Electrical Specifications..............................................................280Table 133JTAG Signal Group DC Specification (JTAG_TCK, JTAG_TMS, JTAG_TDI, JTAG_TRST_N).

280Table 134JTAG Signal Group DC Specification (JTAG_TDO) .................................................281Table 135JTAG Signal Group DC Specification (JTAG_PRDY#, JTAG_PREQ#).........................281Table 136DDR3L-RS Signal Group DC Specifications ..........................................................282Table 137LPDDR3 Signal Group DC Specifications..............................................................282Table 138LPC 1.8V Signal Group DC Specification..............................................................286Table 139LPC 3.3V Signal Group DC Specification..............................................................286Table 140SPI Signal Group DC Specification .....................................................................287


Table 141Power Management 1.8V Suspend Well Signal Group DC Specification.................... 287Table 142PMC_RSTBTN# 1.8V Core Well Signal Group DC Specification ............................... 288Table 143Power Management & RTC Well Signal Group DC Specification .............................. 288Table 144RTC Well DC Specification ................................................................................ 288Table 145PROCHOT# Signal Group DC Specification .......................................................... 289Table 146SVID Signal Group DC Specification (SVID_DATA, SVID_CLK, SVID_ALERT_N) ....... 289Table 147GPIO 1.8V Core Well Signal Group DC Specification ............................................. 290Table 148I2C Signal Electrical Specifications..................................................................... 290Table 149PCI Express DC Receive Signal Characteristics .................................................... 291Table 150PCI Express DC Transmit Characteristics ............................................................ 291Table 151PCI Express DC Clock Request Input Signal Characteristics ................................... 291Table 15219.2 MHz Platform Clock AC Specification........................................................... 293Table 153SVID AC Specification...................................................................................... 293Table 154DDR3L-RS Interface Timing Specification ........................................................... 294Table 155LPDDR3 Interface Timing Specification............................................................... 300Table 156HDMI AC specification...................................................................................... 306Table 157Display Port Transmitter AC specification............................................................ 307Table 158Embedded Display Port AC specification ............................................................. 309Table 159Display Port AUX Channel AC Specification ......................................................... 310Table 160MIPI DSI AC Characteristics ............................................................................. 310Table 161MIPI-CSI Receiver Characteristics ..................................................................... 313Table 162MIPI-CSI Clock Signal Specification ................................................................... 314Table 163MIPI CSI Data Clock Timing Specifications.......................................................... 314Table 164SD Card AC Specification ................................................................................. 315Table 165SD Card Default Speed AC Specification ............................................................. 318Table 166SD Card High Speed AC Specification................................................................. 320Table 167SDIO AC Specification ..................................................................................... 321Table 168eMMC 4.51 AC Characteristics .......................................................................... 324Table 169USB 2.0 AC specification (HIGH SPEED) ............................................................. 327Table 170USB 2.0 AC specification (FULL SPEED).............................................................. 328Table 171USB 2.0 AC specification (LOW SPEED) .............................................................. 328Table 172USB 2.0 HSIC AC Specification.......................................................................... 331Table 173USB 3.0 Signals AC Specification....................................................................... 332Table 174USB SSIC Signals AC Specification .................................................................... 333Table 175I2S Master Mode AC Specifications .................................................................... 333Table 176I2S Slave Mode AC Specifications ...................................................................... 334Table 177SUS Clock Timings .......................................................................................... 334Table 178SPI AC Specifications....................................................................................... 335Table 179Fast SPI AC Specifications ................................................................................ 335Table 180LPC AC Specifications ...................................................................................... 336Table 181I2C Fast/Standard Mode AC Specifications .......................................................... 338Table 182AC Specification for High Speed Mode I2C—Bus Devices ....................................... 340Table 183UART AC Specification ..................................................................................... 342Table 184JTAG AC Specification...................................................................................... 342Table 185Boundary Scan AC Specification ........................................................................ 343Table 186PCI Express Interface Timings .......................................................................... 344Table 187SoC Attributes ................................................................................................ 407


Revision History

Document Number

Revision Number Description Revision Date

33012 0.5 • Initial release September 2013

539071 0.6

• This document is de-classified from Intel Restricted Secret to Intel Confidential. Hence, there is a change in the Document Number.

• Aligned to SoC Pinlist Rev 0p6• Changed the GPIO table to accommodate more details and

aligned the GPIO table with Pinlist rev 0p6• Added SoC Pinlist Location and Ballout DDR3L and LPDDR3

October 2013

539071 0.7 • Updated SoC Pinlist Location and Ballout DDR3L and LPDDR3 and Chapter 20‚ “Electrical Specifications” November 2013

539071 0.8

• Added SKU table in Chapter 1‚ “Introduction”. - Added Feature List Table 1, “CHT-T SoC Packages” for MSP

T4 and VMS T3 - Added Table , “”

• Updated Table 3, “Platform Power Well Definitions”• Added Chapter 11‚ “PCI Express 2.0” - Features, Pinlist and

Electrical Specifications• Added Figure 9, “Display Pipe to Port Mapping [MSP-T4]” and

Figure 10, “Display Pipe to Port Mapping [VMS-T3]” in Chapter 12, “Graphics, Video and Display”.

• Updated Data rate in Table 59, “SoC Display Configuration”• Added Chapter 17‚ “Intel® Sensor Hub”.• Chapter 20‚ “Electrical Specifications”

- Updated SDIO AC Specification - Updated SD Card AC Specification - Updated eMMC 4.51 AC Specification - Added I2S AC Specifications - Added SVID AC Specifications - Added SPI AC Specifications - Added SPINOR AC Specifications - Added PMC AC Specifications - Added LPC AC Specifications - Added I2C AC Specifications - Added UART AC Specifications

• Added “SoC MSP-T4 Pin List Location” and “SoC VMS-T3 Pin List Location” for MSP T4 and VMS T3 Sku.

• Updated Chapter 19.12‚ “PCU - iLB - GPIO” and added Table 111, “GPIO Signals”

• Added Table 187, “SoC Attributes”

December 2013

539071 0.9

• Added Cherry Trail Co-POP details• Updated

- Chapter 1‚ “Introduction” - Chapter 2‚ “Physical Interfaces” - Chapter 9‚ “System Memory Controller” - Chapter 14‚ “USB Controller Interfaces”Section 18.2‚ “SIO -

Serial Peripheral Interface (SPI)”Section 19.4‚ “PCU - Fast Serial Peripheral Interface (SPI)”

- Chapter 20‚ “Electrical Specifications”• Added Figure 118, Figure 119 and • Added Figure 124, Figure 125, Figure 126,and Figure 127

January 2014


539071 1.0

• Updated - Chapter 2‚ “Physical Interfaces” - Chapter 12, “Graphics, Video and Display” - Chapter 17‚ “Intel® Sensor Hub” - Section 18.2‚ “SIO - Serial Peripheral Interface

(SPI)”Section 19.4‚ “PCU - Fast Serial Peripheral Interface (SPI)”Section 19.8‚ “PCU - iLB - Low Pin Count (LPC) Bridge”Chapter 20‚ “Electrical Specifications”

• Changed LPE_I2S_CLK to 9.6 MHz in Clocking Chapter• Changed eMMC bandwidth to 400 MByte/sec in Storage Chapter• Updated the Reset behavior: Table 41, “Types of Resets”• Updated Table 42 in Chapter 7‚ “Thermal Management”• Added Figure 6 in Chapter 7‚ “Thermal Management”• Updated Chapter 22‚ “Ballout and Ball Map”• Updated Chapter 22.2‚ “Package Diagrams”• Added Cherry Trail EDS Volume 2: CDI No. 543698 with following

registers - SoC Transaction Router - System Memory Controller - Graphics, Video and Display - MIPI-Camera Serial Interface (CSI) and ISP - PCI Express* 2.0 - SoC Storage - USB Controller Interfaces - Serial IO (SIO) - Platform Controller Unit

March 2014

Document Number



539071 1.2

• Chapter 1‚ “Introduction” - In Table 1, updated "eDP Data Rate" field of MSP-T4 port to

21.6 Gbps. - Updated Table 1 with POR requirements. - Update the USB feature set to match Table 1. - Added note for 4th USB 3.0 port support. - Updated the Package attributes in Table 2. - Added note for Co-POP package under Table 2.

• Chapter 2‚ “Physical Interfaces” - Added SoC GPIO RCOMP table. - Added PWM signal description. - Updated the Package information. - Updated Table 33, “Multiplexed Functions - MSP T4 SoC” - Added Table 34, “Multiplexed Functions - VMS T3 SoC” and

Table 35, “Multiplexed Functions - CoPOP SoC”• Chapter 5‚ “Integrated Clock”

- Removed UART clock details from Table 36, “SoC Clock Inputs”.

- Changed the I2C CLK support - Updated Signal names in the SoC Clock output table

• Chapter 7‚ “Thermal Management” - Edited Figure 6

• Chapter 10‚ “Graphics, Video and Display” - Changed Embedded DisplayPort Standard Version 1.4b to

"v1.3 and v1.4." in Table 63 - Changed to "eDP1.3/eDP1.4" in Table 63.

• Chapter 11‚ “PCI Express 2.0” - Updated the Number of ports. - Updated Figure 16 with lane 1.

• Chapter 12‚ “MIPI-Camera Serial Interface (CSI) and ISP” - Added note in under signal description of MIPI CSI.

• Chapter 13‚ “SoC Storage” - Added MMC1_RCLK data in Signal Description and MMC

block diagram Figure 22. - Added HS400 mode support - Updated the data rate for Parallel data line operation - Added SD3_WP signal to the Table 75.

• Chapter 14‚ “USB Controller Interfaces” - Added IVCAM support. - Changed the number of data lanes from [0:4] to [0:3] for

USB2 in Signal Description. - Changed the block diagram to appropriate USB ports in

Figure 23. - Added xDCI support.

• Updated Chapter 15‚ “Low Power Engine (LPE) for Audio (I2S)”• Chapter 16‚ “Intel® Trusted Execution Engine (Intel® TXE)”

- Added feature of TXE interaction with NFC• Updated Chapter 17‚ “Intel® Sensor Hub” to match POR

June 2014

Document Number



539071 1.2

• Chapter 18‚ “Serial IO (SIO) Overview” - Updated Section 18.2 - Updated to match POR - Updated Section 18.3 - Added section NFC - Added NFC I2C signal description - Added Fast mode plus support for I2C interface

• Chapter 19‚ “Platform Controller Unit (PCU) Overview” - Removed 19.1.1 BIOS/EFI Boot Strap section

• Section 19.3‚ “PCU - Power Management Controller (PMC)” - Removed 25 MHz Clock Support in Platform Clock Support

section.• Section 19.5‚ “PCU - Universal Asynchronous Receiver/

Transmitter (UART)” - Changed Signal names in chapter - Changed IRQ3 to IRQ4 under legacy interrupt

• Section 19.7‚ “PCU - Intel Legacy Block (iLB) Overview” - Changed the S0iX support statement

• Section 19.12‚ “PCU - iLB - GPIO” - Added GPIO controller feature section in GPIO. - Added Section 19.12.4.1 (3.3V versus 1.8V Modes) under

GPIO registers. - Removed the GPIO signal table as it was duplicate data

already exist in Section 2.25• Chapter 20‚ “Electrical Specifications”

- Added Tj max/Min and SDP Values in Table 115. - Updated table 117 with correct signal names. - Updated table 118 with VCC/VNN/VGG tolerance values.

• In Section 20.7.2‚ “SVID AC Specification” - Changed Tsu for Data to Min -> 7.5ns - Changed Tco to Min -> -2.0ns

• In Section 20.7.4‚ “LPDDR3 Memory Controller AC Specification” - Changed TCTL,TDVB+TVDA,TCMD values.

• In Section 20.7.5‚ “Display AC Specifications” - In Table 159 - Changed FAux transaction Frequency to 1 MHz - In Table 157 - Changed the "f_HBR2" field for the “Type” column from 5.1

to 5.4. - Removed Undershoot specification

• In Section 20.7.8‚ “SDIO AC Specification” - Removed Rise/Fall time for 3.3 V operation

• In Section 20.7.9‚ “eMMC 4.51 AC Specification”

- Changed CLK Cycle Time (HS200 Mode) to 5 ns - Changed Data/CMD Clock to Output Delay (BC Mode) - Added eMMC_RST# related AC spec

• Added Section 20.7.11‚ “USB 2.0 HSIC AC Specification”• Added Section 20.7.13‚ “USB SSIC AC Specification”• In Section 20.7.16‚ “SPI AC Specification”

- Changed min/max values Tco of SPI_MOSI - Changed Setup and hold time for CS - Changed setup time for MISO to 10.8ns

• In Section 20.7.17‚ “PCU- Fast SPI AC Specification” - Changed Setup and hold time to 8.8 and 0ns - Changed Tco to 5.2ns max

June 2014

Document Number



§

• In Section 20.7.18‚ “PCU - LPC AC Specification” - Changed Tco --> 12ns max - Changed setup time to 16ns min - Added Trsie/fall time for 3.3V operation - Added 2 more notes for this section

• In Section 20.7.19‚ “I2C AC Specification”

- Changed the Cb (Cap Load) for all modes in Table 185. - Changed the Cb, tLOW,tHIGH,tHD:DAT, tr CL, tf CL, tf CL1, tr DA, tf DA, Values in Table 186. ”

• In Section 20.7.20‚ “UART AC Specification” - Changed Rise and fall time -> 0.2 to 1.5ns - Added Sample clk frequency, 15 Mhz

• In Section 20.7.14‚ “I2S (Audio) AC Specification” - Changed CLK, Tco values for master Mode. - Changed Hold for DATAIN, Setup from FRM, Tco, Rise/Fall

time for Slave mode• In Section 20.7.5.5‚ “MIPI Display Serial Interface (DSI) AC

Specification” - Added Note: DSI LP TX slew rates in EDS spec are not

measurable with 0 and 5pf load due capacitance of PCB traces.This issue is also mentioned in MIPI Dphy CTS.

• Chapter 21‚ “Ballout and Ball Map” - Updated Figure 116 to Figure 121 - Updated Section 21.2, Section 21.3 and Section 21.4

• Chapter 22‚ “Package Information” - Updated figures in Section 22.2

Revision Number Descriptions

Revision Associated Life Cycle Milestone Release Information

0.5 Design Win Phase Required Release

0.6–0.7 When Needed Project Dependent

0.7 Simulations Complete Required Release


1.0 First Silicon Samples Required Release


1.5 Qualification Silicon Samples Project Dependent


NDA - 2.0Public - XXXXXX-001 First SKU Launch

Required Release Product Launch

2.1 and up When Needed Project Dependent

Document Number



Introduction

1 Introduction

The Cherry Trail SoC is the Intel Architecture (IA) SoC that integrates the next generation Intel® processor core, Graphics, Memory Controller, and I/O interfaces into a single system-on-chip solution.

The figures below shows the system level block diagram of the SoC. Refer to the subsequent chapters for detailed information on the functionality of the different interface blocks.

Note: This document is preliminary. Statements may be missing or subject to change.

The Table 1, “Cherry Trail SoC Packages” lists the different features supported by four Cherry Trail SoC packages.

Introduction


1.1 Cherry Trail SoC PackagesTable 1. Cherry Trail SoC Packages

Interface Category MSP-T4 VMS-T3 Co-POP MSP-T4 Refresh

CPUNo. of Cores 4 4 4 4

Burst Speed 2.56 GHz 2 GHz[4] 2.56 GHz 2.56 GHz

Package

Type 17x1

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