Characterization for Novel Non-traditional CMOS

Inverter Composed of a Junctionless NMOSFET

and a Gated N+-N--P Transistor Kuan-Yu Lu, Jyi-Tsong Lin, Hsuan-Hsu Chen, Yi-Chuen Eng, Chih-Hsuan Tai, Cheng-Hsin Chen,

Yu-Che Chang, and Yi-Hsuan Fan

Dept. of Electrical Engineering, National Sun Vat-Sen University 70 Lien-Hai Rd., Kaohsiung 80424, Taiwan, R.O.C.

E-mail: m983010026@student.nsysu.edu.tw

Abstract-We present a non-traditional CMOS inverter composed a junctionless (JL) NMOSFET and an N+-N--P transistor which with simple process and high integration density in this paper. In the non-traditional CMOS inverter the JL NMOSFET serves as driver and the �-N--P transistor serves as load, respectively. Based on the measurement date of the N+-N--P transistor published, we draw the load line of the non-traditional CMOS inverter and we found out that the �­N--P transistor can be used in the COMS circuit to advance the issues of the conventional CMOS today. Besides, the area reduced more than 46.1 % are also be achieved.

Keywords-CMOS, Inverter, Junctionless.

I. INTRODUCTION As the semiconductor technology developed continues,

the complementary metal-oxide semiconductor (CMOS) logical devices have been used in the digital circuits as well as the very-large-scale integration (VLSI) generally, because of its low static power consumption and good noise margin. Unfortunately, the complicated process, high fabrication cost, and the non-matched mobility are the serious issues of the silicon-based CMOS logical devices. Also, when the device dimensions are scaled-down, the wider width of PMOSFETs appears to be difficult to achieve the high integration density. A number of CMOS studies have been reported to ease the issues mentioned above, including the device fabricated on silicon-on­insulator (SOl) substrate [1], and on germanium-on­insulator (GeOl) substrate [2], on III-V materials [3] [4], or use of stress engineering and three-dimensional (3-D) integration technology [5]. However, the width compensation of PMOSFETs and its complicated processes still exist.

In 1980s, Yasuhisa Omura reported the lateral unidirectional bipolar-type insulated-gate transistor (LUBISTOR) [6], [7] behaving as a gated P-I-N diode. Moreover, P-I-N tunnel field effect transistors (TFETs) have been interested in their low power consumption for future CMOS scaling to date. This is because the steep subthreshold swing (S.S.) and high ION/loFF ratio [8], [9] of

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TFETs benefit for the scaling of power supply voltage. Recently, JL MOSFETs [10] have also been greatly attentive. No junction makes them easier to manufacture due to the absence of source/drain (SID) implantations. Besides, when the device dimensions continue to be scaled-down, the short-channel effects (SCEs) and the drain-induced barrier lowering (DIBL) can be reduced significantly [11] in JL MOSFETs.

In this study, as shown in Fig. 1, we demonstrate a gated N+-N--P transistor which is connected with a JL NMOSFET to form a CMOS-type inverter. Also, that a non-traditional logical device, simple process, high integration density can probably improve problems of the traditional CMOS is also studied.

Fig. I. The schematic view of a non-traditional CMOS being composed ofa JL NMOSFET and an N+-N--P transistor

II. DEVICE DESIGN AND FABRICATION The new method for drawing the load line of a CMOS­

type inverter was proposed in [12]. The design theory of our proposed device is shown in Fig. 2. When fin = 0 V, the Ql is "OFF", and the Q2 is "ON" because the gate controls the energy band. Comparatively, when fin = 1 V, the Ql is "ON", and the Q2 is "OFF" due to the higher barrier between channel and drain regions.

The FLOOPS-ISE was used for simulations. Fig. 3 shows the main process flows of our proposed device. First, photolithography process, lightly phosphorous implantation and annealing for channel region were performed. Then, the photolithography, N+ implantation and annealing for driver channel were carried out. Next, poly-Si deposition, boron implantation, annealing, photolithography and etching for gate formation were performed, respectively. After gate formation, the sidewall spacers were formed, and lithography, p+ implantation as well as annealing for the drain of load were carried out. Finally, a standard BEOL process was used to finish the remaining processes.

Fig. 2. The operation theory of a non-traditional CMOS inverter.

III. DISCUSSION

The measurement date of the N+-N-P transistor published [7] as shown in the inset of Fig. 4, and the calculated current (using the model in [7]) of the N+-N--P transistor is shown in fig. 4. It can be observed that the calculated current by the model in [7] fits well, which assists our evaluation of the non-traditional CMOS inverter. Fig. 5 shows the load line of the non-traditional CMOS inverter which uses the new method for drawing the load line proposed in [12]. The transfer curve and the transient current of the non-traditional CMOS inverter are exhibited in Fig. 6. It can be seen that the transient current is small which probably benefit the low power applications if the device is optimized. That the noise margin high (NMH) is 0.45 V and the noise margin low (NML) is 0.15 V of the non-traditional CMOS inverter is initially obtained although we have not optimized it yet.

We also compare the layout area of the conventional and non-traditional CMOS inverters as shown in Fig. 7. The area of the non-traditional CMOS inverter reduces almost 46.1 % that is advantageous for high integration density.

IV. SUMMARY

A gated N+-N--P transistor which comprises a JL NMOSFET driver and an N+-N--P transistor load to form a novel CMOS-type inverter has been presented. According to the measurement and numerical results, this non-traditional CMOS exhibits good IV and transfer behaviors. Besides, the non-traditional CMOS inverter reduces more than 46.1% area in contrast to the traditional CMOS inverter. Thus, it is believed that the non-traditional CMOS inverter can become

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a high potential candidate for high integration density applications.

Phosphorous implantation

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formation

lithography

P+

implantation

RTA

TEOS ILD

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patterning

Metal

deposition

M 1 patterning

Sintering

Fig.3. The main process flows of a non-traditional CMOS inverter.

Fig.4. The calculated current of the N+-N--P transistor and the inset is measurement data of the N+-N--P transistor published in [7].

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Fig.6. The transfer characteristics of the non-traditional CMOS inverter.

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Fig.7. Comparison of the area penalty of (a) a traditional CMOS inverter and (b) a non-traditional CMOS inverter.

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