Chapter 2

Power Electronic Devices

Control of Energy Consumption

Load Switching

Ideal Switch

Bi-polar Transistor (BJT)

Base CharacteristicsCollector CharacteristicsLinear RegionCharacteristics of Bi-polar Transistor

At point (1)VCE is very smallAt point (2)IC is very smallClosedswitchOpenswitch

ExampleA transistor has a current gain of 200 in the linear region and 10 in the saturation region. Calculate the base current when the collector current is equal to 10 A assuming that the transistor operates in the linear region. Repeat the calculation for the saturation region

SolutionIn the linear regionIn the saturation region

Main Features of BJTCurrent controlled device Base current must be present during the closing periodHigh base losses Low current gain in the saturation region Can operate at high frequencies

Field Effect Transistor (FET)

Main Features of FETVoltage controlled device Low gate losses

Thyristors (Four Layer Diode)

N

P

P

P

P

P

Anode (A)

Cathode (K)

Anode (A)

Anode (A)

Cathode (K)

Cathode (K)

IA

IA

IA

Ic1

Ic2

Q1

Q1

Q2

Q2

VBO

IA

VRB

Ih

VAK

Thyristors [Silicon Controlled Rectifier (SCR)]AK

Closing Conditions of SCRPositive anode to cathode voltage (VAK)Maximum triggering pulse is applied (Ig)Closing angle is a

Opening Conditions of SCRAnode current is below the holding value (Ih)AKOpening angle is b

Other Power Devices (Darlington Transistor)

I

b1

I

b2

I

e2

(B)

(C)

(E)

Other Power Devices Insulated Gate Bipolar Transistor (IGBT)

VGS

(D)

I

b

I

e

(G)

(C)

(E)

IC

VCE

VG2

VG3

VG1 > VG2 > VG3

IC

VG

C

IC

E

G

Ratings of Power Electronic DevicesSteady State Circuit ratings: The current and voltage of the circuit should always be less than the device ratings.

Ratings of Power Electronic DevicesJunction temperature: Losses inside solid-state devices are due to impurities of their material as well as the operating conditions of their circuits.

Ratings of Power Electronic DevicesDuring the conduction period, the voltage drop across the solid-state device is about one volt. This voltage drop multiplied by the current inside the device produces losses. When the device is in the blocking mode (open), a small amount of leakage current flows inside the device which also produces losses. The gate circuits of the SCRs and FETs, and the base circuits of the transistors, produce losses due to their triggering signals. Every time the solid state device is turned on or off, switching losses are produced. These losses are usually higher for faster devices, and for devices operating in high frequency modes.

Ratings of Power Electronic DevicesSurge current: It is the absolute maximum of the non-repetitive impulse current

Ratings of Power Electronic DevicesSwitching time: Turn-on time is the interval between applying the triggering signal and the turn-on of the device. The turn-off time is the interval from the on-state to the off-state. The larger the switching time the smaller is the operating frequency of the circuit.

Ratings of Power Electronic DevicesCritical rate of rise of current (or maximum di/dt): A solid-state device can be damaged if the di/dt of the circuit exceeds the maximum allowable value of the device. di/dt damage can occur even if the current is below the surge limit of the device. To protect the device from this damage, a snubbing circuit for di/dt must be used.

Ratings of Power Electronic DevicesCritical rate of rise of voltage (or maximum dv/dt): When dv/dt across a device exceeds its allowable limit, the device is forced to close. This is a form of false triggering. It may lead to excessive current or excessive di/dt. To protect the device against excessive dv/dt, a snubbing circuit for dv/dt must be used.

di/dt and dv/dt Protection M. A. El-Sharkawi, University of Washington *

M. A. El-Sharkawi, University of Washington

Closing SwitchLoad impedance Load V L s R C s s I 1 + - I2 M. A. El-Sharkawi, University of Washington *

M. A. El-Sharkawi, University of Washington

Closing Switch: Analysis of I1 M. A. El-Sharkawi, University of Washington *LL, RL, CL

M. A. El-Sharkawi, University of Washington

Closing Switch: Analysis of I1 M. A. El-Sharkawi, University of Washington *

M. A. El-Sharkawi, University of Washington

Snubbing Circuit: LsWorst Scenario for Maximum di/dt: When the load capacitor is not charged at t=0 M. A. El-Sharkawi, University of Washington *

M. A. El-Sharkawi, University of Washington

Closing Switch: Analysis of I2The fully charged cap discharges after the switch is closedLoadVLsRCssI2+- M. A. El-Sharkawi, University of Washington *

M. A. El-Sharkawi, University of Washington

Closing Switch: Analysis of I2LoadVLsRCssI2+-At t = 0 M. A. El-Sharkawi, University of Washington *

M. A. El-Sharkawi, University of Washington

Opened SwitchLoad impedance Load V L s R C s s I 3 + - M. A. El-Sharkawi, University of Washington *

M. A. El-Sharkawi, University of Washington

Opened SwitchLoadVLsRCss+-I 3 M. A. El-Sharkawi, University of Washington *

M. A. El-Sharkawi, University of Washington

Opened SwitchAssume the caps are initially discharged M. A. El-Sharkawi, University of Washington *LoadVLsRCss+-I 3

M. A. El-Sharkawi, University of Washington

Selection of the Snubbing Circuit ParametersStep 1: Compute snubbing inductanceStep 2: Compute snubbing ResistanceStep 3: Compute snubbing Capacitance M. A. El-Sharkawi, University of Washington *

M. A. El-Sharkawi, University of Washington

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