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Transcript of Chapter06 CPU Design
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Specifying a CPU
� Fetch cycle± Fetch an instruction from memory, then go to the
decode cycle.� Decode cycle
± Decode the instruction-that is, determine whichinstruction has been fetched, then go to the
execute cycle fit that instruction.
� Execute cycle± Execute the instruction, then go to fetch the next
instruction.
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Generic CPU state diagram
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Specifications for a very simple CPU
� To illustrate the CPU design process,
consider this small and somewhat impractical
CPU. It can access 64 bytes of memory, eachbyte being 8 bits wide.
� The CPU does this by outputting 6-bit
address on its output pins A[5..0] and reading
in the 8-bit value from memory on its inputsD[7..0].
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Specifications for a very simple CPU
� AC (same as in SAP-1)± An 8-bit accumulator labeled AC
� AR (MAR in SAP-1)± A 6-bit address register
� PC (same as in SAP-1)± A 6-bit program counter
� DR (B in SAP-1 & MBR in SAP-2)± A 8-bit data register
� IR (same as in SAP-1)± A 2-bit instruction register
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Instruction set for the very simple CPU
Instruction Instruction Code Operation
ADD 00AAAAAA ACnAC+M[AAAAAA]
AND 01AAAAAA ACnAC^M[AAAAAA]
JMP 10AAAAAA GOTO AAAAAA
INC 11AAAAAA ACnAC+1
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Fetching Instructions From Memory
� FETCH1� ARnPC
� FETCH 2� DRnM, PCnPC+1
� FETCH 3� IRnDR[7..6], ARnDR[5..0]
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Fetch cycle for the very simple CPU
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Fetch and decode cycles for the very
simple CPU
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Executing Instruction
� JMP
± JMP1: PCn DR[5..0]
� INC± INC1: ACn AC + 1
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Complete state diagram for the very
simple CPU
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Establishing Required Data Paths
� The operations associated with each state for
this CPU are
� FETCH1: ARnPC
� FETCH 2: DRnM, PCnPC+1
� FETCH 3: IRnDR[7..6], ARnDR[5..0]
� ADD1: DRnM
� ADD2: ACnAC+DR
� JMP1: PCn DR[5..0]
� INC1: ACn AC + 1
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Establishing Required Data Paths
� To design the data paths, we can take one of
two approaches.
± Direct path� Between each pair of components that transfer data.
± Bus
� Within the CPU and route data between components via
the bus.
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Preliminary register section for the very
simple CPU
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Final register section for the very simple
CPU
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Design a very simple ALU
� The ALU for this CPU performs only twofunctions
± ADDs its two inputs or � Using a standard 8-bit parallel adder
± Logically ANDs its two inputs� Using eight 2-input AND gates
� The outputs of the adder and AND gates areinput to an 8-bit 2 to1 multiplexer.
� The control input of the MUX is called S (for select)
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A very simple ALU
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Designing The Control Unit Using
Hardwired Control
� There are two primary methodologies for
designing control.
± Hardwired control� Uses sequential and combinatorial logic to generate
control signals
± Microsequenced control
� Uses a lookup memory to output the control signals
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Designing The Control Unit Using
Hardwired Control
� The simplest control unit has threecomponents
± Counter � Contains the current state
± Decoder � Takes the current states and generates individual signals
for each state
± Logic� Take the individual state signals and generate the control
signals for each component, as well as the signals tocontrol the counter
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Generic hardwired control unit
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Generic hardwired control unit
� For this CPU, there are a total of 9 states.
� 4-bit counter needed.
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Control signals for Counter
� INC
± Asserted when the control unit is traversing sequential states,
during FETCH1, FETCH2, ADD1, and AND1
� CLR
± Asserted at the end of each execute cycle to return to the
fetch cycle; this happens during ADD2, AND2, JMP1, and
INC1
� LD± Asserted at the end of fetch cycle during state FETCH3
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Hardwired control unit for the Very Simple
CPU
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Control signal generation for the Very
Simple CPU
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Design Verification
� 0: ADD 4
� 1: AND 5
� 2: INC
� 3: JMP 0
� 4: 27H
� 5: 39H
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Execution Trace
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Design And Implementation Of A
Relatively Simple CPU
� Specifications for relatively simple CPU
� Fetching and decoding instruction
� Executing instruction
� Establishing data paths
� Design of a relatively simple ALU
� Designing the control unit using hardwiredcontrol
� Design verification
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Design And Implementation Of A
Relatively Simple CPU
� 16-bit address register, AR
� 16-bit program counter, PC
� 8-bit data register, DR
� 8-bit instruction register, IR
� 8-bit temporary register, TR � 64K bytes of memory (16-bit address)
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Specifications for relatively simple CPU
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Fetching and decoding instruction
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Instruction format� 25 : JUMP 1234H
� The instruction would be stored in memory as
25 : 0000 0101 (JUMP) ± OP Code
26 : 0011 0100 (34H) ± low-order 8 bits of address
27 : 0001 0010 (12H) ± high-order 8 bits of address
� Save memory !
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� NOP± NOP1 : (No operation)
� LDAC± LDAC1 : DRnM, PCnPC+1, ARnAR+1 (high-order half
address)
± LDAC2 : TRnDR, DRnM, PCnPC+1 (TR ± low-order)
± LDAC3 : ARnDR, TR (DR ± high-order)
± LDAC4 : DRnM
± LDAC5 : ACnDR
�FETCH1: ARnPC
�FETCH 2: DRnM, PCnPC+1
�FETCH 3: IRnDR, ARnPC (low-order half address)
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Executing instruction
� STAC
± STAC1 : DRnM, PCnPC+1, ARnAR+1
± STAC2 : TRnDR, DRnM, PCnPC+1± STAC3 : ARnDR, TR
± STAC4 : DRnAC
± STAC5 : MnDR
� MVAC and MOVR
± MVAC1 : RnAC
± MOVR1 : ACnR
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� JMPZ and JPNZ± JMPZY1 : DRnM, ARnAR+1
± JMPZY2 : TRnDR, DRnM
± JMPZY3 : PCnDR, TR
± JMPZN1 : PCnPC+1
± JMPZN2 : PCnPC+1
± JPNZY1 : DRnM, ARnAR+1± JPNZY2 : TRnDR, DRnM
± JPNZY3 : PCnDR, TR
± JPNZN1 : PCnPC+1
± JPNZN2 : PCnPC+1
�FETCH1: ARnPC
�FETCH 2: DRnM, PCnPC+1
�FETCH 3: IRnDR, ARnPC (low-order half address)
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Executing instruction
� The remaining instruction
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Complete state diagram for the Relatively
Simple CPU
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Establishing data paths
� Refer to page 242
� AR and PC must be able to perform a parallel
load and increment� DR, IR, R, and TR must be able to load data
in parallel
� AC will require a lot of work, as will Z
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Generic bidirectional data pin
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Final register section for the Relatively
Simple CPU
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Design of a relatively simple ALU
�� All transfers that modify the contents of ACAll transfers that modify the contents of AC
� Indicate the source of their operands ± arith sec
� Rewriting each operation as the sum of twovalues and a carry ± implemented by adder
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A relatively Simple ALU
Arith secLogic sec
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Designing the the control unit using
hardwired controlState generation for a Relatively Simple CPU Input to CU
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control signal values for a Relatively
Simple CPU - part� Reference table 6.6 =ILDAC^T5
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Register section for he relatively Simple
CPU using multiple buses
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Exercise
� 2, 6, 7, 10, 19
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Real World Example: internal architecture
of the 8085 microprocessor ± Self study
� ALU
� Register section
� Address buffer and address/data buffer
� Interrupt control block
� Control section
� Instruction decoder and machine cycleencoding block
� Serial I/O control block
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Internal organization of the 8085
microprocessor