CHAPTER 6 Virtex Memory. Agenda RAM Applications LUT RAM –SRL 16 –Other uses of LUT RAM (FIFO...
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Transcript of CHAPTER 6 Virtex Memory. Agenda RAM Applications LUT RAM –SRL 16 –Other uses of LUT RAM (FIFO...
CHAPTER 6 Virtex Memory
Agenda
• RAM Applications
• LUT RAM– SRL 16– Other uses of LUT RAM (FIFO focus)
• Block RAM
• Inside Block RAM Cells
RAM Applications
• Operand stacks• Register files• Instruction caches• DMA buffers• Instruction memories• State tables• Logic functions• Message buffers• Virtual channels
• Video line buffers• Digital delay lines• RAMDAC color
mapping tables• Test vector buffers• PCI configuration
space• Sequential machines• More . . .
LUT/RAM/Shifter Structure
WEA0A1A2A3
CLK
WEA0A1A2A3
CLK
WEA0A1A2A3
CLK
WEA0A1A2A3
CLK
WEA0A1A2A3
CLK
D Q
D Q
D Q
D Q
D Q
CONFIGURATIONSHIFTER
SRAM
CONFIGURATION DATA
SHIFT DATASRAM DATA
CD
CD
CD
CD
CELL 0
CELL 1
CELL 2
CELL 14
CELL 15
TO CELL 3
FROM CELL 13
TO NEXT LUT SHIFT INPUT SELECT MUX
A0A1A2A3
CONFIGURATION CLOCK
CLK
DATAOUT
WEA0A1A2A3
CLK
WEA0A1A2A3
CLK
WEA0A1A2A3
CLK
WEA0A1A2A3
CLK
WEA0A1A2A3
CLK
WEA0A1A2A3
CLK
WEA0A1A2A3
CLK
WEA0A1A2A3
CLK
D QD Q
D QD Q
D QD Q
D QD Q
D QD Q
CONFIGURATIONSHIFTER
SRAM
CONFIGURATION DATA
SHIFT DATASRAM DATA
CDCD
CDCD
CDCD
CDCD
CELL 0
CELL 1
CELL 2
CELL 14
CELL 15
TO CELL 3
FROM CELL 13
TO NEXT LUT SHIFT INPUT SELECT MUX
A0A1A2A3
CONFIGURATION CLOCK
CLK
DATAOUT
Linear Feedback Shift Regs.
Galois style
Fibonacci style
Multiple SRL16E LFSR
Virtex 5 SRL 32s Cascaded
Push/Pop Shifter
D Q D Q D Q D Q D Q D QD Q D Q D QD Q D Q D QD Q D Q D Q D Q
D Q D Q D Q D Q D Q D QD Q D Q D QD Q D Q D QD Q D Q D Q D Q
D Q D Q D Q D Q D Q D QD Q D Q D QD Q D Q D QD Q D Q D Q D Q
D Q D Q D Q D Q D Q D QD Q D Q D QD Q D Q D QD Q D Q D Q D Q
D Q D Q D Q D Q D Q D QD Q D Q D QD Q D Q D QD Q D Q D Q D Q
D Q D Q D Q D Q D Q D QD Q D Q D QD Q D Q D QD Q D Q D Q D Q
D Q D Q D Q D Q D Q D QD Q D Q D QD Q D Q D QD Q D Q D Q D Q
D Q D Q D Q D Q D Q D QD Q D Q D QD Q D Q D QD Q D Q D Q D Q
DI0
DI1
DI2
DI3
DI4
DI5
DI6
DI7
DO0
DO1
DO2
DO3
DO4
DO5
DO6
DO7
CLOCK(Push and Pop)
INPUTDATABYTE
ONE LUT
OUTPUTDATABYTED Q D Q D Q D Q D Q D QD Q D Q D QD Q D Q D QD Q D Q D Q D Q
D Q D Q D Q D Q D Q D QD Q D Q D QD Q D Q D QD Q D Q D Q D Q
D Q D Q D Q D Q D Q D QD Q D Q D QD Q D Q D QD Q D Q D Q D Q
D Q D Q D Q D Q D Q D QD Q D Q D QD Q D Q D QD Q D Q D Q D Q
D Q D Q D Q D Q D Q D QD Q D Q D QD Q D Q D QD Q D Q D Q D Q
D Q D Q D Q D Q D Q D QD Q D Q D QD Q D Q D QD Q D Q D Q D Q
D Q D Q D Q D Q D Q D QD Q D Q D QD Q D Q D QD Q D Q D Q D Q
D Q D Q D Q D Q D Q D QD Q D Q D QD Q D Q D QD Q D Q D Q D Q
DI0
DI1
DI2
DI3
DI4
DI5
DI6
DI7
DO0
DO1
DO2
DO3
DO4
DO5
DO6
DO7
CLOCK(Push and Pop)
INPUTDATABYTE
ONE LUT
OUTPUTDATABYTE
Single and Dual Port LUT RAM
Dual Port Distributed SRAM Detail
Cascading LUTs for Depth
Virtex 5 32 X 2Dual Port LUT RAM
Virtex 5 32 X 6Dual Port LUT RAM
Dual Port Select RAM FIFO
Counter Structure
Asynchronous FIFO Issues
• Problems with separate clock domains– Speed discrepancy between the two domains– Possibility of overflowing
• Arrival rate/departure rate problem• Status communication
– Glitching conditions on counters– Metastability
• Would like nice, tidy “always works” solutions• Full details in Sunburst Design writeup by
Cummings & Alfke
Asynchronous FIFO Control
Virtex Family BRAMSFamily Process 32 K 16 K 8 K 4096 2048 1024 512 256
Virtex 250 nm X 1 X 2 X 4 X 8 X 16
Virtex E/EM 180 nm X 1 X 2 X 4 X 8 X 16
Virtex II 150 nm X 1 X 2 X 4 X 9 X 18 X 36
Virtex II Pro 130 nm X 1 X 2 X 4 X 9 X 18 X 36
Spartan 3/E 90 nm X 1 X 2 X 4 X 9 X 18 X 36
Virtex 4 90 nm X 1 X 2 X 4 X 9 X 18 X 36
Virtex 5 65 nm X 1 X 2 X 4 X 8 X 9 X 18 X 36
256 X 16 BRAM Module
ADDRESSDATAIN
DATAOUT
256 X 16ADDR 0-7
DIN 0-15
DOUT 0-15
RD
WR
CLK
EN
ADDRESSDATAIN
DATAOUT
256 X 16ADDR 0-7
DIN 0-15
DOUT 0-15
RD
WR
CLK
EN
256 X 32 BRAM Module
ADDRESS
DATAIN
DATAOUT
256 X 16ADDR 0-7
DIN 0-15
DOUT 0-15
RD
WR
CLK
EN
ADDRESS
DATAIN
DATAOUT
256 X 16ADDR 0-7
DIN 16-31
DOUT 16-31
RD
WR
CLK
EN
ADDRESS
DATAIN
DATAOUT
256 X 16ADDR 0-7
DIN 0-15
DOUT 0-15
RD
WR
CLK
EN
ADDRESS
DATAIN
DATAOUT
256 X 16ADDR 0-7
DIN 16-31
DOUT 16-31
RD
WR
CLK
EN
512 X 16 BRAM Module
ADDRESS
DATAIN
DATAOUT
256 X 16ADDR 0-7
DIN 0-15
DOUT 0-15
RD
WR
CLK
EN
ADDRESS
DATAIN
DATAOUT
256 X 16ADDR 0-7
RD
WR
CLK
ENADDR 8
ADDRESS
DATAIN
DATAOUT
256 X 16ADDR 0-7
DIN 0-15
DOUT 0-15
RD
WR
CLK
EN
ADDRESS
DATAIN
DATAOUT
256 X 16ADDR 0-7
RD
WR
CLK
ENADDR 8
Comment: slide needsInverter on one of the EN’s
BRAM Specialized InterconnectDECODER
DECODER
DOUTB DOUTA
CKB WEB ENB
CKA WEA ENA
DIB0-7 DOB0-7
ADB0-7
DIA0-7 DOA0-7
ADA0-7
DECODER
DECODER
DOUTB DOUTA
CKB WEB ENB
CKA WEA ENA
DIB0-7 DOB0-7
ADB0-7
DIA0-7 DOA0-7
ADA0-7
BRAM Output Multiplexing0 - 35DA[31-0]
DA[31-0]
DA[31-0]
DA[31-0]
PA[3-0]
DA[31-0]
PA[3-0]
DA[31-0]
PA[3-0]
DB[31-0]
DB[31-0]
DB[31-0]
DB[31-0]
DB[31-0]
DB[31-0]
PB[3-0]
PB[3-0]
PB[3-0]
36
1
2
4
9
18
36
1
2
4
9
18
36
36
0 - 35 0 - 35 0 - 35
Memory Array
Port A Port B
0 - 35DA[31-0]
DA[31-0]
DA[31-0]
DA[31-0]
PA[3-0]
DA[31-0]
PA[3-0]
DA[31-0]
PA[3-0]
DB[31-0]
DB[31-0]
DB[31-0]
DB[31-0]
DB[31-0]
DB[31-0]
PB[3-0]
PB[3-0]
PB[3-0]
36
1
2
4
9
18
36
1
2
4
9
18
36
36
0 - 35 0 - 35 0 - 35
Memory Array
Port A Port B
BRAM/Multiplier Relationship
Virtex II BRAM Approach
16 Bit SRAM Structure
Row Address Decoder
A0
A1
ColumnAddressDecoder
A2
A3
DATA OUTDATA INControlLogic
ENAWEOE
Row Address Decoder
A0
A1
ColumnAddressDecoder
A2
A3
DATA OUTDATA INControlLogic
ENAWEOE
Single Storage Cell of SRAM
Row Address
From ColumnTransistors
Left Row (LR)Transistor
Right Row (RR)Transistor
StorageCell
Row Address
From ColumnTransistors
Left Row (LR)Transistor
Right Row (RR)Transistor
StorageCell
Single Bit SRAM Read/Write Circuits
A2
A3
Row Address Decoder
A0
A1
ColumnAddressDecoder
DATA OUTDATA INControlLogic
ENAWEOE
Left Row (LR)Transistor
Right Row (RR)Transistor
Left Column (LC)Transistor
Right Column (RC)Transistor
A2
A3
Row Address Decoder
A0
A1
ColumnAddressDecoder
DATA OUTDATA INControlLogic
ENAWEOE
Left Row (LR)Transistor
Right Row (RR)Transistor
Left Column (LC)Transistor
Right Column (RC)Transistor
16 Bit Dual Port BRAM Structure
Row Address Decoder
Row Address Decoder
A0
A1B0
B1
ColumnAddressDecoder
B2
B3
ColumnAddressDecoder
A2
A3
DATA OUT ADATA IN A DATA OUT B DATA IN BControlLogic Control
Logic
ENAWEOE
ENA
WEOE
Row Address Decoder
Row Address Decoder
A0
A1B0
B1
ColumnAddressDecoder
B2
B3
ColumnAddressDecoder
A2
A3
DATA OUT ADATA IN A DATA OUT B DATA IN BControlLogic Control
Logic
ENAWEOE
ENA
WEOE
512 X 36 Bit FIFO
Virtex 4 BRAM Symbol
V4 BRAM Output Register Structure
V4 BRAM Cascading Structure
Virtex 4 FIFO Support Structure
(this stuff is inside the V4 BRAM module, built in)
8K X 4 Virtex 4 FIFO
Cascading like this requires a 2 IN NOR be built in the LUT fabric
512 X 72 Virtex 4 FIFOCascading like this needs 2 AND, 2 OR and 2 Inverters in LUT fabric
Virtex 5 Dual Port BRAM Symbol
Virtex 5 BRAMOrganized X 64
Virtex 5 BRAM Configurable Options
Virtex 5 BRAM Cascade
V5 BRAM Output MUX/Cascade Circuitry
Timing with/without Fall Through
V5 BRAM 64 Bit ECC
Virtex RAM Closing Comments
• RAM may be the primary on board feature beyond fabric of general use
• Makes having other on board resources more effective– FIFOs –fast cross clock domain interfacing– Microprocessors – code/data storage– DSPs – on chip operand storage– And so on . . .
• See XAPP 463 (appendix) for Verilog/VHDL code listing for using BRAM structure.