1Logic design 6, Dept. of EE, Fu Jen Catholic University, Taiwan

CHAPTER 6Register and Counters

Instructor: Kuan Jen Lin

2

Registers & Counters

Clocked sequential circuitsa group of flip-flops and combinational gatesconnected to form a feedback pathFlip-flops + Combinational gates(essential) (optional)

Register:a group of flip-flopsgates that determine how the information is transferred into the register

Counter:a register that goes through a predetermined sequence of states

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4-Bit Register withParallel Load

1

1

I00 I010

0A0

A0

4

Register IC

Selective Load Capability

74377 Octal D-type FFswith input enable

74374 Octal D-type FFswith output enable

D3

D6Q5

Q2

377

Q1Q0

Q3

EN CLK

Q6

Q4

Q7

D5

D2D1D0

D4

D7

1

3478

13141718

11

256912151619

HGFEDCBA

QHQGQFQEQDQCQBQA

OE

37411

1

3478

13141718

256912151619

CLK

5

Shift Register

Edge trigger or level trigger?

1 0 11 0

1 1 00

6

Serial transfer vs. Parallel transfer

Serial transferInformation is transferred one bit at a timeshifts the bits out of the source register into the destination register

Parallel transfer:All the bits of the register are transferred at the same time

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Serial Transfer

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Example: Serial transfer from reg A to reg B

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SerialAddition

0101

0011

1

1 0

0

1

1010

?001

1

0

1

0

1

Fig. 6.5Serial adder

Register A and B initially hold the augendand addend.

After the add-operation, A holds the sum and B can be used to store q new input

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Second Form of Serial Adder

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A universal shift register

1. A clear control to clear the register to 0.2. A clock input to synchronize the operations.3. A shift-right control to enable the shift right operation and

the serial input and output lines associated w/ the shift right.4. A shift-left control to enable the shift left operation and the

serial input and output lines associated w/ the shift left.5. A parallel-load control to enable a parallel transfer and the n

parallel input lines associated w/ the parallel transfer.6. n parallel output lines.7. A control state that leaves the information in the register

unchanged in the presence of the clock.

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4-bit universal shift register

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Function tableof a 4-bit universal shift register

Function table

Clear s1 s0 A3+ A2+ A1+ A0+ (operation)

0 × × 0 0 0 0 Clear1 0 0 A3 A2 A1 A0 No change1 0 1 sri A3 A2 A1 Shift right1 1 0 A2 A1 A0 sli Shift left1 1 1 I3 I2 I1 I0 Parallel load

14

15

Ripple Counters

Counters are available in two categories: ripple counters and synchronous counters.In a ripple counter, the flip-flop output transition serves as a source for triggering other flip-flops.In a synchronous counter, the C inputs of all flip-flops receives the common clock.

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4-Bit count sequence

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0 0 0 00 0 0 10 0 1 00 0 1 10 1 0 00 1 0 10 1 1 00 1 1 11 0 0 01 0 0 11 0 1 01 0 1 11 1 0 01 1 0 11 1 1 01 1 1 1

A3 A2 A1 A0

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BCD Ripple Counter

A decimal counter follows a sequence of ten states

And returns to 0 after the count of 9.

A decimal counter follows a sequence of ten states

And returns to 0 after the count of 9.

BCD Ripple Counter

•每一個clock cycle，Q1 改變一次。•每當Q1: 1->0，Q2改變一次；除了當 Q8= 1, Q2 維持不變。•每當Q2: 1->0，Q4改變一次•當 1110時，下一個clock，Q8->1。•當 1001時，下一個clock，Q8->0。

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Three-Decade Decimal BCD Counter

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Synchronous Counter

A common clock triggers all flip-flops simultaneouslyThe flip-flop in the least significant position is complemented with every pulse. A flip-flop in any other position is complemented when all the bits in the lower significant positions are equal to 1.

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Waveform of 4-Bit Synchronous Counter

Clock

A0

A1

A2

A3

Up-Down Counter

Up: 0000=>0001=>0010….=>1111=>0000

Down:

1111=>1110=>1101=>….=>0000=>1111

1 0

0

0

0

0

0

0

1

1

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BCD Counter

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4-bit binary counter with parallel load

Fig. 6.14 Four-bit binary counter with parallel load

4-bit Binary Counter with Parallel Load

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Implement BCD Counter using a Counter with Parallel Load

A circuit with n flipflops has 2n binary states.

Use less than this maximum possible number of states.

Table 6-7

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A MOD-12 Counter

A mod 100 counter?

30

Construct a counter that counts from 0 to 64

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Clock Divider

A digital system has a clock generator that produces pulses at a frequency of 80MHz. Design a circuit that provides a clock with a cycle time of (1) 50 ns; (2) 1ms.

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Ring Counter

A ring counter is a circular shift register with only one flip-flop being set at any particular time, all others are cleared.The single bit is shifted from one flip-flop to the next to produce the sequence of timing signals.The timing signals can be generated also by a 2-bit counter that goes through four distinct states.To generate 2n timing signals, we need either a shift register with 2n flip-flops or an n-bit binary counter together with an n-to-2n-line decoder.

Ring Counter

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Johnson Counter

A k-bit ring counter circulates a single bit among the flip-flops to provide k distinguishable states.A switch-tail ring counter is a circular shift register with the complement output of the last flip-flop connected to the input of the first flip-flop.In general, a k-bit switch-tail ring counter will go through a sequence of 2k states.A John counter is a k-bit switch-tail ring counter with 2k-decoding gates to provide outputs for 2k timing signals.

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Design a Circuit to Generate Control Signals (use Johnson counter)

Clock

A

B

C

D