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Transcript of Chapter 6-Introduction to Nanoelectronics
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Introduction toIntroduction toNanoelectronics andNanoelectronics and
FabricationFabrication
Dr. Sabar D. HutagalungSchool of Materials and Mineral ResourcesEngineering, Universiti Sains Malaysia,
14300 Nibong Tebal, Penang, Malaysia
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NanoscienceNanoscience
working small,thinking big
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Nano:From the Greeknanos -meaning "dwarf,
this prefix is used in themetric system to mean10-9 or
1/1,000,000,000.
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What is Nanotechnology?
Nanotechnology is the creation of functional
materials, devices, and systems through control of
matter on the nanometer (1 to 100 nm) length scale
and the exploitation of novel properties andphenomena developed at that scale.
A scientific and technical revolution has begun that
is based upon the ability to systematically organize
and manipulate matter on the nanometer lengthscale.
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Is this technology new?
In one sense there is nothing new
Whether we knew it or not, every piece oftechnology has involved the manipulation of
atoms at some level. Many existing technologies depend crucially on
processes that take place on the nanometerscale.
Ex: Photography & CatalysisNanotechnology, like any other branch of science, is
primarily concerned with understanding how nature works.
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Why is this length scale soimportant?
There are five reasons: The wavelike properties of electrons inside matter are
influenced by variations on the nanometer scale. By
patterning matter on the nanometer length, it is possible
to vary fundamental properties of materials (for instance,melting temperature, magnetization, charge capacity)
without changing the chemical composition.
The systematic organization of matter on the nanometer
length scale is a key feature of biological systems.
Nanotechnology promises to allow us to place artificial
components and assemblies inside cells, and to make
new materials using the self-assembly methods of nature.
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Nanoscale components have very high surface areas,making them ideal for use in composite materials,reacting systems, drug delivery, and energy storage.
The finite size of material entities, as compared to the
molecular scale, determine an increase of the relativeimportance ofsurface tension and local electromagneticeffects, making nanostructured materials harder and lessbrittle.
The interaction wavelength scales of various externalwave phenomena become comparable to the materialentity size, making materials suitable for various opto-electronic applications.
Why is this length scale soimportant?
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How Small We can make the
grains? Because of high surface areas conventional
powders methods reach their limits at 10-6 m
(1 micron) Smaller particles can be made but special
methods are needed!
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Working at the nanoscale
Working in the nanoworld was first proposed byRichard Feynman back in 1959.
But it's only true in the last decade.
The world of the ultra small, in practical terms, isa distant place.
We can't see or touch it.
Because, optical microscopes can't provide
images of anything smaller than the wavelengthof visible light (ie, nothing smaller than 380
nanometres).
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From Theres Plenty of Room at the Bottom, Dec 29, 1959
This image was written using Dip-Pen Nanolithography, and imaged using lateral force
microscopy mode of an atomic force microscope.
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What is Nanoelectronics
Nanoelectronic device? A very small devices to ovecome limits on scalability
Examples: Single-Electron Transistors
controlled electron tunneling to amplify current
Resonance Tunneling Device quantum device use to control current
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Problem of Making MorePowerful Chips The number of
transistors on a chipwill approximately
double every 18 to 24months (MooresLaw).
This law has givenchip designers greater
incentives toincorporate newfeatures on silicon.
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Problem of Making MorePowerful Chips
However, more
transistors means
more electricity and
heat compressed intoa smaller space.
Furthermore, smaller
chips increase
performance but alsocreate the problem of
complexity.
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Problem of Making MorePowerful Chips
A basic MOSFET
Band diagram when on
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Problem of Making MorePowerful Chips
Quantum and coherence
effects, high electric fields
creating avalanche dielectric
breakdowns, heat dissipationproblems in closely packed
structures as well as the non-
uniformity of dopant atoms and
the relevance of single atomdefects are all roadblocks along
the current road of
miniaturization.
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Problem of Making MorePowerful Chips
Problem 1: Carrier mobility
decreases aschannel lengthdecrease and
vertical electricfields increase.
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Problem of Making MorePowerful Chips
Problem 2: Tunneling
through gateoxide (off state
current).
Eox
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Problem of Making MorePowerful Chips
Problem 3: Wattage/Area
increases asdensityincreases
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Single-Electron Transistors(SETs) To solve these problem, the
single-electron tunnelingtransistor - a device thatexploits the quantum effect of
tunneling to control andmeasure the movement ofsingle electrons wasdeveloped.
Experiments have shown thatcharge does not flowcontinuously in these devicesbut in a quantized way.
Fig. A single-electron transistor
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Single-Electron Transistors(SETs) SET consists of a gate
electrode that electrostaticaly
influences electrons traveling
between the source and drain
electrodes. The electrons in the SET need
to cross two tunnel junctions
that form an isolated
conducting electrode calledthe island.
Fig. A single-electron transistor
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Single-Electron Transistors(SETs) Electrons passing through the
island charge and discharge it,
and the relative energies of
systems containing 0 or1
extra electrons depends onthe gate voltage.
The key point is that charge
passes through the island in
quantized units.
Fig. A single-electron transistor
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Single-Electron Transistors(SETs)
For an electron to hop onto the
island, its energy must equal
the Coulomb energy, e2/2C.
When both the gate and bias
voltages are zero, electrons do
not have enough energy to
enter the island and current
does not flow.
Fig. A single-electron transistor
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Single-Electron Transistors(SETs) As the bias voltage between
the source and drain isincreased, an electron canpass through the island when
the energy in the systemreaches the Coulomb energy. This effect is known as the
Coulomb blockade, and thecritical voltage needed to
transfer an electron onto theisland, equal to e/2C, is calledthe Coulomb gap voltage.
Fig. A single-electron transistor
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Here n1 and n2 are the number ofelectrons passed through the tunnelbarriers 1 and 2, respectively, sothat n = n1 - n2, while the total island
capacitance, C, is now a sum ofCG, C1, C2, and whatever straycapacitance the island may have.
Left: Equivalent circuit of anSET
Center: Energy states of an
SET. Top Coulomb blockade
regime, bottom transfer regime
by application of VG=e/2CG
Right: I-V characteristic fortwo different gate voltages.
Solid line VG= e/2CG, dashed
line VG =0
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The Coulomb blockade is a single-electron phenomenon, which originates
in the discrete nature of electric charge that can be transferred from a
conducting island connected to electron reservoirs through thin barriers.
The CB allows a precise control of small number of electrons, withimportant application in switching devices with low power dissipation and a
corresponding increased level of circuit integration.
Coulomb Blockade
Single-electron devices based on the Coulomb blockade.
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DOT
I-V curve controlled by gate
voltage, showing region of QB
Tunneling & QBlockade in SET
Q transport by single-electrontunneling, but essentially suppressedby Coulomb charging energy:
Ec > kbT (Ec = e2/2C)
Tunneling resistance, Rt > Rk
(Junction resistance,
Rk = h/e2 = 25.8 K )
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Silicon SET
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Silicon nanowire transistors
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Enhanced Channel Modulation in Dual-Gated Silicon
Nanowire Transistors
Nano Letters Vol. 5, 2005, 2519-2523
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(a)Schematic of a NW FET, and (inset)
FE-SEM image of a GaN NW FET.
(b)Gate-dependent IVsd data recorded on
a 17.6 nm diameter GaN NW. The gate
voltages for each IVsd curve are
indicated;
(c) IVg data recorded for values of Vsd .
(Inset) Conductance, G, vs gate voltage
C.N.R. Rao et al. / Progress in Solid State Chemistry 31 (2003) 5147.
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ZnO nanorod FETs
Park et al., APL, 85 (2004) 5052-5054
(a)Schematic side view and
(b) field-emission scanning
electron microscopy (FESEM)
image of a ZnO nanorod FET
device.
ZnO nanorod FETs with backgate
geometry were fabricated on SiO2/Si by
deposition of Au/Ti metal electrodes for
source-drain contacts on nanorod
ends.
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(a) Typical IsdVsdcharacteristic
curves as a function ofVgfor ZnO
nanorod FETs. The linear and
symmetric IsdVsdcurves were
obtained under different Vg,
indicating the low resistant ohmic
contact formation between ZnO
and Ti metal layers.
(b) IsdVgcurves of ZnO nanorod
FETs show that the devices
operate in an n-channel depletion
mode with gmof ~140 nS forVsd =
1.0 V.
Park et al., APL, 85 (2004) 5052-5054
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FET fabricated based on
In2O3 nanowires:(a) IV curves recorded
on an In2O3 nanowire of
10 nm diameter,
(b) IVg data of the same
device at Vds = 10 mV.
Inset shows the SEM
image of the nanowire
between the source and
drain electrodes.
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Direct Integration of Metal Oxide Nanowire in Vertical
Field-Effect Transistor
Nano Letters Vol. 4, 2004
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Carbon Nanotube Transistor
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NanoelectronicFabrication
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NanofabricationNanofabrication
Top-downApproach
Bottom-upApproach
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Top-down techniques take a bulk material, machine it, modify it into the
desired shape and product classic example is manufacturing of integrated circuits using a sequence of steps sushas crystal growth, lithography, deposition, etching, CMP, ion implantation
(Microelectronic/Nanoelectronics Fabrication Approach)(Microelectronic/Nanoelectronics Fabrication Approach)
Bottom-up techniques build something from basic materials assembling from the atoms/molecules up not completely proven in manufacturing yet
Examples: Self-assembly Sol-gel technology Deposition (old but is used to obtain nanotubes, nanowires, nanoscale
films) Manipulators (AFM, STM,.)
Top-down vs Bottom-up
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Top-down
From large items to smaller ones. The most common method are
electron beam lithography(EBL) and
scanning probe lithography(SPL). The approach involves molding or etching materials
into smaller components.
Making IC?
Starting with a thin sheet Si wafer,cleaned, coated, preferentiallyetched using highly focused optics inas many as 100 separate operationsbefore the final IC is complete.
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Bottom-up
A general approach
going from small items
to bigger ones.
Building larger, morecomplex objects by
integration of smaller
building blocks or
components.
The sketch shows the essence of
bottom-up manufacturing. Self-assembly from the gaseous
phase. Two principle vapor-phase
technologies that are useful and
widely practiced:
molecular beam epitaxy (MBE) and
vapor-deposition (PVD, CVD).
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Fabrication of SET
SET with a nano particleSET with a nano particle connected
by SWCNs
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FIG. (a) Sketch of the SOInanowire: a metallic top gate
is separated from the SiNW
by a 55 nm silicon oxide.
(b) SEM micrograph of thenanowire with a width below
10 nm and a length of 500
nm.
PHYSICAL REVIEW B 68, 075311 (2003)
Fabrication of SET
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Fabrication of SET
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Fig. Patterning ofSiNWs.
(A) Overview and (B)
zoomed in image of
patterned lines of
vertical SiNWs grown
from lines of singlenanoparticle catalysts
deposited onto a Si
substrate.
(C) A crosssection SEM
image of nanowires that
were positionally aligned
into lines.
Non-Lithographic PositionalControl of SiNWs
The scale bar in images (A), (B), and (C) correspond to 100 m, 1 m, and 1m.
Goldberger, Hochbaum, Fan, and Yang, Nano Letters, 6 (2006) 973 - 977
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Blue corresponds to the Si substrate and the SiNWs channel, grey is SiO2 dielectric
material, and red corresponds to the Cr gate metal.
Vertically IntegratedNanowire Field Effect
Transistors (VINFET)
Fig. Si VINFET fabrication. (A) SiNWs are grown vertically from a Si(111)
substrate. (B) Thermal oxidation of the Si nanowire is used to form the gate
dielectric. (C) The Cr gate material is then sputtered onto the nanowires to
achieve a conformal coating.
Goldberger, Hochbaum, Fan, and Yang, Nano Letters, 6 (2006) 973 - 977
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Fig. Si VINFET fabrication. (A) Conformal LPCVD oxide is deposited around the
nanowire. (B) The Cr-coated nanowire tips are exposed via chemomechanical
polishing and plasma etching of the SiO2 dielectric. (C) The Cr gate material isetched-backed using a Cr photomask etchant. (D) An SEM image taken after the
SiO2 deposition. (E) An SEM image showing the exposed Cr-coated tips. (F) an
SEM image of the device after the Cr etch back procedure.
Goldberger, Hochbaum, Fan, and Yang, Nano Letters, 6 (2006) 973 - 977
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Fig. Si VINFET fabrication. (A) Another layer of LPCVD SiO2 is deposited
onto the nanowire. (B) The nanowire tips are exposed via plasma etching of
the SiO2 dielectric. (C) Ni / Pt contacts are sputtered onto the sample to formthe drain electrode. Cr gate material is then sputtered onto the nanowires to
achieve a conformal coating.
Yellow corresponds to the Ni drain material.
Goldberger, Hochbaum, Fan, and Yang, Nano Letters, 6 (2006) 973 - 977
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In the case for our system (p-type nanowires) with a Cr gate electrode, the
threshold voltage (Vt);
Where VFB is the flatband voltage, NA is the acceptor concentration in Si, C is the
oxide capacitance, s is the oxide permittivity, and s is the surface potential.Since the onset of accumulation for an metal-oxide-semiconductor system occurs
when the surface potential is zero, the threshold voltage is equal to the flatband
potential. VFB can be deduced by the following equation;
Where M is the gate work function, is the electron affinity of Si, and Eg is the
band gap of silicon. F is given by the formula;
Threshold VoltageAnalysis
Goldberger, Hochbaum, Fan, and Yang, Nano Letters, 6 (2006) 973 - 977
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Where ni is the intrinsic carrier concentration in Si.More accurate analyses of the influence of carrier concentration on
threshold voltage at these small length scales can be derived using
drift-diffusion simulations.
Threshold VoltageAnalysis
Goldberger, Hochbaum, Fan, and Yang, Nano Letters, 6 (2006) 973 - 977
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(B) Ids vs Vgs with Vds ranging from -1.0 V to -0.2 V in 0.2 V steps, from
top to bottom, respectively, measured from a device with 48
nanowires in parallel.
(C) TEM image of a 6.5 nm SiNW, obtained from the device used in(A).Scale bar is 100 nm. A typical device has a ~6-7 nm SiNWs diameter,surrounded by a ~30- 35 nm thick shell of SiO2, and a Cr metal gate
length of ~300-350 nm.
Fig. Ultra-thin body VINFET.
(A) Cross-sectional SEM image. The
scale bar is 200 nm. Blue is Si
source, grey SiO2
dielectric, red the
gate material, and yellow the drain
metal. The SiNW is not colored, due
to the inability of resolving this
feature via SEM.
The Cr coverage on the front of the
wire was likely stripped duringcleavage.
Goldberger, Hochbaum, Fan, and Yang, Nano Letters, 6 (2006) 973 - 977
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Fabrication Approaches toNanowires Devices Removing the nanorods/nanowires from the initial growth susbtrate
is by sonification in a solvent such ethano.
Fig. shows ZnO nanorods aftergrowth on the Si substrate (left)
and after 5 min sonification inethanol (right).
The acoustic energy supplied to
the solvent is enough to
dislodge a large fraction of the
nanorods and disperse them
into the solution.It was found that >90% of the
nanorods could be harvested in
this manner.
Mater. Sci. Eng. R 47 (2004) 147
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Transfer of the nanorods from the ethanol solution to a new
substrate is by dispersing the solution onto the new
substrate, followed by evaporation of the ethanol.
The advantage of this approach is simplicity but the maindrawback is the random nature of where the nanorods are
placed.
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The approach is to initially prepare an SiO2-coated Si wafer and etch alignment
marks into the SiO2.
Once the NWs are on this new substrate, a mask design for the particular device
being fabricated using software on an e-beam writer and then transferred
lithographically so that the ends of the NWs are covered by Ohmic contact pads.
The approach
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Fig. SEM micrographs of structure for transport measurements of ZnO
nanowires (top) and close-up of central region (bottom).
Fig. Schematic of ZnO nanowire depletion-
mode FET.
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SET Fabrication Using EBL
Wafer Cutting (sample size 15 mm X 15 mm)
Wafer Cleaning (Standard Cleaning 1)
Substrate Heating Up (200C, 30 minutes)
Spin Coating (3000 rpm spin speed, 30 seconds)
Pre-bake Hotplate (90C, 2 minutes)
E-beam Exposure (Exposure e-beam doses variation)
Development (ma-D 532, 25 seconds)
Rinse in Stopper (De-Water, 5 minutes)
Uda Hashim et al, UniMAP
S D i & Q t D t D i
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Source-Drain & Quantum Dot DesignMask
SET Mask design schematic
SET Mask Design using GDSIIEditor
Uda Hashim et al, UniMAP
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Nanodevices PatternedUsing SPL
(Scanning ProbeLithography)
S i b i (SPM)Scanning probe microscope (SPM):
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Tunneling Curren
Metal Tip
Sample
e- cloud
Scanning probe microscope (SPM):Scanning probe microscope (SPM):
from STM to AFMfrom STM to AFM
SPM was originated from the scanning tunnelingmicroscopy (STM).
SPM is a relatively new family of microscope thatcan
measure surface morphology down to atomic resolution, 3D imaging, and make nanopatterns (line or dot arrays).
STM uses the tunneling current flowing
between tip and sample to map the
topography.
STM is limited toconductive samples.
S i b i (SPM)Scanning probe microscope (SPM):
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Atomic Force Microscopy (AFM) extended theapplications of SPM
Forconductive & non-conductive samples, even insolutions.
AFM measures the attractive or repulsive forcesbetween the tip and sample.
Many surface/interface properties (mechanical,magnetic, electric, optical, thermal, chemical properties)can be measured using AFM.
AFM also used for fabrication of various nanostructurespatterns (AFM-based nanolithography).
Scanning probe microscope (SPM):Scanning probe microscope (SPM):
from STM to AFMfrom STM to AFM
Comparison of SPM and other Microscope
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10
mm
10um
10nm
10 nm 10 um 10 mmX,Y Resolution
ZReso
lution
SEMOpticalMicroscope
10pm
SPM
TEM
Comparison of SPM and other Microscope
0.2nm
800 um
15um
A li i f M l i f i SPM
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Semi-Semi-
conductorconductor
PolymerPolymer
PlasticPlastic
RubberRubber
StorageStorage
devicedeviceHDHD
MemoryMemory
FerroelectricFerroelectric
devicedeviceMemoryMemory
Thin filmThin film
BiotechnologyBiotechnology
ProteinProtein
CellCell
InorganicInorganic
GlassGlass
CeramicsCeramics
MetalMetal
RaRa ParticleParticle & grain& grain analysisanalysis Pitch & height measurementPitch & height measurementTopography
VEVE FrictionFriction AdhesionAdhesion HardnessHardness Nano-indentationNano-indentation Mechanical
Leak CurrentLeak Current PolarizationPolarization Dielectric constantDielectric constant Surface PotentialSurface PotentialElectric
Magnetic ForceMagnetic Force Magnetic Domain & FluxMagnetic Domain & FluxMagnetic
FluorescenceFluorescence SpectrumSpectrum Optical TransitionOptical Transition Optical RecordOptical RecordOptical
Lithography Manipulation oxidization ScratchProcessing
Applications of Multi-function SPMApplications of Multi-function SPM
S i P b Lith (SPL)Scanning Probe Lithograpy (SPL)
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Scanning Probe Lithograpy (SPL)Scanning Probe Lithograpy (SPL)
One of the most methods is local anodicoxidation (LAO) by AFM where the application of a +ve voltage to the
surface with respect to the tip in humidity atmosphere.
By controlling the certain condition between
the AFM tip and the sample, desirednanopatterns can be created.
Experimental Method
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Experimental Method
Silicon waferSilicon wafer
(n-type 100)(n-type 100)
NanoPatterninNanoPatternin
gg
(by AFM)(by AFM)
RCA CleaningRCA Cleaning
(RCA 1 & RCA(RCA 1 & RCA
2)2)
PassivatedPassivated
(5 % HF 10 s)(5 % HF 10 s)SurfaceSurface
AnalysisAnalysis
(by AFM)(by AFM)
SPI3800N SeriesSPI3800N Serieswith SPA-300HVwith SPA-300HV
NanoNavi (vector & rasterNanoNavi (vector & raster
scan),scan), conductive AFM tipconductive AFM tip
(coated Rh,(coated Rh, TIPTIP
20 3020 30nm)nm)
V t S
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Vector Scan
BeforBefor
eeAfterAfter
AFM Lithography (Si wafer) by electrolyte oxidation
0.2m
Scan
Electrolyte Oxidation
Cantilever
Raster Scan Fine fabrication b Raster Scan
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Raster Scan - Fine fabrication by Raster Scan -
Nano dots
on Si wafer
sample
D:
Symbol
image by
Raster scan
By Nano function Project team NITS Nano Tech. depart.
BMP file of designAfter fabrication
Recall BMP file
Vector Scan Raster Scan
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Vector Scan Raster Scan- Influence of absorbed water layer
Fabrication by
Raster scan
Apply 5V
Voltage to 1m
area
Measurement
area 2m
Air Vacuum 410-6
Torr
200nm 200nm
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OXIDIZED LINESCRATCH LINE
SILICONWAFER
OXIDIZED DOT
Scratch and Oxide Line
Single dot double dots and triple dots patterned on silicon
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Single dot, double dots, and triple dots patterned on siliconsurfaceat -8V tip bias voltage with different oxidation time.
3 ms 5 ms
8 ms 1 ms
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Dot Oxide Array on Si (100) wafer
( h 10 nm and w 200 nm )
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Oxide Dot Array (Surface Profile)
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Line Oxide
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Line Oxide (With Profile)
LAO Mechanism
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LAO Mechanism
The oxides grow on substrateby the application of a voltagebetween a conductive tip(cathode) and a substrate(anode).
Water molecules adsorbed ona substrate dissociates intofragments (e.g. H+, OH-, andO2-) and acts as electrolyte.
Schematic diagram of local-
anodic-oxidation (LAO)
process performed by AFM.
Cervenka et al., Appl. Surf. Sci., 253 (2006) 2373.
T.-H. Fang, Microelectronics Journal, 35 (2004) 70.
LAO Mechanism
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LAO Mechanism
At the Si/SiO2 interface, OH-
react with holes h+as follow:
Si + 4h+ + 2OH
SiO2+ 2H+
The proton concentrationincreases after long pulsetimes, with the
H+ + OHH2O
neutralization reaction.
Schematic diagram of local-
anodic-oxidation (LAO)
process performed by AFM.
Cervenka et al., Appl. Surf. Sci., 253 (2006) 2373.
T.-H. Fang, Microelectronics Journal, 35 (2004) 70.
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SET Pattern
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SET Pattern
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SET Pattern (Profile)
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SET Pattern (Profile)
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SET Pattern (Profile)
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USM letter Oxide on Si (100) wafer
Summary
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Summary
Nanoelectronics is not only about size but alsophenomena, mechanism, etc.
Nanoelctronics is a wide open field with vastpotential for breakthroughs coming fromfundamental research.
Some of the major issues that need to be addressedare: Understand nanoscale transport (theory & experimental). Develop/understand self-assembly techniques to do
conventional things cheaper. Find new ways of doing electronics and find ways of
implementing them (e.g. quantum computing; hybrid Si-biological systems; cellular automata).