Chapter 6 Differential and Multistage Amplifiers The most widely used circuit building block in...

Chapter 6Differential and Multistage Amplifiers

The most widely used circuit building block in analog integrated circuits.

Use BJTs, MOSFETS and MESFETs (metal semiconductor FET – read 5.12 – Gallium Arsenide-GaAs Device).

• Differential pair circuits are one of the most widely used circuit building blocks. The input stage of every op amp is a differential amplifier

• Basic Characteristics – Two matched transistors with emitters

shorted together and connected to a current source

– Devices must always be in active mode – Amplifies the difference between the two

input voltages, but there is also a common mode amplification in the non-ideal case

• Let’s first understand how this circuit works.

• Assume the inputs are shorted together to a common voltage, vCM, called the common mode voltage – equal currents flow through Q1 and Q2

– emitter voltages equal and at vCM-0.7 in order for the devices to be in active mode

– collector currents are equal and so collector voltages are also equal for equal load resistors

– difference between collector voltages = 0 • What happens when we vary vCM?

– As long as devices in active mode, equal currents flow through Q1 and Q2

– Note: current through Q1 and Q2 always add up to I, current through the current source

– So, collector voltages do not change and difference is still zero….

– Differential pair circuits thus reject common mode signals

• Q2 base grounded and Q1 base at +1 V

– All current flows through Q1

– No current flows through Q2

– Emitter voltage at 0.3V and Q2’s EBJ not FB

– vC1 = VCC-IRC

– vC2 = VCC

• Q2 base grounded and Q1 base at -1 V

– All current flows through Q2

– No current flows through Q1

– Emitter voltage at -0.7V and Q1’s EBJ not FB

– vC2 = VCC-aIRC

– vC1 = VCC

• Apply a small signal vi

– Causes a small positive DI to flow in Q1

– Requires small negative DI in Q2 • since IE1+IE2 = I

– Can be used as a linear amplifier for small signals (DI is a function of vi)

• Differential pair responds to differences in the input voltage – Can entirely steer current from one side of

the diff pair to the other with a relatively small voltage

• Let’s now take a quantitative look at the large-signal operation of the differential pair

Large-Signal Operation

• First look at the emitter currents when the emitters are tied together

• Some manipulations can lead to the following equations

• and there is the constraint:

• Given the exponential relationship, small differences in vB1,2 can cause all of the current to flow through one side

T

EB

V

Vv

SE e

Ii

1

1 T

EB

V

Vv

SE e

Ii

2

2 T

BB

V

vv

E

E ei

i 21

2

1

T

BB

V

vvEE

E

eii

i12

1

1

21

1

T

BB

V

vvEE

E

eii

i21

1

1

21

2

Iii EE 21

T

BB

V

vvE

e

Ii

12

11

T

BB

V

vvE

e

Ii

21

12

• Notice vB1-vB2 ~= 4VT enough to switch all of current from one side to the other

• For small-signal analysis, we are interested in the region we can approximate to be linear

– small-signal condition: vB1-vB2 < VT/2

Small-Signal Operation• Look at the small-signal operation: small

differential signal vd is applied

– expand the exponential and keep the first two terms

T

d

V

vC

e

Ii

11

dBB vvv 21

T

d

T

d

T

d

V

v

V

v

V

v

C

ee

Iei

22

2

1

2222121

211

d

TTdTd

TdC

v

V

II

VvVv

VvIi

2222d

TC

v

V

IIi

22d

Tc

v

V

Ii

TT

Cm V

I

V

Ig

2

2dmc vgi

multiply top and bottom by

T

d

V

v

e 2

Differential Voltage Gain

• For small differential input signals, vd << 2VT, the collector currents are…

• We can now find the differential gain to be…

21d

mCC

vgIi

22d

mCC

vgIi

21d

CmCCCCC

vRgRIVv

22d

CmCCCCC

vRgRIVv

Cmd

ccd Rg

v

vvA

21

Differential Half Circuit

• We can break apart the differential pair circuit into two half circuits – which then looks like two common emitter circuits driven by +vd/2 and –vd/2

• We can then analyze the small-signal operation with the half circuit, but must remember

– parameters r,gm, and ro are biased at I/2

– input signal to the differential half circuit is vd/2

– voltage gain of the differential amplifier (output taken differentially) is equal to the voltage gain of the half circuit

oCmd

cd rRg

v

vA

21

vd/2 r v

gmvr RC

vc1

Common-Mode Gain

• When we drive the differential pair with a common-mode signal, vCM, the incremental resistance of the bias current effects circuit operation and results in some gain (assumed to be 0 when R was infinite)

R

Rv

rR

Rvv C

CMe

CCMC 221

R

Rvv C

CMC 22

• If the output is taken differentially, the output is zero since both sides move together. However, if taken of the single circuit, the common-mode gain is finite

• If we look at the differential gain of the circuit, we get…

• Then, the common rejection ratio (CMRR) will be

– which is often expressed in dB

R

RA C

cm 2

Cmd RgA

RgA

ACMRR m

cm

d

2

1

cm

d

A

ACMRR 10log20

CM and Differential Gain Equation

• Input signals to a differential pair usually consists of two components: common mode (vCM) and differential(vd)

• Thus, the differential output signal will be in general…

221 vv

vCM

21 vvvd

2

2121

vvAvvAv cmdo

The BJT Differential Pair

Use CD

Implemented by a transistor circuit

Connection to RC not essential to the operation

Essential that Q1 and Q2 never enter saturation

Different Modes of Operation

Differential pair with a common-mode input

Common voltage

I/2

vE = vCM-VBE

vC1 = VCC – ( ½) I RC

vC2 = VCC – ( ½) I RC

vC1 – vC2 = ?

Vary vCM (what happens?)

Rejects common-mode

Differential pair with a large differential input


vB1 = +1

Q1

Q2

vE = 0.3

Keeps Q2 off

vC1 = VCC - I RC

vC2 = VCC

Differential pair with a large differential input o opposite polarityTo that of (b)


Differential pair with a small differential input


Exercise 6.1

5 0.71

4.3 vE 0.7

vC2 5 4.3 1 vC2 0.7

vC1 5

Large-Signal Operation of the BJT Differential Pair

Equations

iE1IS

e

vB1 vE( )

VT

iE2IS

e

vB2 vE( )

VT

iE1

iE2e

vB1 vB2( )

VT

iE1

iE1 iE21

1 e

vB2 vB1( )

VT

iE2

iE1 iE21

1 e

vB1 vB2( )

VT

iE11

1 e

vB2 vB1( )

VT

iE21

1 e

vB1 vB2( )

VT

Which can be manipulated to yield

iE1 iE2 I

I

I

The collector currentscan be obtained by multiplying the emitter currents by Alfa, which is ver close to unity

Large-Signal Operation of the BJT Differential Pair

Relatively small difference voltage vB1 – vB2 will cause the current I to flow almost entirely in one of the two transistors.

4.VT (~100mV) is sufficient to switch the current to one side of the pair.

Small-Signal OperationThe Collector Currents When vd is applied

vd vB1 vB2

iC1 I

1 e

vd

VT

iC2 I

1 e

vd

VT iC1 I e

vd

2 VT

e

vd

2 VTe

vd

2 VT

vd

2 VT

iC1

I 1vd

2 VT

1vd

2 VT 1

vd

2 VT

iC1

I 1vd

2 VT

1vd

2 VT 1

vd

2 VT

~

iC2 I2

I2 VT

vd

2 iC1

I2

I2 VT

vd

2

vBQ1 VBEvd

2 vBQ2 VBE

vd

2 gm

IC

VT

I

2

VT

ic

Multiplying by

Assuming vd<<2VT

Interpretation: IC1 increases by ic and iC2 decreases by ic

An Alternative Viewpoint

reVT

IE

VT

I

2

ievd

2 re

Assume I to be ideal – its incremental resistance will be infinite and vd appears across a total resistance 2.re.

ic ie vd2 re

gmvd

2

A simple technique for determining the signal currents in a differential amplifier excited by a differential voltage signal vd; dc quantities are not

shown.

If emitter resistors are included

ievd

2 re 2 RE

A differential amplifier with emitter resistances. Only signal quantities are shown (on color).

Input Differential Resistance

ibie

1

vd

2 re

1

Ridvd

ib 1 2 re 2 r

This is the resistance-reflection rule; the resistance seen between the two bases is equal to the total resistance in the emitter circuit multiplied by the beta+1

Input Differential Resistance

Rid 1 2 re 2 RE( )

Differential Voltage Gain

iC1 IC gmvd

2 iC2 IC gm

vd

2 IC

I2

vC1 VCC IC RC( ) gm RCvd

2

vC2 VCC IC RC( ) gm RCvd

2

Advc1 vc2

vdgm RC

Ad 2RC( )

2 re 2 RE( )

RCre RE

Ad 2RC( )

2 re 2 RE( )

RCre RE

The voltage gain is equal to the ratio of the total resistance in the collector circuit (2RC) to the total resistance in the emitter circuit (2re+2RE)

~

Equivalence of the differential amplifier (a) to the two common-emitter amplifiers in (b). This equivalence applies only for differential input signals. Either of the two common-emitter amplifiers in (b) can be used to evaluate the differential gain, input differential resistance, frequency response, and so on, of the differential amplifier.

Equivalence of the Differential Amp. To a Common-Emitter Amp.

Differential amplifier fed in a complementary manner (push-pull or balanced)

Base of Q1 raisedBased of Q2 lowered

Equivalent Circuit Model of a Differential Half-Circuit

Ad gmRC ro

RC ro

Common-Mode Gain

vc1 vCM RC

2 R re vCM

RC2 R

vc2 vCM RC2 R

Acm RC2 R

Ad1

2gm RC

CMRRAd

Acm

Assuming symmetry

AcmRC

2 RRC

RC vCM

v1 v22

vo Ad v1 v2( ) Acmv1 v2

2

If output is taken single-endedlyAcm and the differential gain AdWe can define CMRR

CMRR gm R 1

Common-mode half-circuits

Assuming non-symmetry

Input Common-Mode Resistance

vCM ro

r

Ricm =

Ricm

2 . Ricm

vCM

Equivalent common-mode half-circuitSince the input common-mode resistance is usually very large, its value will be affected by the transistor resistancesR0 and r

Example 6.1 – Class Discussion

Example 6.3

I 1 VCC 15 RC 10 1

vB1 t( ) 5 0.005sin 2 1000 t

vB2 t( ) 5 0.005sin 2 1000 t vBE 0.7 at 1mA

a) vE b) gm c) iC d) vC e) vc1-vc2 f) gain at 1000Hz

a )

VBE 0.7 0.025ln0.5

1

VBE 0.683

vE 5 VBE vE 4.317

b )

gmIC

VT gm 20

c )

iC1 t( ) 0.5 gm 0.005sin 2 1000 t iC2 t( ) 0.5 gm 0.005sin 2 1000 t

0 0.001 0.002 0.003 0.004 0.0050.3

0.4

0.5

0.6

iC1 t( )

iC2 t( )

t

d )

vC1 t( ) VCC IC RC( ) 0.1 RC sin 2 1000 t

vC2 t( ) VCC IC RC( ) 0.1 RC sin 2 1000 t

0 0.001 0.002 0.003 0.004 0.0059

10

11

vC1 t( )

vC2 t( )

t

e )

0 0.001 0.002 0.003 0.004 0.0052

0

2

vC2 t( ) vC1 t( )

t

Other Non-Ideal Characteristics

Input Offset Voltage

Input Bias and Offset Currents

Exercise 6.4

100

Delta_RC 0.02 Delta_IS 0.1 Delta_ 0.1 I 100 A

From Eq. 6.55

VOS VTDelta_RC

RC

2Delta_IS

IS

2

VOS 25 0.02( )2

0.12 VOS 2.55

IBI

2 1 IB 0.495 A

IOS IBDelta_

IOS 4.95 104 50nA

Biasing In BJT Integrated Circuits

Many resistors, transistors and capacitors makes impossible to use conventional biasing methods

Biasing in IC is based on the use of constant-current sources

The Diode-Connected Transistor

i

i

1

1i

Shorting the base and the collector of a BJT results in a two-terminal device having an I-v characteristic identical ot the iE-vBE of the BJT.

Since the BJT is still in active mode (vCB=0 results in an active mode operation) the current I divides between base and collector according to the value of the BJT Beta.

Thus, the BJT still operates as a transistor in the active mode. This is the reason the I-v characteristics of the resulting diode is identical to the iE-vBE relationship of the BJT

i

Exercise 6.5

R incremental = r // (1/gm) // ro

Rinc

r1

gm

r1

gm

ro

r1

gm

r1

gm

ro

r

1ro

r

1ro

re rore ro

re Rinc25

0.5

Rinc 50

The Current Mirror

Io

IO

1IE IREF

2

1 IE

IO

IREF

2

1

12

I O

I REF

12

1V O V EE V BE

VA

Finite Beta and Early Effect

•For what value of would current mirror have a gain error 1%, 0.1 %

•Imperfection due to base current diverted from reference current IREF

Exercise 6.6

IO5 1.073 103IO5 IO

5 4.3( )Rout

VO 5at

IO 9.804 104IO

IREF

12

VO 4.3VO VEE VBEVO VBat

Rout 1 105Rout

100

IREF

Rout roVA

IREF

IREF 0.001 100VBE 0.7VEE 5

A Simple Current Source

I REF

VCC VBE

R

VCC

VBE

Neglecting the effect of finite beta and Dependence of Io and Vo, the output current Io will be equal IREF

IoIREF

Exercise 6.7

IO IREF IREF 0.001 VCC 5 VBE 0.7

neglect the effects ro and finite Beta 100 VA 50

roVA

IREF ro 5 10

4R

VCC VBE

IREF R 4.3 10

3

at VO 3 IO

IREF

12

VO VBE

ro IO 1.026 10

3

Current-Steering Circuits

Generation of a number of cross currents.

I REF

VCC VEE VEB1 VBE2

R

IC Circuits2 power suppliesIREF is generated in the branch of the diode-connected transistor Q1, resistor R, and the diode-connected transistor Q2.

Exercise 6.9

Comparison With MOS Circuits

1 - The MOS mirror does not suffer from the finite Beta2 – Ability to operate close to the power supply is an important issue on IC design3 - Current Transfer: BJTs ~ relative areas; MOS ~ W/L4 - VA lower for MOS

Improved Current-Source Circuits IREF

1

2

1 2

IE

IO

1IE

IO

IREF

1

12

2

1

12

2

IREF

VCC VEB1 VBE3

R

The Wilson Current Mirror

Output resistance equal

A factor greater the then simple

Current source

Disadvantage: reduced output swing.Observe that the voltage at the collector at Q3 has to be greater than the negative supply voltage by(vBB1 = VCEsat-3), which is about a volt.

ro2

Exercise 6.10

I EI E

I E

1

I E

1

2 I E

1

I E

1 I E

1

2

1I E

2

1 2I E

2

1 2I E

~

IREF

1

2

1 2

IE

IO 2

1 2IE

IO

IREF

2 2 2

IO

IREF

1

12

2

Widlar Current SourceIt differs from the basic current mirror in an important way: a resistor RE is included in the emitter lead of Q2. Neglecting the base current we can write:

VB1 VT lnIREF

IS

VB2 VT lnIO

IS

VB1 VB2 VT lnIREF

IO

VB1 VB2 IO RE

IO RE VT lnIREF

IO

Example 6.2

Example 6.3

Current sources for biasing amplifying stages

Multistage Amplifiers – Example 6.4 – pg. 552

Calculating 1st stage gain

-- Assuming

Model Eqs. on Pg. 263

er

In the same manor

k

rRi

05.5)25101(2

)1(22

542 rrRi

krrRid 2.2021

krrr e

1.10100*101))(1(21

10025.25

21 E

T

IV

ee rr

)()()( 1

E

T

C

T

m I

V

I

V

gr


Calculating 1st stage gain

VV

kk

rrRRR

RI

RI

vv

ee

i

RTotalEE

RTotalCC

id

oA

4.22200

40||05.5

)||(

1

21

212

__

__1

1Ri2

Total emitter resistance

Total collector resistance


Calculating 2nd stage gain

VVkk

rrRR

ee

iA 2.59508.234||3||

2 54

33

Ri3

re4 and re5 calc. before

Potential gain is halved b/c converting to single-ended output

))(1( 743 ei rRR

25125

7 C

T

IV

er

k

kRi

8.234

)253.2(1013


Calculating 3rd stage gain

Purpose is to allow amplified signal to swing negatively

Ri4

5525

8er

k

RrR ei

5.303)30005(101

))(1( 684

VV

kkk

RrRR

vv

e

i

o

oA 24.6325.25.303||7.15||

3 47

45

2

3


Calculating 3rd stage gain

VV

RrR

vv

eo

oA

998.30053000

4 68

6

3

Overall Gain

VV

vv AAAAAid

o 85134321

152)(|| 1865

R

eo rRROutput Resistance

The BJT Differential Amplifier With Active Load

vo gm vd Ro

Ro

ro2 ro4

ro2 ro4ro2 ro4 ro

Ro

ro

2vo gm vd

ro

2

vo

vd

gm ro

2

gm

IC

VTro

VA

ICIC

I

2

gm roVA

VT

constant for a given transitor

Ri 2 r Gm gm

I

2

VT

The Cascode Configuration

BJT Single Stage Common-Emitter Amplifier

http://jas2.eng.buffalo.edu/applets/education/ckt/comEmitAmp/index.html

MOSFET Operation

http://jas2.eng.buffalo.edu/applets/education/mos/mosfet/mosfet.html#saturation

MOS Differential Amplifiers – MOS Differential Pair

MOS Differential Amplifiers – Offset Voltage

MOS Differential Amplifiers – Current Mirrors

Problem 6.1

RC 3000 vBE 0.7 iC 0.001 vCM 2 VCC 5 100

at iC 0.0005 vBE 0.7 0.025ln0.5

1

vBE 0.683

vE vCM vBE vE 2.683

iC1

1iC iC1 4.95 10

4

vC1 VCC iC1RC vC1 3.515

Problem 6.15

Ad 40Advc2 vc1

vd

vc2 2vc2 ie RCvc1 2vc1 ie RC

iE2 6 104iE2 IE ie

iE1 1.4 103iE1 IE ie

ie 4 104ie

vd

2 re RE( )

RC 5000IE 0.001RE 100re 25vd 0.1

BJT Differential Amplifier Laboratory

PurposeThe purpose of this lab is to investigate the behavior of a BJT difference amplifier. The circuit’s behavior needs to be modeled with theoretical equations and a computer simulation. Comparison of laboratory results with theoretical and simulated results is required for the relative validity of the models. This lab also investigates the variation of differential and common mode gains using a Monte Carlo analysis.

ProcedureConstruct the circuit in Figure 1 on PSpice and a Jameco JE26 Breadboard using a Hewlett-Packard 6205 Dual DC Power Supply as the voltage sources and an MPQ2222 Bipolar Junction Transistor (Q2N2222).

Using a Keithley 169 Digital Multi-Meter measure the voltages across the resistors to determine the transistor base current and collector current. From these current values calculate .

Figure 1) Circuit for testing transistor value

Next construct the amplifier circuit shown in Figure 2. All transistors are MPQ2222 Bipolar Junction Transistors. Use PSpice to construct the circuit.

Measure the DC values at the collector of Q1 and Q2. Do the measured values agree with theoretical ones.

Measure the DC value at the emitter of Q1 and Q2. Do the measured value agree with the theoretical one.

Indicate the inverting and non-inverting output.

Input an AC signal into Q1 of your circuit at frequencies . What is the single voltage gain of your circuit?

Figure 2

Both inputs (Vin1 and Vin2) should be then grounded in order to determine the DC operating point of the amplifier. Bias point voltages are measured and then compared to the bias points produced by the PSpice simulation. Record DC bias point data. Use a Wavetek 190 Function Generator with a sinusoidal input voltage of amplitude 0.031 V and apply to one of the input terminals and the other terminal remained grounded, as shown in figure 2. Use a Tektronix TDS 360 Digital Oscilloscope and a Fluke 1900A Multi-Meter the output of the amplifier to observe input signal frequencies. Determine the corner frequency (3-dB point) of the output and compared with the corner frequency generated with an AC sweep in PSpice. Plot the PSpice AC sweep simulation. Next calculate the differential mode voltage gain, AV-dm, from the laboratory data and

compare to the AV-dm predicted by the PSpice simulation and theoretical equations. Both

inputs are tied together to create a common mode signal on the input terminals. The output voltage is then used to calculate the common mode voltage gain, AV-cm, and then

compared to the AV-cm predicted by the PSpice simulation and theoretical equations. From

these values the common mode rejection ratio (CMRR) should be calculated for each case. Finally, PSpice should be used to perform a Monte Carlo analysis of the circuit. The resistors were all given standard unbridged values and were allowed to vary uniformly within 5% of the nominal resistor value. The transistors should be given a nominal value (say 175) and allowed to vary uniformly to +/- 100. The variations of differential and common mode gains should be graphed on two histograms.

Analysis / Questions What are the values of for the first transistor? (typical values of range from approximately 125 to 225) With the exception of the Monte Carlo analysis, all transistors were assumed to have this value in the PSpice simulations. All four transistors were contained within one integrated circuit so that hopefully there would be little change in values from one transistor to the next, making the previous assumption reasonably valid. How close are the measured DC bias points of the circuit to those predicted by the PSpice simulation? What is the reason for the small differences between measured and predicted voltages?

Exercises 6.17

An Active-Loaded CMOS Amplifier

Exercise 6.19

BiCMOS Amplifiers

Exercise 6.20

BiCMOS Amplifiers

Exercise 6.21

BiCMOS Amplifiers

Exercise 6.22

BiCMOS Current Mirrors and Differential Amplifiers

Gallium Arsenide (GaAs) Amplifiers

Current sources – Exercise 6.23


A Cascode Current Source – Exercise 6.24


Increasing The Output Resistance by Bootstrapping


A Simple Cascode Configuration – The Composite Transistor


Differential Amplifiers

Multistage Amplifiers

Example 6.4

Multistage Amplifiers

Example 6.5 SPICE Simulation of a Multistage Amplifier

Chapter 6 Differential and Multistage Amplifiers The most widely used circuit building block in...

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Transcript of Chapter 6 Differential and Multistage Amplifiers The most widely used circuit building block in...