CHAPTER 5CHAPTER 555 Small Signal Intrinsic Equivalent Circuit Model...

Chapter 5: Small Signal Intrinsic...........

Pujarini Ghosh 135

CHAPTER CHAPTER CHAPTER CHAPTER 5555

Small Signal Intrinsic Equivalent Circuit Model of Small Signal Intrinsic Equivalent Circuit Model of Small Signal Intrinsic Equivalent Circuit Model of Small Signal Intrinsic Equivalent Circuit Model of

Cylindrical/Surrounded Gate MOSFET for Cylindrical/Surrounded Gate MOSFET for Cylindrical/Surrounded Gate MOSFET for Cylindrical/Surrounded Gate MOSFET for

Microwave Frequency ApplicationsMicrowave Frequency ApplicationsMicrowave Frequency ApplicationsMicrowave Frequency Applications

5.1. INTRODUCTION

Advancement in radio frequency integrated circuits (RFICs) in the last decade has

been driving a huge market for communications in various forms. These developments

have created a rapid expanding market for RFICs, which were previously dominated by

slow growing military and cable television industries [Lai07]. The technical requirements

imposed on these transceiver components were truly challenging. At the same time, the

consumer’s demand on low-cost, low-power and high-volume radio frequency devices

that were formerly implemented using bulky, expensive, and power-hungry hybrid

components were very large. Drawing an analogy to digital integrated circuit technology,

it appeared that the optimum technology choice for RFIC applications might follow the

same path that digital IC implementations followed towards the CMOS devices with the

costs dropping dramatically as the level of integration increases [Schmitz91]. The

MOSFETs used in digital CMOS have been successfully miniaturized to achieve higher

speed operation. Moreover, with scaling of the device dimensions into the sub-50 nm

regime, the transistors have achieved cut-off frequencies in the GHz regime, making

CMOS technology suitable for wireless communication and other RF applications

[Kilchytska03, Larson03, Saito98 & Yang02].


Pujarini Ghosh 136

The designing of analog and digital integrated circuits requires an authentic high

speed device model, which is an important tool to carry out high-speed digital

applications. A large-signal model [Collantes95 & Ho97] should be used which will describe

the active device over the whole operating frequency range. The most suitable method to

examine a MOSFET at high frequencies involves S-parameter measurements [Curtice84].

For the characterization of the broadband behaviour of a device, measurements have to be

performed at different bias, as the electrical properties of a MOSFET strongly depend on

the applied gate bias and drain to source bias and also the frequency range of interest over

which it measured. Using an equivalent circuit consisting of different intrinsic circuit

elements, S-parameters were evaluated in-terms of fifteen frequency impendent variables.

Several commercially available programs such as MATLAB, MATHCAD, numerical

methods, simulated methods etc. were present to optimize some of or all of these

parameters [Nagatomo93]. Although in general the measured S-parameter approximated by

these methods and the resulting element values may differ considerably from their actual

physical values [Curtice84, Nagatomo93 & Lin94]. The analytical methods [Rorsman96,

Dambrine98, Berroth90 & Minasian77] on the other hand allow to extract the equivalent

circuit parameters in a straightforward manner. The most favourable extraction method

was originally proposed by Minasian [Minasian77] and was later modified by Dambrine

et.al [Dambrine98], and Berroth & Bosch [Berroth90]. In this method the series and shunt

parasitic elements of the device were first extracted by measuring the S-parameters under

suitable passive modes of its operation. Once these parasitic elements are carefully

determined, the S-parameters are then measured under active mode of device operation.

These are then successively transformed into Z (Impedance) parameters and Y

(Admittance) parameters.

In the analysis presented in this chapter, a similar equivalent circuit model has been

applied for CGT/SGT MOSFET [Ghosh12a & Auth97] then Y parameters are analytically

calculated from the equivalent circuit and then the (Scattering) S-parameters are

extracted. The advantage of CGT/SGT MOSFET is that it allows excellent control of the

charges over the channel thus minimizing the scaling limitations caused due to the short

channel effects (SCEs), thereby, increasing the device performances. In CGT/SGT


Pujarini Ghosh 137

MOSFET the source, drain and gate are arranged vertically and the sidewalls of the pillar

are used as the channel region due to which the structure has a large effective channel

width even in a small-occupied area. As a result, the channel length can be adjusted

without changing the occupied area of the MOSFET resulting in high packing density

Due to high packing density and immunity against short channel effects the CGT/SGT

MOSFET has become the main point of interest in this analysis for studying CGT/SGT

MOSFET behaviour at broad frequency range.

Admittance parameters (Y-parameters) of CGT/SGT MOSFET were evaluated

using the analysis of small signal equivalent circuit. Scattering parameters (S-parameters)

and power gains such as maximum stable gain, unilateral power gain and maximum

unilateral transducer power gain [Ghosh12b] were then evaluated over the frequency range

of interest. The different power gains of CGT/SGT MOSFET were compared with bulk

MOSFET and it was found that CGT/SGT MOSFET were better as compared to bulk

MOSFET due to its cylindrical profile; hence the CGT/SGT MOSFET had better

efficiency. A good agreement is obtained between model and simulated data which

validate the theoretical analysis.

5.2. ANALYTICAL MODELING

5.2.1. Unified Charge Control Model

The structure of CGT/SGT MOSFET considered in the analysis is shown in the Fig. 5.01.

Better electrostatic control has been obtained in CGT/SGT MOSFET due to which the

short channel effects associated to gradual channel approximation can be neglected.

Hence, the electrostatic behaviour of the CGT/SGT MOSFET has been described by 1D

Poisson’s equation in the radial direction.

In a lightly doped CGT/SGT MOSFET, using Poisson’s equation the potential

distribution in the silicon pillar takes the form as

2

2

( )1

Vqd d k T k Te

R d r qd r

ψψ ψ

δ

−

+ =

(5.01)

where


Pujarini Ghosh 138

2

( )

q ni

kTsi

δε

= (5.02)

q (1.6 x 10-19

C) is the electronic charge, R is the radius of the cylinder, in (1.45 x 1016

cm-3

) is the intrinsic carrier concentration, siε (11.7εo) is the relative permitivity of silicon

(εo=8.85x 10-12

), V is the electron quasi fermi potential, k is the Boltzman s’ constant.

Fig. 5.01 Cross sectional view of Cylindrical/Surrounded gate MOSFET. tox = 2.5nm, R=10nm, L=50nm,

Фm=4.8eV, ND+=5 x 10

19 cm

-3, NA=10

16 cm

-3, Vgs=0.5V & 1V and Vds=0.5V unless stated otherwise.

Equation (5.01) is solved subjected to the following boundary conditions:[Jiménez04b]

( 0) 0d

rdr

ψ= =

(5.03)

( ) sr Rψ ψ= = (5.04)

where R is the radius of the device and s

ψ is the surface potential.

The well known solution for the differential equation (5.01) is [Jiménez04a]

2 1( ) 2 ln

Brr A kT

qψ

+= −

(5.05)

where A and B are the constants and are related as, [Jiménez04a]

8ln

BkT

Aq

δ

− = (5.06)


Pujarini Ghosh 139

substituting (5.06) in (5.05) the electrostatic potential ( )rψ in radial direction is obtained

as

( )2

2

8( ) ln

1

kT Br

q Brψ

δ

− =

+

(5.07)

Consider the current flow in the channel direction only. V, electron quasi fermi potential

is assumed to be constant along the radial direction, thus (5.07) becomes

( )2

2

8( ) ln

1

kT Br V

q Brψ

δ

− = +

+

(5.08)

The mobile sheet charge density controlled by gate electrode is given as:

( )ox gs m sQ C V φ ψ= − ∆ − (5.09)

where

ln 1

oxox

ox

Ct

RR

ε=

+

(5.10)

mφ∆ is the workfunction difference between the gate electrode and intrinsic silicon.

Gauss s’ Law at r=R is expressed as,

si

r R

dQ

dr

ψε

=

= (5.11)

differentiating (5.08) and using (5.11) the mobile sheet charge can also be expressed as,

2

4

( 1)

sikTBR

Qq BR

ε−=

+ (5.12)

Thus equating (5.09) and (5.12)

( )2

gs m s

q BRV

kT

ηφ ψ

β

−− ∆ − = (5.13)

where

4si

oxC R

εη = and (5.14)

21 BRβ = + (5.15)


Pujarini Ghosh 140

also, at r=R (5.08) becomes

2

8lns

kT BV

qψ

δβ

−= +

(5.16)

substituting (5.16) in (5.13)

( ) ( ) ( )( )2

2

18ln ln 1 ln

gs m

qV V

kT R

βφ β β η

δ β

− − ∆ − − = − − +

(5.17)

β can be solved from (5.17) as a function of V. Where V is the channel potential, varies

V=0 at the source end to V=Vds at the drain end.

Rewriting (5.12), Q in terms of β is expressed as,

0

1Q Q

β

β

−=

(5.18)

where 0

4si

kTQ

qRε= (5.19)

The drain current in SGT/CGT MOSFET is calculated using unified charge model

[Iñiguez05] given below

2ds

dVI R Q

dzπ µ= (5.20)

where µ the effective mobility of the electrons,

integrating (5.20) and taking the limits from 0 to Vds

2dsI dz R QdVπ µ=∫ ∫ (5.21)

Drain current in terms of β is obtained as

( )2( )

D

Sds

R dVI Q d

L d

β

β

π µβ β

β

=

∫ (5.22)

where L is the channel length, Sβ and Dβ are values of β at the source end and the drain

end respectively.

dV

dβis obtained by differentiating (5.17)

2

1 2

1

dV kT

d q

η

β β β β

= + +

− (5.23)


Pujarini Ghosh 141

Putting (5.23) and (5.18) in (5.22), drain current is obtained as

( ) ( )

( ) ( )

2 22

2 2

4 12 1 ln4 2 2

D Ssi D S Sds

D S DD S

kTIL q

β βπµε β β βη η

β β ββ β

− − = + − +

………………………………...(5.24)

5.2.2. Capacitance Model

The total charge is obtained by integrating the mobile charge sheet density over the

channel length

20

L

Q R Q d zT o l π= − ∫ (5.25)

Electric field is represented as dV

Edz

=

(5.20) becomes,

2

ds

R QdVdz

I

π µ= (5.26)

replacing dz in (5.25) and changing the limits of integration from 0-L to 0-Vds

2 2(2 )

0

ds

ds

VQ R Q dV

Tol I

µπ= − ∫ (5.27)

QTol in terms of β can be obtained using (5.23) as,

2 2

2

1 2(2 ) ( )

1

D

dsS

kTQ R Q d

Tol qI

β ηµπ β β

β β ββ

= − + +∫

− (5.28)

Integrating (5.28),

3 2 3 2

3 1 3 1

3 3D S

D SD D S S

QTol

η η η η η ηα β β

β ββ β β β

− + − += − + + − + − −

(5.29)

Where α

2 2 3 3

3

64 si

ds

k T

I q

π ε µα

−=

(5.30)

Now, the total gate charge is given by


Pujarini Ghosh 142

g Tol oxQ Q Q= − − (5.31)

where oxQ is the total oxide fixed charge. Neglecting oxQ in comparison to TolQ ,

3 2 3 2

3 1 3 1

3 3g D S

D SD D S S

Qη η η η η η

α β ββ ββ β β β

− + − += − − + + − + − −

(5.32)

The intrinsic capacitances Cgs and Cgd are defined respectively as [Liu09]

g

gs

s

dQC

dV= − (5.33)

and

g

gd

d

dQC

dV= − (5.34)

From (5.33)

g sgs

s s

dQ dC

d dV

β

β= − (5.35)

from (5.23) s

s

d

dV

β at the source is given as,

2

1 2

1

s

s s s s

dV kT

d q

η

β β β β

= + +

− (5.36)

differentiating (5.32) with respect tos

β ,

( )2 3 4

2 11 3g

s s s s s

dQ

d

ηη ηα

β β β β β

− −= + + +

(5.37)

combining (5.36) and (5.37) gs

C is obtained as,

( ) ( )2 3 4

1 2

21

3 2 11gs

kTs s s s

qs s s

Cη

β β β

η ηα η

β β β β + + −

− − = − + + −

(5.38)

In exactly similar way using (5.23), (5.32) and (5.34), gate drain capacitance gd

C is

obtained as,


Pujarini Ghosh 143

( )2 3 4

1 2

21

2 11 3gd

kTd d d d

qd d d

Cη

β β β

ηα η η

β β β β + + −

− −= + + +

(5.39)

5.3. MODEL FORMULATION

5.3.1. Admittance Parameters

The intrinsic small signal equivalent circuit of CGT/SGT MOSFET used in the analysis

is shown in Fig. 5.02 comprised of intrinsic elements. Using network analysis

techniques, the Y parameters for the simplified circuit model can be derived and

expressed in terms of intrinsic small signal parameters [Berroth90]

Fig. 5.02. Small signal equivalent circuit of Cylindrical/Surrounded gate MOSFET.

Using nodal analysis the current I1 at input port and current I2 at output port are evaluated

as fellows

211 iiI += (5.40)

2 5 4 3 2I i i i i= + + − (5.41)

therefore, I1 can be obtained as,


Pujarini Ghosh 144

( )1 211

1 1i gd

gs gd

V VVI

R Rj C j Cω ω

−= +

+ +

(5.42)

where 2 fω π= ; f is the frequency of operation.

Further rationalizing (5.42)

( ) ( )( )1 1 2

1( 1) (1 )

gs gd gd

gs i gd gd

V j C V V j C RI

j C R j C R

ω ω

ω ω

−= +

+ + (5.43)

similarly I2 can be obtained as,

( )1 222 21 1d m

gddsgd

V VVI V g Y

Rj Cj C

ωω

−= + + −

+ (5.44)

where, exp( )m gs mY V g jωτ= − (5.45)

Vgs is the voltage drop at Cgs.

By applying voltage divider rule at Cgs

1

1

1

1 1

gs

gs

i gsi

gs

Vj C V

VR j C

Rj C

ω

ωω

= =++

(5.46)

substituting (5.45) and (5.46) in (5.43),

( )( )( )1 21

2 2 2 exp1 1

gd

ds d mgs i gd gd

V V j CVI V j C V g g j

j C R j C R

ωω ωτ

ω ω

−= + + − −

+ + (5.47)

The different Y- parameters can now be evaluated as follows:

(A) Y11, is the input admittance parameter, which is the ratio of the current at input

port to the voltage at input port when the output port is short circuited

2

111

1 0V

IY

V=

= (5.48)

From (5.43) making V2=0


Pujarini Ghosh 145

1

1 (1 ) (1 )

gs gd gd

gs i gd gd

j C j C RI

V j C R j C R

ω ω

ω ω= +

+ + (5.49)

rationalizing (5.49)

2 2 2 2 2

11gs gs i gd gd gdj C C R C R j C

YD D

ω ω ω ω+ += +

′ (5.50)

where,

2 2 21 i gsD R Cω= + (5.51)

2 2 21 gd gdD R Cω′ = + (5.52)

since gdR is very small (5.50) can be simplified as,

2 2

11gs i gs

gd

C R CY j C

D D

ωω

= + +

(5.53)

(B) Y12, is the reverse transfer admittance parameter, which is the ratio of current at

input port to the voltage at output port when input port is short circuited

1

112

2 0V

IY

V=

= (5.54)

putting V1=0 in (5.43)

( )12

(1 )

gd gd

gd gd

j C RY

j C R

ω

ω= −

+ (5.55)

rationalizing (5.55)

2 2

12gd gd gdj C C R

YD D

ω ω−= −

′ ′ (5.56)

neglecting gdR , Y12 becomes,

12 gdY j Cω= − (5.57)

(C) Y21, is the forward transfer admittance parameter, which is the ratio of current

at the output port to the voltage at input port when output port is short circuited


Pujarini Ghosh 146

2

221

1 0V

IY

V=

= (5.58)

substituting V2=0 in (5.47)

21

exp( )

1 1

gdm

gs i gd gd

j Cg jY

j C R j R C

ωωτ

ω ω

−= −

+ + (5.59)

neglecting Rgd, Y21 becomes

21

exp( )

1

mgd

gs i

g jY j C

j C R

ωτω

ω

−= −

+ (5.60)

(D) Y22, is the output admittance parameter, which is the ratio of current at the

output port to the voltage at output port when the input port is short circuited

1 0

222

2 V

IY

V=

= (5.61)

substituting V1=0 in (5.47)

( ) ( )

2 2

22 2 2 2 2 2 21 1

gd gd gdds d

gd gd gd gd

j C C RY j C g

C R C R

ω ωω

ω ω= + + +

+ + (5.62)

which on simplification gives,

2 2

22gd gd gd

d ds

C C RY g j C

D D

ωω

= + + + ′ ′

(5.63)

on neglecting Rgd the Y22 becomes

22 ( )d ds gdY g j C Cω= + + (5.64)

Fig. 5.03, Fig. 5.04, Fig 5.05 and Fig. 5.06 show the variation of real and imaginary part

of input admittance Y11, the reverse transfer admittance Y12, forward transfer admittance

Y21 and output admittance Y22 respectively as a function of frequency evaluated using

above proposed model for CGT/SGT MOSFET. The results shown are also compared

with the work by Cho et.al. [Cho11] and found to be in good agreement.


Pujarini Ghosh 147

0

2

4

6

8

10

12

14

0 50 100 150 200Frequency (GHz)

Y11 (

uS

)

Imaginary Y11

∆ Real Y11

Line =Model

Symbol=[Cho11]

Fig. 5.03. Real and Imaginary part of Y11 of CGT/SGT MOSFET as a function of frequency at Vgs=1V,

Vds=0.5V, L=30nm, R=5nm and tox=3.5nm.

-2.5

-2

-1.5

-1

-0.5

0

0.5

0 50 100 150 200Frequency (GHz)

Y12(u

S)

Imaginary Y12

∆ Real Y12

Line= Model

Symbol=[Cho11]

Fig. 5.04. Real and Imaginary part of Y12 of CGT/SGT MOSFET as a function of frequency at Vgs=1V,

Vds=0.5V, L=30nm, R=5nm and tox=3.5nm.


Pujarini Ghosh 148

-10

10

30

50

0 50 100 150 200Frequency (GHz)

Y21 (u

S)

Imaginary Y21

∆ Real Y21

Line =Model

Symbol=[Cho11]

Fig. 5.05. Real and Imaginary part of Y21 of CGT/SGT MOSFET as a function of frequency at Vgs=1V

and Vds=0.5V. L=30nm, R=5nm and tox=3.5nm.

0

5

10

15

20

25

0 50 100 150 200Frequency (GHz)

Y22 (

uS

) ImaginaryY22

∆ Real Y22

Line =Model

Symbol=[Cho11]

Fig. 5.06. Real and Imaginary part of Y22 of CGT/SGT MOSFET as a function of frequency at Vgs=1V

and Vds=0.5V. L=30nm, R=5nm and tox=3.5nm.

5.3.2. Transconductance and Drain Conductance

The transconductance gm and drain conductance gd are defined as

constantds

dsm

gsV

dIg

dV=

=

(5.65)


Pujarini Ghosh 149

constantgs

dsd

gdV

dIg

dV=

=

(5.66)

Unity gain frequency (cut-off frequency) ft is the figure of merit which is defined as the

frequency at which the current gain of the device becomes unity (0dB). The value of fT is

approximated as

( )2

mT

gs gd

gf

C Cπ=

+ (5.67)

The transit time,τ is defined as the time taken by the electrons to cross the channel

length in the velocity-saturated region and it determines the speed of the device [Chen94],

is given by

1

2t

fτ

π= (5.68)

5.3.3. Scattering Parameters

Scattering implies causing something to separate into different components, and

scattering parameters provide a measure of the degree of separation and the magnitudes

of the different components. At low frequencies, the Z (open circuit impedance

parameter), Y (short circuit admittance parameter), h (hybrid parameter) and ABCD

(cascade) parameters are used to describe input output relation of two-port networks.

These parameters cannot be measured accurately at higher frequencies as the required

short-and open-circuit tests are difficult to achieve over a broadband range of microwave

frequencies. A set of parameters that is very useful in microwave range are the scattering

parameters (S parameters) [Guy98 & Lee00]. These parameters are defined in terms of

traveling waves and completely characterize the behavior of two-port networks at

microwave frequencies [Liao87].

The scattering concept is more difficult to visualize when the incident and reflected

component do not actually exist and is true for a transistor connected to its load through a

lumped matching network [Carson75 & Vendlin82]. Therefore it is necessary to define what

is meant by incident and reflected components because they cannot be identified. When


Pujarini Ghosh 150

the scattering concept is applied to lumped circuits, the actual currents and voltages can

be separated into scattered components.

Therefore

1 1 1i rV V V= + (5.69)

2 2 2i rV V V= + (5.70)

At this point new variables are defined as follows

1 11 1

0 0

i rV V

a bZ Z

= = (5.71)

2 22 2

0 0

i rV V

a bZ Z

= = (5.72)

where 0Z (50Ω) is the characteristics impedance of the transmission line. At port 1

1a represents the incident wave and 1b the reflected wave. Similarly, at port 2, 2a

represents the incident wave and 2b the reflected wave. The S parameters can now be

defined by the following relationship among these new variables [Vendlin82]

1 11 1 12 2b S a S a= + (5.73)

2 21 1 22 2b S a S a= + (5.74)

or in the matrix form,

1 11 12 1

2 21 22 2

b S S a

b S S a

=

(5.75)

where

Two Port Network

Input port Output Port

Port 1 Port 2

a1 a2

b1 b2

Fig. 5.07. Two Port Network

V1 V2

+ +

- -


Pujarini Ghosh 151

2

111

1 0a

bS

a=

= is the input reflection coefficient with the output matched

1

112

2 0a

bS

a=

= is the reverse transmission coefficient with the input matched

2

221

1 0a

bS

a=

= is the forward transmission coefficient with the output matched

1

222

2 0a

bS

a=

= is the output reflection coefficient with the input matched

Input or output ports are considered to be matched when it is terminated by the

characteristics impedance, Zo.

These are called scattering parameters as the reflected wave “b” can be thought of as

being “scattered” by the device from the incoming wave “a”.

The analysis of CGT/SGT MOSFET has been carried out for a channel length L=50 nm,

device radius R=10 nm, oxide thickness tox=2.5 nm, uniformly doped source/drain region,

ND+ with doping density of 5x10

19 cm

−3, p type substrate, NA with a doping density of

1016

cm−3

, the metal gate work function (Фm) is 4.8 eV and drain-to-source voltage

Vds=0.5V unless stated otherwise. The analytical results are compared with the simulated

results of ATLAS 3D device simulator [ATLAS10] at various gate biases and then

compared with the bulk MOSFET at channel length L=50 nm, width W=1µm and gate

oxide thickness tox=2.5 nm.

The S-parameters have been evaluated in terms of intrinsic Y-parameters by using

transformation given in [Ramo93] and are given below

The S-parameters, thus evaluated and expressed as

• The input reflection scattering coefficient ( 11S ) is obtained as

211 22 12 21

11

(1 )(1 )o o oZ Y Z Y Z Y YS

− + +=

∇ (5.76)

• The reverse transmission scattering coefficient ( 12S ) is obtained as

1212

2( )oZ YS

−=

∇ (5.77)


Pujarini Ghosh 152

• The forward transmission scattering coefficient ( 21S ) is obtained as

2121

2( )oZ YS

−=

∇ (5.78)

• The output reflection scattering coefficient ( 22S ) is obtained as

211 22 12 21

22

(1 )(1 )o o oZ Y Z Y Z Y YS

+ − +=

∇ (5.79)

where 211 22 12 21(1 )(1 )o o oZ Y Z Y Z Y Y∇ = + + − (5.80)

and oZ characteristics impedance at each port is assumed to be 50 Ω. 50 Ω impedance

was selected from a trade off between the lowest loss and maximum power handling

capabilities in microwave devices [Golio08].

0.9

1

1.1

1 10 100 1000Frequency (GHz)

Re (

S11)

0.5V

1V

Vds=0.5V

Vgs

Lines Model

Symbols Simulated

Fig. 5.08. Real part of input reflection coefficient Re [S11] as a function of frequency for CGT/SGT

MOSFET.

Fig.5.08 to Fig.5.23 show the variations of S-parameters (S11 Input reflection coefficient,

S12 Reverse transmission Coefficient, S21 Forward transmission Coefficient and S22 output

reflection coefficient) both in real and imaginary form as a function of frequency ranging

from 1 GHz to 1000 GHz range. These parameters which have been evaluated

analytically using intrinsic equivalent circuit model are then compared with the results

obtained from 3-D device simulation at low gate bias of Vgs=0.5V & a high gate bias of


Pujarini Ghosh 153

Vgs=1V and at a drain bias of Vds=0.5V. A good agreement is obtained between the

simulated and analytical results for both the gate bias.

-120

-100

-80

-60

-40

-20

0


Im (

S11)

X 1

0-5

0.5V

1V

Lines Model

Symbols Simulated

Vgs

Fig. 5.09. Imaginary part of input reflection coefficient Im [S11] as a function of frequency for

CGT/SGT MOSFET

0.84

0.86

0.88

0.9

0.92

0.94

0.96

0.98

1

1.02


Re

(S

11)

MOSFET="0.5V"

CGT/SGT="0.5V"

MOSFET="1V"

CGT/SGT="1V"

Vgs

Vds=0.5V

Fig. 5.10. Real part of input reflection coefficient Re [S11] as a function of frequency for CGT/SGT and

a comparison with Bulk MOSFET.


Pujarini Ghosh 154

-0.3

-0.25

-0.2

-0.15

-0.1

-0.05

0


Im (

S 11)

MOSFET="0.5V"MOSFET="1V"

CGT/SGT="0.5V"CGT/SGT="1V"

Vgs

Vds

=0.5V

Fig. 5.11. Imaginary part of input reflection coefficient Im [S11] as a function of frequency for

CGT/SGT MOSFET and a comparison with Bulk MOSFET.

Fig.5.08 and Fig.5.09 show the variation of real and imaginary part of input reflection

coefficient as a function of frequency respectively for CGT/SGT MOSFET. And Fig.5.10

and Fig.5.11 shows the comparison between the bulk-MOSFET and CGT/SGT MOSFET

in terms of real and imaginary input reflection coefficients.

0

300

600

900

1200

1500

1800


Re (

S12)

x 1

0-8

0.5V

1VVgs

Vds=0.5V

Lines Model

Symbols Simulated

Fig. 5.12. Real part of Reverse transmission coefficient Re[S12] as a function of frequency for

CGT/SGT MOSFET.


Pujarini Ghosh 155

0

5

10

15

20

25


Im (

S12)

x 1

0-5

0.5V

1V

Lines Model

Symbols

Simulated

Vds=0.5V

Vgs

Fig. 5.13. Imaginary part of reverse transmission coefficient Im [S12 ] as a function of frequency for

CGT/SGT MOSFET.

0

0.005

0.01

0.015

0 250 500 750 1000

Frequency (GHz)

MO

SF

ET

Re

(S

12)

0

400

800

1200

1600

2000

CG

T/S

GT

Re

(S12 ) x

10

-8

MOSFET

MOSFET

CGT/SGT

CGT/SGT

Vgs=1V

Vgs=0.5V

Vds=0.5V

Fig. 5.14. Real part of Reverse transmission coefficient Re[S12] as a function of frequency for CGT/SGT

MOSFET and a comparison with Bulk MOSFET.

Fig. 5.12 and Fig. 5.13 show the variation of real and imaginary part of Reverse

transmission coefficient as a function of frequency for CGT/SGT MOSFET. A

comparison between the bulk-MOSFET and CGT/SGT MOSFET in terms of real and

imaginary reverse transmission coefficients is also shown in Fig.5.14 and Fig.5.15. From

the figure it is analyzed that both real and imaginary reverse transmission coefficient for


Pujarini Ghosh 156

CGT/SGT MOSFET is very less as compared to bulk one, which is more desirable for

better device performances because of better power gain. And a good matching between

the analytical and simulated data validates the model.

0

1

2

3

4

5

6

7

0 500 1000Frequency (GHz)

MO

SF

ET

Im

(S

12)x

10

-2

0

5

10

15

20

25

CG

T/S

GT

Im (S

12 ) x

10

-5

/∆ Vgs=1V

/ Vgs=0.5V

Fig. 5.15. Imaginary part of reverse transmission coefficient Im [S12] as a function of frequency for


-50

-40

-30

-20

-10

0


Re

(S21)

x 1

0-5

0.5V

1V

Vgs

Lines Model

Symbols

Simulated

Vds=0.5V

Fig. 5.16. Real part of forward transmission coefficient Re [S21] as a function of frequency for CGT/SGT

MOSFET.


Pujarini Ghosh 157

0

10

20

30

40

50

60

1 10 100 1000

Frequency (GHz)

Im (

S21)

x 1

0-5

0.5V

1V

Lines Model

Symbols Simulated

Vds=0.5V

Vgs

Fig. 5.17. Imaginary part of forward transmission coefficient Im[S21] as a function of frequency for

CGT/SGT MOSFET.

-15

-12

-9

-6

-3

0


MO

SF

ET

R

e (S

21)x

10

-2

-47

-32

-17

-2

13

CG

T/S

GT

Re (S

21 )x

10

-5

Vgs=0.5V

Vgs=1V

∆ / CGT/SGT MOSFET

/ MOSFET

Vds=0.5V

Fig. 5.18. Real part of forward transmission coefficient Re [S21] as a function of frequency for CGT/SGT


Fig.5.16 and Fig.5.17 show the variation of real and imaginary part of forward

transmission coefficient with respect to frequency for CGT/SGT MOSFET. A

comparison between the bulk-MOSFET and CGT/SGT MOSFET in terms of real and

imaginary forward transmission coefficient as a function of frequency is also shown in


Pujarini Ghosh 158

Fig.5.18 and Fig.5.19. From the figure reasonably good matching between the model and

simulated data is observed which validates the model.

0

5

10

15

20


MO

SFE

T Im

(S

21)x

10

-2

0

20

40

60

CG

T/S

GT Im

(S21 ) x

10

-5

/ MOSFET

/∆ CGT/SGT

Vgs=0.5V

Vgs=1V

Fig. 5.19. Imaginary part of forward transmission coefficient Im[S21] as a function of frequency for


0.99

1

1.01


Re

(S

22)

0.5V

1VVgs

Vds=0.5V Lines Model

Symbols Simulated

Fig. 5.20. Real part of output reflection coefficient Re[S22] as a function of frequency for CGT/SGT

MOSFET.

Fig.5.20 and Fig.5.21 show the variation of real and imaginary part of output reflection

coefficient as a function of frequency for CGT/SGT MOSFET. A comparison between


Pujarini Ghosh 159

the bulk-MOSFET and CGT/SGT MOSFET in terms of real and imaginary output

reflection coefficient is also shown in Fig.5.22 and Fig.5.23.

-20

-18

-16

-14

-12

-10

-8

-6

-4

-2

0


Im (

S22)

x 1

0-5

0.5V

1VVgs

Lines Model

Symbols Simulated

Vds=0.5V

Fig. 5.21. Imaginary part of output reflection coefficient Im[S22] as a function of frequency for

CGT/SGT MOSFET.

0.96

0.97

0.98

0.99

1

1.01


Re

(S

22)

0.5V0.5V1V1V

CGT/SGT MOSFET

Vgs

MOSFET

Vds=0.5V

Fig. 5.22. Real part of output reflection coefficient Re[S22] as a function of frequency for CGT/SGT



Pujarini Ghosh 160

-9

-7

-5

-3

-10 300 600 900

Im (

S22)

x 1

0-2

-30

-20

-10

Frequency (GHz)

Im (S

22 ) x

10

-5

/ 0.5V

/∆ 1V

MOSFET

CGT/SGT

Fig. 5.23. Imaginary part of output reflection coefficient Im[S22] as a function of frequency for


5.4. Power gains

Power gains play an important role in design of an amplifier in microwave frequency

range. Several definitions of power gains are important for the design of amplifiers.

5.4.1. Unilateral Power gain (UT)

Unilateral Power Gain (UT ) is the only device characteristic that is invariant under

lossless reciprocal embeddings and can be used as a figure of merit to compare any three-

terminal, active device. If UT is greater than one, the two-port device is active; otherwise,

that device is passive. This is especially relevant to microwave engineers since UT is

usually slightly greater than or equal to unity, in the microwave frequency range. It is the

highest possible gain that an active port can achieve. Unilateral power gain determines

the high power and high gain capability of the device.

Unilateral power Gain (UT) is expressed as [Ladbrooke89].

21

12

21 21

12 12

212

1

Re

S

S

T S S

S S

UK

−=

−

(5.81)

where K is stability factor defined as


Pujarini Ghosh 161

2 2 2

11 22

12 21

1

2

S SK

S S

+ ∆ − −= (5.82)

where

11 22 12 21S S S S∆ = − (5.83)

-10

0

10

20

30

40

50

60

70

0 200 400 600 800 1000Frequency(GHz)

Un

ila

tera

l P

ow

er

Ga

in (

dB

)0.5V

1V

Vgs

Lines Model

Symbols

Simulated

Vds=0.5V

Fig. 5.24. Variation of Unilateral Power gain (UT) (in dB) as a function of frequency for CGT/SGT

MOSFET.

K is the stability factor which determines the stability of the device or its resistance to

oscillations. K>1 and ∆ <1 forms the primary condition for the device to be stable.

Higher is the frequency upto which the device is stable (i.e. K>1), greater is suitability of

the device for RF and Low noise amplifier devices. The frequency at which the unilateral

power gain becomes unity (0dB) is known as maximum frequency of oscillation.

Fig. 5.24 shows the variation of Unilateral power gain (UT) as a function of frequency for

CGT/SGT MOSFET at channel length L=50 nm. At a constant drain bias Vds=0.5V and

gate bias of Vgs=0.5V & Vgs=1V. Unilateral power gain is obtained using (5.81). From the

figure, it is observed that there is an exponential decrease in the unilateral power gain as

the frequency increases. By extrapolating the curve of unilateral power gain fmax is

obtained, which comes out to be around 700 GHz. A good matching between the

simulated results with the analytical data validates the model.


Pujarini Ghosh 162

5.4.2. Maximum Stable power gain (Gms) [Goswami00 & Goswami01]

Maximum stable power gain, Gms is defined as

21

12

SGms

S= (5.84)

This is the gain that can be achieved by resistively loading the two-port network such that

the stability factor (K) is unity and then simultaneously matching the input and output

ports.

Fig. 5.25 indicates the variation of Maximum stable power gain (Gms) with respect to

frequency upto 1 THz for CGT/SGT MOSFET at channel length, L=50 nm at Vds=0.5V

and gate bias of Vgs=0.5V & Vgs=1V. Maximum stable power gain, Gms is an important

parameter used for designing low noise amplifier (LNA). From the figure it is analysed

that highest Gms value is obtained at 30 dB; and even at frequency of 1000 GHz Gms

have a value above 0 dB, which is only due to the better matching at input and output

ports. Thus, a simultaneous conjugate match has been obtained in the analysis. A good

agreement between the analytical model and simulated data is obtained.

0

10

20

30

0 200 400 600 800 1000

Frequency (GHz)

Maxim

um

sta

ble

Pow

er

Gain

(G

ms)

(dB

)

0.5V

1V

Lines Model

Symbols Simulated

Vds=0.5V

Vgs

Fig. 5.25. Variation of Maximum Stable power gain (Gms) (in dB) as a function of frequency for

CGT/SGT MOSFET.


Pujarini Ghosh 163

5.4.3. Maximum unilateral Transducer power gain ( maxTUG ) [Goswami00 &

Ladbrooke89]

Maximum unilateral transducer power gain is defined as

( )( )

2

21max 2 2

11 221 1TU

SG

S S=

− − (5.85)

Fig 5.26 anticipates the variation of Maximum unilateral Transducer power gain (GTUmax)

as function of frequency upto 1 THz range for CGT/SGT MOSFET at a channel length,

L=50 nm at Vds=0.5V and gate bias of Vgs=0.5V & Vgs=1V. The Maximum Unilateral

Transducer Power Gain (GTUmax) is obtained when the source reflection coefficient, sΓ is

adjusted as *11s SΓ = and the load reflection coefficient, LΓ is adjusted as *

22L SΓ = . From

the figure it is observed that at 1000 GHz maximum unilateral transducer power gain

have value above 0dB which predicts better matching between the input and output ports.

This is given by the (5.85). At lower frequencies maximum unilateral transducer power

gain is obtained at 50-70 dB. A good matching between the analytical results and

simulated values validates the model.

0

10

20

30

40

50

60

0 200 400 600 800 1000

Frequency (GHz)

Max U

nila

tera

l Tra

nsducer

Pow

er

gain

(dB

)

0.5V

1V

Lines Model

Symbols Simulated

Vds=0.5V

Vgs

Fig. 5.26. Variation of Maximum unilateral transducer power gain (GTUmax) (in dB) as a function of

Frequency CGT/SGT MOSFET.


Pujarini Ghosh 164

-5

5

15

25

35

45

0 2 4 6 8 10Frequency (GHz)

Diff

ere

nt G

ain

s (

dB

)

Solid symbols= MOSFET [Gosw ami00]

Hollow Symbols=CGT/SGT MOSFET

Unilateral Power Gain

Maximum Unilateral

transducer Power Gain

♦♦♦ Maximum Stable Power Gain

Fig. 5.27. Variation of different gains with frequency for both MOSFET and CGT/SGT MOSFET at L=

0.8 µm and Vds=3V.

Fig. 5.27 predicts the variation of different gain namely unilateral power gain, maximum

unilateral transducer power gain and maximum stable gain as a function of frequency for

both MOSFET and CGT/SGT MOSFET at L=0.8 µm. From the figure, it is analyzed

that all the gains are higher for CGT/SGT MOSFET as compared to bulk MOSFET; this

is due to the better gate controllability over the channel obtained using

Cylindrical/Surrounded architecture and hence improves the efficiency. Therefore,

CGT/SGT MOSFET is a useful device for microwave frequency applications.

5.5. Conclusion

An intrinsic circuit model for CGT/SGT MOSFET has been proposed from where

microwave characteristics in terms of scattering parameters (S11 Input reflection

coefficient, S12 Reverse transmission Coefficient, S21 Forward transmission Coefficient

and S22 output reflection coefficient) and power gains in terms of unilateral power gain,

Maximum Unilateral transducer power gain and maximum stable gain have been

obtained. The results so obtained using the model are then compared with bulk MOSFET.

It is observed that CGT/SGT device has better device performance in terms of different

power gains. This can be concluded that this circuit can be used for high frequency


Pujarini Ghosh 165

applications through proper designing and optimization of the structure. Improvement in

the CGT/SGT MOSFET as compared to bulk MOSFETs concluded that

cylindrical/surrounded architecture has a better gate control as compared to bulk

MOSFET.


Pujarini Ghosh 166

5.6. REFERENCES

[ATLAS10] ATLAS 3D DEVICE Simulator, SILVACO International, 2010.

[Auth97] C. P. Auth and J. D. Plummer, “Scaling theory for cylindrical,

fully depleted, surrounding-gate MOSFETs”, IEEE Electron

Device Letters. vol.18, no.2, pp. 74–76, 1997.

[Berroth90] M. Berroth and R. Bosch, “Broad band determination of the FET

small signal equivalent circuit”, IEEE Trans. Microwave Theory

Tech. vol. 38, no.7, pp. 891-895, 1990.

[Carson75] S. R. Carson, “High Frequency amplifiers”, Wiley-Interscience,

New York, 1975.

[Chen94] J.W Chen, M. Thurairaj and M.B Das, “Optimization of gate-to-

drain separation in submicron gate length modulation doped

FET’s for maximum power gain performances”, IEEE Trans

Electron Devices, vol.41, no.4, pp.465-475, 1994.

[Cho11] Seongjae Cho, Kyung Rok Kim, Byung-Gook Park, and In Man

Kang “Compact Modeling of Silicon Nanowire MOSFET for

Radio Frequency Applications”, Microwave and optical

technology letters, vol.53, no.2, pp.471-473, 2011.

[Collantes95] J. M. Collantes, J. J. Raoux, J. P. Villotte, R. Quere, G.

Montorial, and F.Dupis, “A new large-signal model based on

pulse measure ment techniques for RF power MOSFET”, IEEE

MTT- S Dig, Orlando, pp.1553-1556, 1995.

[Curtice84] W. R. Curtice and R. L, Camisa, “Self-consistent GaAs FET

models for amplifier design and device diagnostics”, IEEE

Trans. Microwave Theory Tech. vol.32, no.12, pp.1573-1578,

1984.

[Dambrine98] G. Dambrine, A Cappy, F. Heliodore and E. Playez, “A new

method for determining the FET small signal equivalent circuit”,


Pujarini Ghosh 167

IEEE Trans. Microwave Theory Tech. vol.36, no.7, pp.1151-

1159, 1988.

[Ghosh12a] P. Ghosh, S. Haldar, R.S. Gupta, M Gupta “An Analytical Drain

Current Model for Dual Material Engineered

Cylindrical/Surrounded Gate MOSFET” Microelectronics

Journal, vol.43, no.1, pp.17-24, 2012.

[Ghosh12b] P Ghosh, S Haldar, R.S Gupta and Mridula Gupta, “An Accurate

Small Signal Modeling of Cylindrical/Surrounded Gate

MOSFET for High Frequency Applications” Journal of

Semiconductor Technology and Science, vol.12, no.4, pp.377-

387, 2012.

[Golio08] M. Golio and J. Golio, “The RF and Microwave Passive and

Active Technologies”, Second Edition. CRC Press Taylor &

Francis Group, 2008.

[Goswami00] A. Goswami, A. Agarwal, S. Bose, S. Haldar, M. Gupta and R.S

Gupta, “Substrate effect dependent scattering parameter

extraction of short gate length IGFET for microwave frequency

applications”, Microwave optical technology Letters, vol.24,

no.5, pp.341-348, 2000.

[Goswami01] A. Goswami, M. Gupta and R.S.Gupta, “Analysis of scattering

parameters and thermal noise of a MOSFET for its Microwave

frequency applications”, Microwave optical technology Letters,

vol.31, no.2, pp.97-105, 2001.

[Guy98] B. M. Guy, Z. Ouarch, M. Prigent, R.Quere and J. Obregon,

“Direct extraction of a distributed nonlinear FET model from

pulsed I-V/ pulsed S-parameter measurements”, IEEE

Microwave and Guided Wave Letters, vol.8, no.2, pp.102-104,

1998.

[Ho97] M. C. Ho, K. Green, R. Culbertson, J. Y. Yang, D. Ladwing and

P.Ehnis, “A physical large signal Si-MOSFET model for RF


Pujarini Ghosh 168

Circuit design,” IEEE MTT-S Dig, Denver, CO; pp.391-394,

1997.

[Jiménez04a] D. Jiménez, J. J. Sáenz, B. Iñíguez, ,J. Suñé, L. F. Marsal, and J.

Pallarès, “Modeling of Nanoscale Gate-All-Around MOSFETs”

IEEE Electron Device Letters, vol.25, no.5, pp.314-316, 2004.

[Jiménez04b] D. Jiménez, B. Iñíguez, ,J. Suñé, ,L. F. Marsal, J. Pallarès, ,J.

Roig and D. Flores, “Continuous Analytic I–V Model for

Surrounding–Gate MOSFETs” IEEE Electron Device Letters,

vol.25, no.8, pp.571-573, 2004.

[Kilchytska03] V.Kilchytska, A.Neve, L.Vancaillie, D.Levacq, S.Adriaensen,

H.Van Meer, K.De Meyer, C.Raynaud, M.Dehan, J.P.Raskin

and D.Flandre, “Influence of device engineering on the analog

and RF performances of SOI MOSFETs”, IEEE Trans. Electron

Devices, vol.50, pp.577–588, 2003.

[Larson03] L.E.Larson, “Silicon technology tradeoffs for radio

frequency/mixed signal systems-on-a-chip”, IEEE Trans.

Electron Devices, vol.50, pp.683–699, 2003.

[Iñiguez05] B. Iñiguez, D. Jimenez, J. Roig, H. A. Hamid, L. F.Marsal, and

J. Pallares, “Explicit continuous model for long-channel

undoped surrounding-gate MOSFETs,” IEEE Trans. Electron

Devices, vol.52, no.8, pp.1868–1873, 2005.

[Ladbrooke89] P.H Ladbrooke, “MMIC design GaAs FET’s and HEMT’s”,

Artech House, Boston, London 1989.

[Lai07] R. Lai, X. B. Mei, W.R. Deal, W. Yoshida, Y. M. Kim, P.H. Liu,

J. Lee, J. Uyeda, L. Samoska and A. Fung, “Sub 50 nm InP

HEMT Device with Fmax Greater than 1 THz.” IEDM; pp.609-

611, 2007.

[Lee00] S. Lee and H.K. Yu, “A semianalytical parameter extraction of a

SPICE BSIM3v3 for RF MOSFET’s using S-parameters”, IEEE


Pujarini Ghosh 169

Trans. Microwave Theory and Techniques, vol.48, no.3, pp 412-

416, 2000.

[Liao87] S. Liao, “Microwave Circuit Analysis and Amplifier Design”,

Englewood Cliffs, NJ: Prentice-Hall, 1987.

[Lin94] F. Lin and G. Kompa, “FET model parameters extraction based

on optimization with multi plane data fitting and bidirectional

search: A new concept”, IEEE Trans. Microwave Theory Tech.

vol.42, no.7, pp. 1114-1121, 1994.

[Liu09] F. Liu, J. Zhang, F. He, F. Liu, L. Zhang and M. Chan “A

charge-based compact model for predicting the current–voltage

and capacitance–voltage characteristics of heavily doped

cylindrical surrounding-gate MOSFETs”, Solid State

Electronics, vol.53, pp. 49–53, 2009.

[Minasian77] R. A. Minasian, “Simplified GaAs MESFET model to 10GHz”,

IEEE Electron Device Letters, vol.13, no.18, pp. 549-551, 1977.

[Moldovan07] Oana Moldovan, Benjamin Iñiguez, David Jiménez, and Jaume

Roig, “Analytical Charge and Capacitance Models of Undoped

Cylindrical Surrounding-Gate MOSFETs,” IEEE Trans.

Electron Devices, vol.54, no.1, pp.162-165, 2007.

[Nagatomo93] K. Nagatomo, Y.H Daido, M. Shimizu and N. Okubo, “GaAs

MESFET characterization using least square approximation by

rational functions”, IEEE Trans. Microwave Theory Tech. vol.

41, no.2, pp. 199-205, 1993.

[Oh80] S. Y. Oh, D. E. Ward and R. W. Dutton “Transient analysis of

MOS transistor”, IEEE Journal Solid- State Circuit; vol.15,

no.4, pp. 636–43, 1980.

[Ramo93] S. Ramo, J. R. Whinnery and T. V. Duzer, “Fields and Waves in

Communication Electronics”, Third Edition, John Wiley & Sons

Inc. pp.537-541, 1993.


Pujarini Ghosh 170

[Rorsman96] N. Rorsman, M Garcia, C. Karlsson and H. Zirath., “Accurate

small signal modeling of HFET for millimeter-wave

applications”, IEEE Trans. Microwave Theory Tech. vol.44,

no.3, pp. 432-437, 1996.

[Saito98]

M. Saito, M. Ono, R. Fujimoto, H. Tanimoto, H. Nobuyuki, T.

Yoshitomi, T. Ohguro, H. S. Momose and H. Iwai, “0.15 µm RF

CMOS technology compatible with logic CMOS for low-voltage

operation”, IEEE Trans. Electron Devices, vol.45, pp.737–742,

1998.

[Schmitz91] A. E. Schmitz, R. H. Walden, L. E. Larson, S. E. Rosenbaum, R.

A. Metzber, J. R. Behnke and P. A. Mac Donald, “A deep-sub-

micrometer microwave digital CMOS SOS technology”, IEEE

Electron Device Letters, vol.12, pp.16-17, 1991.

[Vendlin82] D. G. Vendlin, “Design of amplifiers and oscillators by the S-

parameter method”, Wiley-Interscience, New York, 1982.

[Yang02]

J. Y. Yang, K. Benaissa, D. Crenshaw, B. Williams, S. Sridhar,

J. Ai, G. Boselli, S. Zhao, S. P. Tang, N. Mahalingam, S.

Ashburn, P. Madhani, T. Blythe and H. Shichijo, “0.1 µm RF

CMOS on high resistivity substrate for system on chip (SOC)

application”, Proceedings of IEDM, pp.667–670, 2002.

CHAPTER 5CHAPTER 555 Small Signal Intrinsic Equivalent Circuit Model...

Documents

Transcript of CHAPTER 5CHAPTER 555 Small Signal Intrinsic Equivalent Circuit Model...