CHAPTER 5 GENERATION OF PWM USING FPGA FOR...
Transcript of CHAPTER 5 GENERATION OF PWM USING FPGA FOR...
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CHAPTER 5
GENERATION OF PWM USING FPGA FOR ASYMMETRIC CASCADED
TWENTY SEVEN LEVEL INVERTER
5.1 Introduction
However, asymmetrical nine level inverter performances were better compared
to conventional method. But the content of harmonic (i.e. total harmonic distortion
THD) will be present that nine level. So whenever level of inverter will be increase,
THD & cost will be going to tremendously reduce. For this reason only, Twenty Seven
Level Cascaded Multilevel Inverter is proposed in this chapter [63].
5.2 Asymmetrical Nine Level Inverter Method
Asymmetric Nine Level Inverter was used in the conventional method.
However, asymmetric has benefit than symmetric, it content the amount of ripple. In
this method, nine level output produced by using only six switches. But the given dc
source value will be different and no of switches was minimum compared with
symmetric nine level. If any harmonic presences in the system, the effects, and losses
are high. It will be damage the entire part. To avoid THD we should increase the
inverter level then only system will be healthy. Because of these reason Twenty Seven
Level will be preferred.
5.3 Twenty Seven Level Cascaded Asymmetrical Inverter
Asymmetric Cascaded Inverter with DC Sources in 9:3:1 Ratio the structure
introduced in this thesis is a multilevel inverter [25], which uses unequal DC Sources.
The general function of this multilevel inverter is the same as that of the other two
inverters. The multilevel inverter using Asymmetric cascaded-inverter provides a large
number of output voltage levels without increasing the number of full bridge units. This
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configuration provides higher voltage at higher modulation frequencies due to which
the topology can be employed for high power applications [20].
Due to the reduction in the number of DC Sources employed, the structure
becomes more reliable and the output voltage has higher resolution due to increased
number of steps and the reference sinusoidal voltage can be better achieved. This
configuration recently becomes very popular in AC power supply and adjustable speed
drive applications [36]. This new inverter can avoid extra clamping diodes or voltage
balancing capacitors. An Asymmetric cascaded H-bridge inverter circuit is shown in
Fig.5.1.
Fig.5.1 Structure of Twenty Seven Level Asymmetrical cascaded inverter.
It is used to generate Twenty Seven Level output for the DC Sources 9:3:1 ratio.
The output waveform for S=3 have Twenty Seven Level as +13 …………. +1
[56] and zero. By different combinations of the 12 switches, S1-S12, each inverter
level can generate three different voltage outputs, + , - and zero. Fig.5.1 shows
Structure of Twenty Seven Level cascaded inverter with this circuit it is possible to
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obtain a maximum of Twenty Seven Level with the 9:3:1 ratio. Switching states
are developed for positive, negative and zero voltages and with these patterns the
switching table is developed and the gate pulses are generated. The generated gate
pulses are then given to each switch in accordance with the developed pattern and the
output is obtained. Thus the proposed circuit uses asymmetric voltages sources to
produce Twenty Seven Level.
Table 5.1 Switching for half cycle Asymmetrical Cascaded Inverter.
Bridge 1 (9v) Bridge 2(3v) Bridge 3(v) Voltage (amplitude)
0 0 0 0
0 0 1 V
0 1 -1 2V
0 1 0 3V
0 1 1 4V
1 -1 -1 5V
1 -1 0 6V
1 -1 1 7V
1 0 -1 8V
1 0 0 9V
1 0 1 10V
1 1 -1 11V
1 1 0 12V
1 1 1 13V
One advantage of this particular asymmetric MLI is that most of the power
delivered to the load by H Bridge having the highest DC source called “MAIN” bridge.
Table 5.1 shows the simulated power distribution in one phase of the Twenty Seven
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Level -level MLI as a function of output voltage [37]. At full power, around 81% of the
real power is delivered by the Main H-bridge but only 16% from the Aux-1 Bridge and
approximately 3% of the total power from Aux-2 Bridge. By using four bridges and
ternary voltage ratio we can have the 81 level output voltage but more bridges increase
the cost and hence their losses and will reduce the efficiency. Further for fourth bridge
DC source is 27 times the DC source voltage for the first bridge and hence bridge
requires much more different power rating still have to carry the same current. Rating
of the fourth bridge would be 27 times higher than rating of the first bridge and for 81
levels inverter switching losses are also increased. When we use the 3 bridges THD is
14.96 with additional one bridge it reduces to 12.9 that is not a great reduction. Hence,
In ACMLI use of ternary GP ratio with three bridges that is Twenty Seven Level is
optimum than all other level.
Fig.5.2 Simulation circuit diagram for Asymmetric Twenty Seven Level Inverter
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Fig.5.3 Simulation result for Asymmetric twenty seven level inverter
5.4 Proposed PWM generation using FPGA
A number of PWM methods are used to get the high frequency supply as well as
reduce the chip size. The Pulse width of PWM pulse changes with the Sine wave so as
to hold back the lower order harmonics with simple control and great DC utilization
[75]. With successively getting better reliability and performance of digital controllers,
the digital control techniques have majority over other analog controlled parts.
The proposed PWM generation unit is designed the synchronous binary counter
using mealy FSM with wave pipelined techniques, resulting in highest PWM
frequencies with an adjustable duty cycle resolution, while the PWM unit can be easily
interfaced to a microcontroller or DSP system. The improvement of high frequency
PWM generator architecture for power converter control by using FPGA. The resulting
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PWM frequency depends on the target FPGA device speed grade and the duty cycle
resolution constraints.
5.5 Proposed PWM generation with Mealy FSM based Counter and Wave
Pipelined (MFCWPT) Technique
The Proposed PWM techniques are designed to reduce the area and to increase the
frequency [58]. The area is reduced using Mealy FSM based 4 bit counter and
frequency is improved using Wave Pipelined techniques. Wave pipelined circuit
consist of clock gating structure. Hence the register clock is controlled by 2 input AND
gate. Global clock is generated, when en=1 and system clock is also one. So switching
activity is reduced during the clock input is zero. Proposed PWM is generated using
Mealy FSM based counter with Wave Pipelined (MFCWPT) Techniques offer less area
than the all other techniques and high frequency than the MFCPT techniques as shown
in Fig.5.4.
Fig. 5.4 Circuit diagram of Proposed PWM with Wave-pipelined techniques and
Modified FSM based counter (PPMCMP).
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Fig. 5.5 Circuit diagram of Clock-Gating Register.
Clock gating Register nothing but WPT Structure is shown in Fig.5.5 to reduce
the System Clock generation process. Wave pipelined techniques (WPT) is used to
obtain low area and less power consumption based PWM generation unit. Previous
PWM generation unit was designed by introducing pipelined techniques to perform the
parallel process in order to reduce the delay.
Fig.5.6 Simulation result of Proposed PWM generation using FPGA.
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Simulation process is illustrated the working principle of PWM pulse generation
using ModelSim6.3C. Whenever enable is high (1), corresponding input values are
processed to generate PWM pulses. For Example, if the input is seven, the
corresponding output is generating after the seven clock cycle as shown in Fig.5.6.
Similarly all the inputs are processed by introducing counter to count values.
Fig. 5.7 Area utilization of Proposed PWM with FSM based counter and Wave
Pipelined techniques.
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Fig. 5.8 Delay and Frequency utilizations of Proposed PWM with FSM based counter
and Wave Pipelined techniques.
Proposed PWM with Finite State machine based counter and WPT techniques is
used to reduce the delay utilization. Delay is measured by Xlinx10.1 Synthesis process
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as shown in Fig.5.8. Delay and Frequency of proposed PWM is improved as 3.240 ns
and 308.671 MHz
Table 5.2 Comparison of different PWM techniques using FPGA.
Fig. 5.9 Comparison of area and delay utilization of different PWM generation
techniques.
12
10
7
2.8143.65 3.24
0
2
4
6
8
10
12
14
Counter based PWM techniques
MFCPT based PWM techniques
MFCWPT based PWM Techniques
Slices
Delay (ns)
Different PWM
generation Techniques
Slices (Area) Delay (ns) Frequency
( MHz)
Counter based PWM
techniques
12 2.814 355.315
MFCPT based PWM
techniques
10 3.650 Twenty Seven
Level 3.946
MFCWPT based PWM
Techniques
7 3.240 308.671
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Fig. 5.10 Comparison of frequency utilization of different PWM generation techniques.
In this research work FPGA medium is chosen for generation of PWM as
triggering input for power inverter [46]. Two different PWM techniques have been
introduced in this work. Aiming at the reduction of area, PWM Techniques using
Mealy FSM based counter with pipelined technique (MFCPT) was proposed which
uses FSM based counter to reduce area. Even though it has efficiently reduced the area,
a reduction in frequency has also occurred in this method. Hence to overcome that, a
Proposed PWM using Mealy FSM based counter with Wave-pipelined techniques
(MFCWPT) was introduced which not only reduces the area by 50% of the
conventional method but also improves the frequency of the PWM [47].
355.315
273.946
308.671
0
75
150
225
300
375
Counter based PWM techniques
MFCPT based PWM techniques
MFCWPT based PWM Techniques
Frequency (MHz)
Counter based PWM techniques
MFCPT based PWM techniques
MFCWPT based PWM Techniques
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Table 5.3 Nine level Asymmetric and Twenty Seven Level Asymmetric Total
Harmonic Distortion (THD) Result in %.
Types THD Value
Nine level asymmetric 20.92
Twenty seven level asymmetric 3
Fig.5.11 THD analysis between Asymmetric Nine level and Twenty Seven level
Inverter.
Nine levels asymmetric is compared with proposed twenty seven level, reduced
number of component and THD in proposed scheme 6.3.Graphical result of THD result
obtained using Simulation result is mentioned in fig.5.11.
20.92
3
0
10
20
30
Nine Level Asymmetric Twenty seven level asymmtetric
THD
Nine Level Asymmetric
Twenty seven level asymmtetric
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5.6 Conclusion
Design of proposed Twenty Seven Level Inverter is provided better THD
performance with less number of active elements. The FPGA based hardware is
implementing and Result is compared with conventional topology of a novel nine
Level. The Less frequency and low ranges of THD is achieved using Asymmetrical
Twenty Seven Level Inverter using FPGA.