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Transcript of Chapter 5 Enhanced Direct Memory Access (EDMA). Dr. Naim Dahnoun, Bristol University, (c) Texas...
Chapter 5Chapter 5
Enhanced Direct Memory Access Enhanced Direct Memory Access (EDMA)(EDMA)
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004
Chapter 5, Slide 2
Learning ObjectivesLearning Objectives
The need for a DMA (EDMA).The need for a DMA (EDMA). Terms and definitions (with examples).Terms and definitions (with examples). EDMA functionality, including:EDMA functionality, including:
Transfer modes and synchronisation.Transfer modes and synchronisation. EDMA interrupt.EDMA interrupt. Quick DMA (QDMA).Quick DMA (QDMA).
Programming the EDMA, including:Programming the EDMA, including: Using the Chip Support Library (CSL).Using the Chip Support Library (CSL). Example “inout” program using Ping-Pong Example “inout” program using Ping-Pong
EDMA.EDMA.
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004
Chapter 5, Slide 3
The Need for a DMAThe Need for a DMA There are two methods for transferring data from one part of the memory to another, these are using:There are two methods for transferring data from one part of the memory to another, these are using:
(1)(1) CPU.CPU.
(2)(2) DMA.DMA.
If a DMA is used then the CPU only needs to configure the DMA. Whilst the transfer is taking place the CPU is then free to perform other operations.If a DMA is used then the CPU only needs to configure the DMA. Whilst the transfer is taking place the CPU is then free to perform other operations.
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004
Chapter 5, Slide 4
Introduction to the EDMAIntroduction to the EDMA
The ‘C6211/C6711 on-chip EDMA The ‘C6211/C6711 on-chip EDMA controller allows data transfers between controller allows data transfers between the level two (L2) cache memory the level two (L2) cache memory controller and the device peripherals.controller and the device peripherals.
These transfers include:These transfers include: Cache servicing.Cache servicing. Non-cacheable memory accesses.Non-cacheable memory accesses. User programmed data transfers.User programmed data transfers. Host accesses.Host accesses.
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004
Chapter 5, Slide 5
EDMA InterfaceEDMA Interface The C621x/C671x/C641x Block diagram.The C621x/C671x/C641x Block diagram.
The EDMA allows data transfer to/from any addressable memory spaces.The EDMA allows data transfer to/from any addressable memory spaces.
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004
Chapter 5, Slide 6
EDMA FunctionalityEDMA Functionality
The data transfer is performed with zero The data transfer is performed with zero overhead.overhead.
It is transparent to the CPU which means It is transparent to the CPU which means that the EDMA and CPU operations can that the EDMA and CPU operations can be independent.be independent.
However, if the EDMA and CPU both try However, if the EDMA and CPU both try to access the same memory location to access the same memory location arbitration will be performed by the arbitration will be performed by the program memory controller.program memory controller.
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004
Chapter 5, Slide 7
EDMA FunctionalityEDMA Functionality
mem1mem1 A0A0A1A1A2A2A3A3A4A4A5A5
mem2mem2 A0A0A1A1A2A2A3A3A4A4A5A5
A0A0A1A1A2A2A3A3A4A4A5A5
SourceSource DestinationDestination
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004
Chapter 5, Slide 8
EDMA FeaturesEDMA Features
The ‘C6211/C6711 on-chip EDMA The ‘C6211/C6711 on-chip EDMA controller has the following features:controller has the following features: 16 channels.16 channels. 1 auxiliary channel dedicated for the HPI 1 auxiliary channel dedicated for the HPI
(not accessible to the user).(not accessible to the user). 1 Quick DMA (QDMA).1 Quick DMA (QDMA).
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004
Chapter 5, Slide 9
EDMA Channel PrioritiesEDMA Channel Priorities
The ‘C6211/C6711 EDMA channels have two The ‘C6211/C6711 EDMA channels have two programmable levels of priority (Level 0 programmable levels of priority (Level 0 reserved only for the L2).reserved only for the L2).
* * Requests from CPU/L1 and L2 controllerRequests from CPU/L1 and L2 controller
Options Options (PRI 31:39)(PRI 31:39) Priority LevelPriority Level RequestorsRequestors
000b000b001b001b010b010b
011-111b011-111b
Level 0: UrgentLevel 0: UrgentLevel 1: HighLevel 1: HighLevel 2: LowLevel 2: Low
ReservedReserved
L2 Controller *L2 Controller *EDMA, QDMA, HPIEDMA, QDMA, HPIEDMA, QDMAEDMA, QDMA
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004
Chapter 5, Slide 10
EDMA PerformanceEDMA Performance
The ‘C6211/C6711 EDMA can perform The ‘C6211/C6711 EDMA can perform element transfers with element transfers with single-cyclesingle-cycle throughput provided there is no conflict.throughput provided there is no conflict.
The following conditions can limit the The following conditions can limit the performance:performance: EDMA stalls when there are multiple EDMA stalls when there are multiple
transfer requests on the same priority level.transfer requests on the same priority level. EDMA accesses to L2 SRAM with lower EDMA accesses to L2 SRAM with lower
priority than the CPU.priority than the CPU.
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004
Chapter 5, Slide 11
Some DefinitionsSome Definitions
The relation between a block, frame and The relation between a block, frame and element is shown below:element is shown below:
N N = Element count (ELECNT).= Element count (ELECNT). M M = Frame count (FRMCNT).= Frame count (FRMCNT). See See SPRU190SPRU190 page 6-5 for more. page 6-5 for more.
ElementElement
ESIZEESIZE
00: 32-bits00: 32-bits01: 16-bits01: 16-bits10: 8-bits10: 8-bits11: rsvd11: rsvd
Elem 1Elem 1
Elem 2Elem 2
Elem NElem N
FrameFrame
..
..
Frame 1Frame 1
Frame 2Frame 2
Frame Frame MM
BlockBlock
..
..
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004
Chapter 5, Slide 12
How the EDMA WorksHow the EDMA Works
Reload channel parameters.Reload channel parameters.
OptionsOptions
SourceSource
DestinationDestination
IndexIndex
Link AddrLink AddrCount ReloadCount Reload
3131 1616 1515 00
Transfer CountTransfer Count
Channel 15Channel 15
Channel 1Channel 1
......
Channel 0Channel 0
Reload 69Reload 69
Reload 1Reload 1
......
Reload 0Reload 0
The EDMA has a parameter RAM The EDMA has a parameter RAM composed of:composed of:
Parameter RAMParameter RAM
Channel parameters.Channel parameters.
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004
Chapter 5, Slide 13
How the EDMA WorksHow the EDMA Works
The EDMA has a parameter RAM composed of:The EDMA has a parameter RAM composed of: Channel parameters.Channel parameters. Reload channel parameters.Reload channel parameters.
The user programs both channel and reload channel parameters.The user programs both channel and reload channel parameters. The channel parameters contain all the information needed for the EDMA in order to perform a transfer.The channel parameters contain all the information needed for the EDMA in order to perform a transfer. When a transfer is complete the channel parameters are reloaded from the corresponding reload channel.When a transfer is complete the channel parameters are reloaded from the corresponding reload channel.
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004
Chapter 5, Slide 14
EDMA ParametersEDMA Parameters
The parameters in the parameter table need to be The parameters in the parameter table need to be determined before the EDMA can be programmed.determined before the EDMA can be programmed.
OptionsOptions
SourceSource
DestinationDestination
IndexIndex
Link AddrLink AddrCount ReloadCount Reload
3131 1616 1515 00
Transfer CountTransfer Count
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004
Chapter 5, Slide 15
EDMA Parameters (Options)EDMA Parameters (Options)
EDMA Channel Options RegisterEDMA Channel Options Register
ESIZEESIZE 2DS2DS TCCTCCTCINTTCINTSUMSUMPRIPRI31 2931 29
2DD2DD DUMDUM LINKLINK FSFS28 2728 27 2626 25 2425 24 2323 22 2122 21 2020 19 1619 16 11 00
RSVDRSVD15 215 2
Bit FieldBit Field
31:2931:29
28:2728:27
2626
25:2425:24
2323
22:2122:21
2020
19:1619:16
11
00
LabelLabel
PRIPRI
ESIZEESIZE
2DS2DS
SUMSUM
2DD2DD
DUMDUM
TCINTTCINT
TCCTCC
LINKLINK
FSFS
DescriptionDescription
Priority levels for the EDMA eventPriority levels for the EDMA event
Element size (32/16/8-bit)Element size (32/16/8-bit)
Source dimensionSource dimension
Source address update modeSource address update mode
Destination dimensionDestination dimension
Destination address update modeDestination address update mode
Transfer complete interrupt enableTransfer complete interrupt enable
Transfer complete codeTransfer complete code
LinkLink
Frame synchronisationFrame synchronisation
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004
Chapter 5, Slide 16
EDMA Parameters (Options)EDMA Parameters (Options)
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004
Chapter 5, Slide 17
EDMA Parameters (Options)EDMA Parameters (Options)
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004
Chapter 5, Slide 18
EDMA ParametersEDMA Parameters
Source:Source: Start address of the source. Start address of the source. Transfer Count:Transfer Count:
Upper 16 bits [31:16]: Frame count.Upper 16 bits [31:16]: Frame count. Lower 16 bits [15:0]: Element count.Lower 16 bits [15:0]: Element count.
Destination:Destination: Start address of the destination. Start address of the destination.
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004
Chapter 5, Slide 19
EDMA ParametersEDMA Parameters
Index:Index: Upper 16 bits [31:16]: Frame index.Upper 16 bits [31:16]: Frame index. Lower 16 bits [15:0]: Element index.Lower 16 bits [15:0]: Element index.
Count reload:Count reload: Value to be reloaded into the element count when a frame is complete (only used in 1-D mode). Value to be reloaded into the element count when a frame is complete (only used in 1-D mode). Link address:Link address: Specifies the address from where the parameters are reloaded. The 16-bit value is added to 0x01A0 xxxx to form the 32-bit address. Specifies the address from where the parameters are reloaded. The 16-bit value is added to 0x01A0 xxxx to form the 32-bit address.
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004
Chapter 5, Slide 20
EDMA SynchronisationEDMA Synchronisation
Two methods for initiating a transfer:Two methods for initiating a transfer:
This is known as unsynchronised EDMA. With this method the CPU This is known as unsynchronised EDMA. With this method the CPU writes to the Event Register (ER) through the Event Set Register (ESR) in writes to the Event Register (ER) through the Event Set Register (ESR) in order to start the EDMA transfer (this can be used to simulate an event).order to start the EDMA transfer (this can be used to simulate an event).
(1)(1) CPU initiated.CPU initiated.
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004
Chapter 5, Slide 21
In this case the event is latched in the Event Register (ER) which then In this case the event is latched in the Event Register (ER) which then triggers the transfer.triggers the transfer.
The events that can trigger a transfer are given on the following slide.The events that can trigger a transfer are given on the following slide.
EDMA SynchronisationEDMA Synchronisation
Two methods for initiating a transfer:Two methods for initiating a transfer:
(2)(2) Event triggered.Event triggered.(1)(1) CPU initiated.CPU initiated.
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004
Chapter 5, Slide 22
EDMA EventsEDMA Events
An event can be cleared using the CPU by An event can be cleared using the CPU by writing to the Event Clear Register (ECR).writing to the Event Clear Register (ECR).
Channel0123456789
101112131415
EventDSPINTTINT0TINT1
SD_INTEXT_INT4EXT_INT5EXT_INT6EXT_INT7
EDMA_TCC8EDMA_TCC9EDMA_TCC10EMDA_TCC11
XEVT0REVT0XEVT1REVT1
Event DescriptionHost port host to DSP interruptTimer 0 interruptTimer 1 interruptEMIF SDRAM timer interruptExternal interrupt pin 4External interrupt pin 5External interrupt pin 6External interrupt pin 7EDMA transfer complete code 1000b interruptEDMA TCC 1001b interruptEDMA TCC 1010b interruptEDMA TCC 1011b interruptMcBSP0 transmit eventMcBSP0 receive eventMcBSP1 transmit eventMcBSP1 receive event
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004
Chapter 5, Slide 23
Transfer SynchronisationTransfer Synchronisation
The synchronisation mode depends on whether or not the transfer is The synchronisation mode depends on whether or not the transfer is two dimensional.two dimensional.
Therefore first specify that the transfer is either 1-D or 2-D.Therefore first specify that the transfer is either 1-D or 2-D.
0b = 1 dimensional0b = 1 dimensional 1b = 2 dimensional1b = 2 dimensional
2DS 2DD Options Register2DS 2DD Options Register
26 2326 23
Destination dimensionDestination dimension
Source dimensionSource dimension
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004
Chapter 5, Slide 24
1-D Synchronisation1-D Synchronisation
There are two modes of synchronisation in the 1-D transfer mode.There are two modes of synchronisation in the 1-D transfer mode. These are:These are:
Element synchronised: each event causes one element to be transferred.Element synchronised: each event causes one element to be transferred. Frame synchronised: each event causes a whole frame to be transferred.Frame synchronised: each event causes a whole frame to be transferred.
The FS bit is used to specify the synchronisation mode.The FS bit is used to specify the synchronisation mode.
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004
Chapter 5, Slide 25
1-D Transfer Synchronisation1-D Transfer Synchronisation
Element synchronised (FS=0):Element synchronised (FS=0): In this case the EDMA transfers each element after receiving the synchronisation event until the whole frame is transferred.In this case the EDMA transfers each element after receiving the synchronisation event until the whole frame is transferred. The element count is then reloaded and the frame count decremented.The element count is then reloaded and the frame count decremented. The frame index is then added to the last element address to calculate the next frame start address.The frame index is then added to the last element address to calculate the next frame start address. If the link is enabled (LINK=1b) then the transfer parameters are reloaded.If the link is enabled (LINK=1b) then the transfer parameters are reloaded.
FS Options RegisterFS Options Register
00
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004
Chapter 5, Slide 26
Example: 1-D Transfer with FS=0Example: 1-D Transfer with FS=0
ESIZE = 10bESIZE = 10b ELECNT = 4ELECNT = 4 FRMCNT = 0FRMCNT = 0 SUM = 01bSUM = 01b
DST:DST:
8 bits8 bits
889910101111
8-bit Pixels8-bit Pixels11 22 33 44 55 66
77 1212
1313 1414 1515 1616 1717 1818
1919 2020 2121 2222 2323 2424
2525 2626 2727 2828 2929 3030
88 99 1010 1111889910101111
88 99 1010 1111SRC:SRC:
SourceSource DestinationDestination
Sync eventSync event
00b = 32-bits00b = 32-bits 01b = 16-bits01b = 16-bits 10b = 8-bits10b = 8-bits 11b = Reserved11b = Reserved
00b = Fixed00b = Fixed 01b = Increment01b = Increment 10b = Decrement10b = Decrement 11b = Modified by INDEX11b = Modified by INDEX
FRMCNT = M - 1FRMCNT = M - 1
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004
Chapter 5, Slide 27
Example: 1-D Transfer with FS=0Example: 1-D Transfer with FS=0
DST:DST:
8 bits8 bits
889910101111
8-bit Pixels8-bit Pixels11 22 33 44 55 66
77 1212
1313 1414 1515 1616 1717 1818
1919 2020 2121 2222 2323 2424
2525 2626 2727 2828 2929 3030
88 99 1010 1111889910101111
88 99 1010 1111
Source = SRC+7Source = SRC+7
Destination = DSTDestination = DST
FRMIDX ELEIDXFRMIDX ELEIDX
Link AddrLink AddrCount ReloadCount Reload
3131 1616 1515 00
FRMCNT = 0 ELECNT = 4FRMCNT = 0 ELECNT = 4
ESIZEESIZE
OptionsOptions 1010
SRC:SRC:
SourceSource DestinationDestination
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004
Chapter 5, Slide 28
DST:DST:
8 bits8 bits
661010141418182222
Example: 1-D Transfer with FS=0Example: 1-D Transfer with FS=0
ESIZE = 10b (8-bits)ESIZE = 10b (8-bits) ELECNT = 5, FRMCNT = 0ELECNT = 5, FRMCNT = 0 SUM = 11bSUM = 11b ELEIDX = 4ELEIDX = 4
8-bit Pixels8-bit Pixels11 22 33 44
55
99 1010 1111 1212
1313 1414 1515 1616
1717 1818 1919 2020
66 77 88
2121 2222 2323 2424
2525 2626 2727 2828
66
1010
1414
1818
2222
661010141418182222
SourceSource DestinationDestination
SRC:SRC:
In this mode:In this mode:Next frame addr = Next frame addr = LastLast element addr + FRMIDX element addr + FRMIDX
Sync eventSync event
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004
Chapter 5, Slide 29
1-D Transfer Synchronisation1-D Transfer Synchronisation
Frame synchronised (FS=1):Frame synchronised (FS=1): In this case the EDMA transfers a whole frame after receiving the synchronisation event.In this case the EDMA transfers a whole frame after receiving the synchronisation event. In this mode the frame index no longer represents the difference between the address of the last element of the frame and the start address of the next frame.In this mode the frame index no longer represents the difference between the address of the last element of the frame and the start address of the next frame. The frame index is added to the start address of the frame to derive the start address of the next frame.The frame index is added to the start address of the frame to derive the start address of the next frame. See the example on the following slide.See the example on the following slide.
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004
Chapter 5, Slide 30
16 bits16 bits
88101012121616
3636......
404042424444......
16-bit Data16-bit Data11 22 33 44 55 66 77
1212 1313 1414
1515 1616 1717 1818 1919 2020 2121
2222 2323 2424 2525 2626 2727 2828
88 99 1010 1111
2929 3030 3131 3232 3333 3434 3535
3636 3737 3838 3939 4040 4141 4242
4343 4444 4545 4646 4747 4848 4949
Example: 1-D Transfer with FS=1Example: 1-D Transfer with FS=1
All elements in a frame are offset by All elements in a frame are offset by ELEIDX bytes.ELEIDX bytes.
All frames in a block are offset by All frames in a block are offset by FRMIDX bytes.FRMIDX bytes.
DST:DST: 8810101212
121288 1010SRC:SRC:
SourceSource DestinationDestination
20201616 1818
28282424 2626
3232 3434
3636
1616......3636404042424444
4040 4242
4444
Sync eventSync event
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004
Chapter 5, Slide 31
16 bits16 bits
88101012121616
3636......
404042424444
16-bit Data16-bit Data11 22 33 44 55 66 77
1212 1313 1414
1515 1616 1717 1818 1919 2020 2121
2222 2323 2424 2525 2626 2727 2828
88 99 1010 1111
2929 3030 3131 3232 3333 3434 3535
3636 3737 3838 3939 4040 4141 4242
4343 4444 4545 4646 4747 4848 4949
Example: 1-D Transfer with FS=1Example: 1-D Transfer with FS=1
ESIZE = 01b (16bits)ESIZE = 01b (16bits) ELECNT = 3ELECNT = 3 FRMCNT = 4FRMCNT = 4 SUM = 11b, 2DS = 0, FS = 1SUM = 11b, 2DS = 0, FS = 1 FRMIDX = 16, ELEIDX = 4FRMIDX = 16, ELEIDX = 4
DST:DST: 8810101212
121288 1010SRC:SRC:
SourceSource DestinationDestination
20201616 1818
28282424 2626
3636
3232 34341616......3636404042424444
4040 4242
4444
In this mode:In this mode:Next frame addr = Next frame addr = FirstFirst element addr + FRMIDX element addr + FRMIDX
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004
Chapter 5, Slide 32
DST:DST:
8 bits8 bits
8-bit Pixels8-bit Pixels11 22 33 44 55 66
77 1212
1313 1414 1515 1616 1717 1818
1919 2020 2121 2222 2323 2424
2525 2626 2727 2828 2929 3030
88 99 1010 1111SRC:SRC:
SourceSource DestinationDestination
22441414161626262828
Example: 1-D Transfer with FS=1Example: 1-D Transfer with FS=1
22 44
1414 1616
2626 2828
ESIZE = 10bESIZE = 10b ELECNT = 2ELECNT = 2 FRMCNT = 2FRMCNT = 2 SUM = 01b, 2DS =0b, FS = 1SUM = 01b, 2DS =0b, FS = 1 FRMIDX = 12, ELEIDX = 2FRMIDX = 12, ELEIDX = 2
22441414161626262828
Sync eventSync event
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004
Chapter 5, Slide 33
2-D Synchronisation2-D Synchronisation
There are two modes of synchronisation in the 2-D transfer mode.There are two modes of synchronisation in the 2-D transfer mode. These are:These are:
Array synchronised: each event causes one line of the array to be transferred.Array synchronised: each event causes one line of the array to be transferred. Block synchronised: each event causes the entire block to be transferred.Block synchronised: each event causes the entire block to be transferred.
The FS bit is used to specify the synchronisation mode.The FS bit is used to specify the synchronisation mode.
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004
Chapter 5, Slide 34
2-D Transfer Synchronisation2-D Transfer Synchronisation
Array synchronised (FS=0):Array synchronised (FS=0): This is the same as the 1-D frame synchronisation mode except that the elements are all contiguous.This is the same as the 1-D frame synchronisation mode except that the elements are all contiguous. One array is transferred per synchronisation event.One array is transferred per synchronisation event. The frame count is equal to the number of frames minus one because when the FRMCNT=0 the complete transfer parameters are reloaded after sending the last The frame count is equal to the number of frames minus one because when the FRMCNT=0 the complete transfer parameters are reloaded after sending the last
transfer request to the address generation hardware.transfer request to the address generation hardware. The frame index is added to the start address of the frame to derive the next frame address.The frame index is added to the start address of the frame to derive the next frame address.
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004
Chapter 5, Slide 35
16-bit Data16-bit Data11 22 33 44 55 66 77
1212 1313 1414
1515 1616 1717 1818 1919 2020 2121
2222 2323 2424 2525 2626 2727 2828
88 99 1010 1111
2929 3030 3131 3232 3333 3434 3535
3636 3737 3838 3939 4040 4141 4242
4343 4444 4545 4646 4747 4848 4949
Example: 2-D Transfer with FS=0Example: 2-D Transfer with FS=0
With 2D transfers there is no indexing With 2D transfers there is no indexing between elements, therefore ELEIDX is between elements, therefore ELEIDX is not used in 2D transfers.not used in 2D transfers.
To specify a 2D source set 2DS in channel To specify a 2D source set 2DS in channel options.options.
16 bits16 bits
889910101111
......1515
4040
DST:DST:99 111188 1010
SRC:SRC:
SourceSource DestinationDestination
889910101111
1616 18181515 1717
2323 25252222 2424
3030 32322929 3131
3737 40403636 38381515......4040
Sync eventSync event
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004
Chapter 5, Slide 36
16-bit Data16-bit Data11 22 33 44 55 66 77
1212 1313 1414
1515 1616 1717 1818 1919 2020 2121
2222 2323 2424 2525 2626 2727 2828
88 99 1010 1111
2929 3030 3131 3232 3333 3434 3535
3636 3737 3838 3939 4040 4141 4242
4343 4444 4545 4646 4747 4848 4949
Example: 2-D Transfer with FS=0Example: 2-D Transfer with FS=0
16 bits16 bits
889910101111
......1515
4040
DST:DST:99 111188 1010
SRC:SRC:
SourceSource DestinationDestination
889910101111
1616 18181515 1717
2323 25252222 2424
3030 32322929 3131
3737 40403636 38381515......4040
ESIZE = 01b (16bits)ESIZE = 01b (16bits) ELECNT = 4, FRMCNT = 4ELECNT = 4, FRMCNT = 4 SUM = 01b, 2DS = 1bSUM = 01b, 2DS = 1b FRMIDX = 14, ELEIDX = N/AFRMIDX = 14, ELEIDX = N/A
In this mode:In this mode:Next frame addr = Next frame addr = FirstFirst element addr + FRMIDX element addr + FRMIDX
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004
Chapter 5, Slide 37
2-D Transfer Synchronisation2-D Transfer Synchronisation
Block synchronised (FS=1):Block synchronised (FS=1): This is the same as the 1-D frame synchronisation mode except that the elements are all contiguous.This is the same as the 1-D frame synchronisation mode except that the elements are all contiguous. The entire block is transferred following the synchronisation event.The entire block is transferred following the synchronisation event. At the end of each frame the frame index is added to the last element address to calculate the next frame start address.At the end of each frame the frame index is added to the last element address to calculate the next frame start address.
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004
Chapter 5, Slide 38
Example: 2-D Transfer with FS=1Example: 2-D Transfer with FS=1
16-bit Data16-bit Data11 22 33 44 55 66 77
1212 1313 1414
1515 1616 1717 1818 1919 2020 2121
2222 2323 2424 2525 2626 2727 2828
88 99 1010 1111
2929 3030 3131 3232 3333 3434 3535
3636 3737 3838 3939 4040 4141 4242
4343 4444 4545 4646 4747 4848 4949
16 bits16 bits
889910101111
......1515
4040
DST:DST:99 111188 1010
SRC:SRC: 889910101111
1616 18181515 1717
2323 25252222 2424
3030 32322929 3131
3737 40403636 38381515......4040
SourceSource DestinationDestination
ESIZE = 01b (16bits)ESIZE = 01b (16bits) ELECNT = 4, FRMCNT = 4ELECNT = 4, FRMCNT = 4 SUM = 01b, 2DS = 1bSUM = 01b, 2DS = 1b FRMIDX = 8, ELEIDX = N/AFRMIDX = 8, ELEIDX = N/A
In this mode:In this mode:Next frame addr = Next frame addr = LastLast element addr + FRMIDX element addr + FRMIDX
Sync eventSync event
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004
Chapter 5, Slide 39
EDMA Interrupt GenerationEDMA Interrupt Generation
The EDMA controller is responsible for generating transfer completion interrupts to the CPU.The EDMA controller is responsible for generating transfer completion interrupts to the CPU. The EDMA generates a single interrupt (EDMA_INT) to the CPU on behalf of all 16 channels.The EDMA generates a single interrupt (EDMA_INT) to the CPU on behalf of all 16 channels. The programmer has to read the CIPR register to determine which channel caused the interrupt or The programmer has to read the CIPR register to determine which channel caused the interrupt or
which interrupts are pending while the ISR is being serviced.which interrupts are pending while the ISR is being serviced.
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004
Chapter 5, Slide 40
EDMA Interrupt GenerationEDMA Interrupt Generation
TCINT TCC
31 20 19 16 0
OPTIONSOPTIONS
Each channel has an Each channel has an OPTIONSOPTIONS register register OPTIONSOPTIONS contains: contains:
TCINTTCINT - do you want to interrupt CPU?- do you want to interrupt CPU? TCC TCC - 4 bit completion code (your choice)- 4 bit completion code (your choice)
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004
Chapter 5, Slide 41
EDMA Interrupt GenerationEDMA Interrupt Generation
TCINT TCC
31 20 19 16 0
OPTIONSOPTIONS
Each channel has an Each channel has an OPTIONSOPTIONS register register OPTIONSOPTIONS contains: contains:
TCINTTCINT - do you want to interrupt CPU?- do you want to interrupt CPU? TCC TCC - 4 bit completion code (your choice)- 4 bit completion code (your choice)
Upon completion:Upon completion: If you set TCINT = 1, then CIPR bit equal toIf you set TCINT = 1, then CIPR bit equal to TCC value (you set) is set to oneTCC value (you set) is set to one
rsvd CIP15 CIP14 CIP8 CIP7 CIP6 CIP5 CIP4 CIP3 CIP2 CIP1 CIP0
31 15 14 8 7 6 5 4 3 2 1 0
CIPRCIPR
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004
Chapter 5, Slide 42
EDMA Interrupt GenerationEDMA Interrupt Generation
TCINT TCC
31 20 19 16 0
OPTIONSOPTIONS
Each channel has an Each channel has an OPTIONSOPTIONS register register OPTIONSOPTIONS contains: contains:
TCINTTCINT - do you want to interrupt CPU?- do you want to interrupt CPU? TCC TCC - 4 bit completion code (your choice)- 4 bit completion code (your choice)
Upon completion:Upon completion: If you set TCINT = 1, then CIPR bit equal toIf you set TCINT = 1, then CIPR bit equal to TCC value (you set) is set to oneTCC value (you set) is set to one
CIER bit must be setCIER bit must be set for CPU to be interrupted for CPU to be interrupted Only 1 EDMA interrupt to CPUOnly 1 EDMA interrupt to CPU. Upon int, CPU should service all . Upon int, CPU should service all
pending channels set in CIPRpending channels set in CIPR
rsvd CIP15 CIP14 CIP8 CIP7 CIP6 CIP5 CIP4 CIP3 CIP2 CIP1 CIP0
31 15 14 8 7 6 5 4 3 2 1 0
CIPRCIPR
CIERCIER rsvd CIE15 CIE14 CIE8 CIE7 CIE6 CIE5 CIE4 CIE3 CIE2 CIE1 CIE0
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004
Chapter 5, Slide 43
Chaining EDMA TransfersChaining EDMA Transfers
After completion of an EDMA channel transfer another EDMA channel transfer can be triggered.After completion of an EDMA channel transfer another EDMA channel transfer can be triggered. This triggering mechanism is similar to event triggering.This triggering mechanism is similar to event triggering. However this method can only be used to trigger EDMA channels 8 to 11.However this method can only be used to trigger EDMA channels 8 to 11.
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004
Chapter 5, Slide 44
Chaining EDMA TransfersChaining EDMA Transfers
In addition to setting the TCINT and TCC bits there is In addition to setting the TCINT and TCC bits there is also another register, the Channel Chain Enable Register also another register, the Channel Chain Enable Register (CCER) that must be set.(CCER) that must be set.
CCE11CCE11 CCE10CCE10 ReservedReservedCCE8CCE8CCE9CCE9ReservedReserved
1111 1010 7 07 0889931 31 1212
Channel Chain Enable Register (CCER)Channel Chain Enable Register (CCER)
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004
Chapter 5, Slide 45
Chaining EDMA TransfersChaining EDMA TransfersChannel Changing … ah, that is, Channel Changing … ah, that is, Channel ChainingChannel Chaining
CCERCCER rsvd CCE11CCE10 CCE8 rsvd CCE9
Upon completion, one EDMA channel can kick-off anotherUpon completion, one EDMA channel can kick-off another Rather than setting CIER bit (to enable CPU int), set CCER Rather than setting CIER bit (to enable CPU int), set CCER
to enable channel 8-11 to startto enable channel 8-11 to start
TCINT TCC
31 20 19 16 0
OPTIONSOPTIONS
CIPRCIPR CIP11 CIP10 CIP8 CIP9
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004
Chapter 5, Slide 46
EDMA Interrupt GenerationEDMA Interrupt GenerationE V T15 E V T14 E V T0E V T1
R E V T1 XE V T1 T IN T0 D S P IN T
E E 15 E E 14 E E 0E E 1
T riggers
C om plete
C hanne l 15
T riggers
C om plete
C hanne l 14
T riggers
C om plete
C hanne l 1
T riggers
C om plete
C hanne l 0
TC IN T TC C
D ecoder
4
E D M A _IN T
E S R 14E S R 15 E S R 1 E S R 0
TC IN T TC C
D ecoder
4
E V T11
E E 11
T riggers
C om plete
C hanne l 11
E V T8
E E 8
T riggers
C om plete
C hanne l 8
E S R 11 E S R 8C C 11 C C 8
C IP 15 C IP 14 C IP 0C IP 1C IP 11
C C E 11
C IP 8
C C E 8
C IE 15 C IE 14 C IE 0C IE 1C IE 11 C IE 8
C C 11 C C 8
Event Register(ER)
Event Enable Register(EER)
Channel InterruptPending Register (CIPR)
Channel Chain EnableRegister (CCER)
Channel InterruptEnable Register (CIER)
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004
Chapter 5, Slide 47
Introduction to the Quick DMA (QDMA)Introduction to the Quick DMA (QDMA)
The QDMA provides a very efficient way of moving data.The QDMA provides a very efficient way of moving data. It supports nearly all the same modes as the EDMA however transfer requests are submitted faster.It supports nearly all the same modes as the EDMA however transfer requests are submitted faster. However it does not support reload of a count or link.However it does not support reload of a count or link. Therefore the QDMA is suited to one-off moves of blocks of data internally whereas the EDMA is suited to moving data between Therefore the QDMA is suited to one-off moves of blocks of data internally whereas the EDMA is suited to moving data between
peripherals and the memory.peripherals and the memory.
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004
Chapter 5, Slide 48
QDMA RegistersQDMA Registers
The QDMA is programmed via two sets of five write-only memory mapped registers:The QDMA is programmed via two sets of five write-only memory mapped registers: Writing to the first set of registers configures the QDMA but does not submit a request.Writing to the first set of registers configures the QDMA but does not submit a request. Writing to the second set of registers configures the QDMA and submits a transfer request.Writing to the second set of registers configures the QDMA and submits a transfer request.
OptionsOptions
SourceSource
DestinationDestination
IndexIndex
3131 1616 1515 00
Transfer CountTransfer Count
OptionsOptions
SourceSource
DestinationDestination
IndexIndex
3131 1616 1515 00
Transfer CountTransfer Count
0x0200 00000x0200 0000
0x0200 00040x0200 0004
0x0200 00080x0200 0008
0x0200 000c0x0200 000c
0x0200 00100x0200 0010
0x0200 00200x0200 0020
0x0200 00240x0200 0024
0x0200 00280x0200 0028
0x0200 002c0x0200 002c
0x0200 00300x0200 0030
QDMA Registers (Set 1)QDMA Registers (Set 1) QDMA Pseudo Registers (Set 2)QDMA Pseudo Registers (Set 2)
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004
Chapter 5, Slide 49
QDMA Options RegisterQDMA Options Register
EDMA Channel Options RegisterEDMA Channel Options Register
ESIZEESIZE 2DS2DS TCCTCCTCINTTCINTSUMSUMPRIPRI31 2931 29
2DD2DD DUMDUM RSVDRSVD FSFS28 2728 27 2626 25 2425 24 2323 22 2122 21 2020 19 1619 16 11 00
RSVDRSVD15 215 2
Bit FieldBit Field
31:2931:29
28:2728:27
2626
25:2425:24
2323
22:2122:21
2020
19:1619:16
00
LabelLabel
PRIPRI
ESIZEESIZE
2DS2DS
SUMSUM
2DD2DD
DUMDUM
TCINTTCINT
TCCTCC
FSFS
DescriptionDescription
Priority levels for the QDMA eventPriority levels for the QDMA event
Element size (32/16/8-bit)Element size (32/16/8-bit)
Source dimensionSource dimension
Source address update modeSource address update mode
Destination dimensionDestination dimension
Destination address update modeDestination address update mode
Transfer complete interrupt enableTransfer complete interrupt enable
Transfer complete codeTransfer complete code
Frame synchronisationFrame synchronisation
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004
Chapter 5, Slide 50
Other QDMA RegistersOther QDMA Registers Source:Source: Start address of the source. Start address of the source. Transfer Count:Transfer Count:
Upper 16 bits [31:16]: Frame count.Upper 16 bits [31:16]: Frame count. Lower 16 bits [15:0]: Element count.Lower 16 bits [15:0]: Element count.
Destination:Destination: Start address of the destination. Start address of the destination. Index:Index:
Upper 16 bits [31:16]: Frame index.Upper 16 bits [31:16]: Frame index. Lower 16 bits [15:0]: Element index.Lower 16 bits [15:0]: Element index.
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004
Chapter 5, Slide 51
Configuring the QDMAConfiguring the QDMA
Five writes are required to submit a request:Five writes are required to submit a request: The first four registers are configured by writing to the corresponding QDMA registers.The first four registers are configured by writing to the corresponding QDMA registers. The fifth register is configured by writing to the corresponding pseudo register causing the request to be The fifth register is configured by writing to the corresponding pseudo register causing the request to be
submitted.submitted.
OptionsOptions
SourceSource
DestinationDestination
IndexIndex
3131 1616 1515 00
Transfer CountTransfer Count
OptionsOptions
SourceSource
DestinationDestination
IndexIndex
3131 1616 1515 00
Transfer CountTransfer Count
0x0200 00000x0200 0000
0x0200 00040x0200 0004
0x0200 00080x0200 0008
0x0200 000c0x0200 000c
0x0200 00100x0200 0010
0x0200 00200x0200 0020
0x0200 00240x0200 0024
0x0200 00280x0200 0028
0x0200 002c0x0200 002c
0x0200 00300x0200 0030
QDMA Registers (Set 1)QDMA Registers (Set 1) QDMA Pseudo Registers (Set 2)QDMA Pseudo Registers (Set 2)
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004
Chapter 5, Slide 52
Features of the QDMAFeatures of the QDMA
All transfers are frame synchronised.All transfers are frame synchronised. Although linking is not supported, completion interrupts and channel chaining are supported.Although linking is not supported, completion interrupts and channel chaining are supported. The values held in the registers are not changed by the hardware hence the same transfer can be repeated The values held in the registers are not changed by the hardware hence the same transfer can be repeated
by a single write to one of the pseudo registers.by a single write to one of the pseudo registers.
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004
Chapter 5, Slide 53
Programming the EDMAProgramming the EDMA
There are three methods available for programming the EDMA:There are three methods available for programming the EDMA:(1)(1) Writing directly to the EDMA registers.Writing directly to the EDMA registers.
(2)(2) Using the Chip Support Library (CSL).Using the Chip Support Library (CSL).
(3)(3) Graphically using the DSP/BIOS GUI interface.Graphically using the DSP/BIOS GUI interface.
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004
Chapter 5, Slide 54
Programming the EDMA - DirectProgramming the EDMA - Direct
(1)(1) Writing directly to the EDMA registers:Writing directly to the EDMA registers: Although this method is straightforward, it relies on a good understanding of the EDMA and the Although this method is straightforward, it relies on a good understanding of the EDMA and the
DSP memory map.DSP memory map. This method is tedious and prone to errors.This method is tedious and prone to errors.
#include <intr.h>#include <intr.h>
#include <regs.h>#include <regs.h>
#include <c6211dsk.h>#include <c6211dsk.h>
void EDMA_setup (void)void EDMA_setup (void)
{{
*(unsigned volatile int *) ECR = 0xffff;*(unsigned volatile int *) ECR = 0xffff;
*(unsigned volatile int *) EER = 0xffff;*(unsigned volatile int *) EER = 0xffff;
*(unsigned volatile int *) CIPR = 0xffff;*(unsigned volatile int *) CIPR = 0xffff;
*(unsigned volatile int *) CIER = 0xffff;*(unsigned volatile int *) CIER = 0xffff;
......
}}
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004
Chapter 5, Slide 55
Programming the EDMA - CSLProgramming the EDMA - CSL
(2)(2) Using the Chip Support Library:Using the Chip Support Library: The CSL provides a C language interface for configuring and controlling the on-chip peripherals, in this case the EDMA.The CSL provides a C language interface for configuring and controlling the on-chip peripherals, in this case the EDMA. The library is modular with each module corresponding to a specific peripheral. This has the advantage of reducing the code size.The library is modular with each module corresponding to a specific peripheral. This has the advantage of reducing the code size. Some modules rely on other modules also being included, for example the IRQ module is required when using the EDMA module.Some modules rely on other modules also being included, for example the IRQ module is required when using the EDMA module.
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004
Chapter 5, Slide 56
Programming the EDMA - CSLProgramming the EDMA - CSL
The CSL can be divided into four sections:The CSL can be divided into four sections:Constants Functions Macros Structure
EDMA_CHA_CNT EDMA_allocTable EDMA_ADDR (<REG>) EDMA_ConfigEDMA_SUPPORT EDMA_allocTableEx EDMA_RGET(<REG>)
EDMA_TABLE_CNT EDMA_chain EDMA_RSET(<REG>,X)EDMA_clearChannel EDMA_FGET(<REG>,<FIELD>)
EDMA_clearParm EDMA_FSET(<REG>,<FIELD>,fieldval)EDMA_close EDMA_FSETS(<REG>,<FIELD>,<SYM>)
EDMA_config EDMA_RGETA(addr, <REG>)EDMA_configArgs EDMA_RSETA(addr,<REG>,x)
EDMA_disableChaining EDMA_FGETA(addr,<REG>,<FIELD>)EDMA_enableChaining EDMA_FSETA(addr,<REG>,<FIELD>,fieldval)EDMA_disableChannel EDMA_FSETSA(addr,<REG>,<FIELD>,<SYM>)EDMA_enableChannel EDMA_ADDRH(h,<REG>)
EDMA_freeTable EDMA_RGETH(h,<REG>)EDMA_freeTableEx EDMA_RSETH(h,<REG>,x)EDMA_getChannel EDMA_FGETH(h,<REG>,<FIELD>)EDMA_getConfig EDMA_FSETH(h,<REG>,<FIELD>,fieldval)
…
See Code Composer Studio help for more See Code Composer Studio help for more details.details.
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004
Chapter 5, Slide 57
S eria lP o rt
EDM A
Sourceaddress
event (internal tim er 1 is selected)
Switch address at the com pletion of atransfer
FFTProcessing
B uffe r (p ing )
Destination address 1
coun t
B u ffe r (pong)
coun t
Destination address 2
Programming the EDMA - CSL ExampleProgramming the EDMA - CSL Example
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004
Chapter 5, Slide 58
CSL programming procedure:CSL programming procedure:(1)(1) Create handles for the EDMA channel and reload parameters:Create handles for the EDMA channel and reload parameters:
(2)(2) Create the EDMA configuration:Create the EDMA configuration:
Programming the EDMA - CSL ExampleProgramming the EDMA - CSL Example
EDMA_Handle hEdma;EDMA_Handle hEdma;
EDMA_Config cfgEdma;EDMA_Config cfgEdma;
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004
Chapter 5, Slide 59
CSL programming procedure (cont):CSL programming procedure (cont):(3)(3) Create the configuration structures for the ping and pong Create the configuration structures for the ping and pong
channels:channels:
Programming the EDMA - CSL ExampleProgramming the EDMA - CSL Example
EDMA_Config cfgEdmaPong = {0x28720002, EDMA_SRC_OF(McBSP0_DRR), EDMA_CNT_OF(BUFF_SZ),
EDMA_DST_OF((unsigned int)cin_data),EDMA_IDX_OF(0x00000004),EDMA_RLD_OF(0x00000000)};};
EDMA_Config cfgEdmaPing = {EDMA_Config cfgEdmaPing = {0x28720002, EDMA_SRC_OF(McBSP0_DRR), EDMA_CNT_OF(BUFF_SZ),
EDMA_DST_OF((unsigned int)in_data),EDMA_IDX_OF(0x00000004),EDMA_RLD_OF(0x00000000)};};
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004
Chapter 5, Slide 60
Programming the EDMA - CSL ExampleProgramming the EDMA - CSL Example
CSL programming procedure (cont):CSL programming procedure (cont):(4)(4) Map the event to a physical interrupt (see Interrupt section):Map the event to a physical interrupt (see Interrupt section):
This maps the EDMA_INT interrupt to CPU_INT8.This maps the EDMA_INT interrupt to CPU_INT8.
(5)(5) Set the interrupt dispatcher configuration structure (see Interrupt section):Set the interrupt dispatcher configuration structure (see Interrupt section):
IRQ_map (IRQ_EVT_EDMAINT, 8);IRQ_map (IRQ_EVT_EDMAINT, 8);
IRQ_configArgs (IRQ_EVT_EDMAINT,IRQ_configArgs (IRQ_EVT_EDMAINT, EdmaIsr,EdmaIsr, 0x00000000,0x00000000, IRQ_CCMASK_DEFAULT,IRQ_CCMASK_DEFAULT, IRQ_IEMASK_ALL);IRQ_IEMASK_ALL);
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004
Chapter 5, Slide 61
Programming the EDMA - CSL ExampleProgramming the EDMA - CSL Example
CSL programming procedure (cont):CSL programming procedure (cont):(6)(6) Open up an EDMA channel associated with the Timer 1 (remember each EDMA is associated with a specific event):Open up an EDMA channel associated with the Timer 1 (remember each EDMA is associated with a specific event):
(7)(7) Allocate the EDMA reload parameters:Allocate the EDMA reload parameters:
Note: -1 means allocate at any available location.Note: -1 means allocate at any available location.
(8)(8) Copy the first reload configuration structure to the EDMA configuration structure:Copy the first reload configuration structure to the EDMA configuration structure:
hEdmaPing = EDMA_allocTable (-1);hEdmaPing = EDMA_allocTable (-1);
hEdmaPong = EDMA_allocTable (-1);hEdmaPong = EDMA_allocTable (-1);
cfgEdma = cfgEdmaPing;cfgEdma = cfgEdmaPing;
hEdma = EDMA_open (EDMA_CHA_TINT1, EDMA_OPEN_RESET);hEdma = EDMA_open (EDMA_CHA_TINT1, EDMA_OPEN_RESET);
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004
Chapter 5, Slide 62
Programming the EDMA - CSL ExampleProgramming the EDMA - CSL Example
CSL programming procedure (cont):CSL programming procedure (cont):(9)(9) Configure the link fields of the configuration structure:Configure the link fields of the configuration structure:
This can be done at stage 3 but in this way we do not know the numerical value of the reload address.This can be done at stage 3 but in this way we do not know the numerical value of the reload address.
(10)(10) Setup the EDMA channel using the configuration structure:Setup the EDMA channel using the configuration structure:
cfgEdmaPing.rld = EDMA_RLD_RMK(0,hEdmaPong);cfgEdmaPing.rld = EDMA_RLD_RMK(0,hEdmaPong);cfgEdmaPong.rld = EDMA_RLD_RMK(0,hEdmaPing);cfgEdmaPong.rld = EDMA_RLD_RMK(0,hEdmaPing);cfgEdma.rld = EDMA_RLD_RMK(0,hEdmaPong);cfgEdma.rld = EDMA_RLD_RMK(0,hEdmaPong);
EDMA_config (hEdmaPing, &cfgEdmaPing); EDMA_config (hEdmaPing, &cfgEdmaPing);
EDMA_config (hEdmaPong, &cfgEdmaPong);EDMA_config (hEdmaPong, &cfgEdmaPong);
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004
Chapter 5, Slide 63
Programming the EDMA - CSL ExampleProgramming the EDMA - CSL Example
CSL programming procedure (cont):CSL programming procedure (cont):(11)(11) Finally initialise all the EDMA registers:Finally initialise all the EDMA registers:
EDMA_RSET (ECR, 0xffff);EDMA_RSET (ECR, 0xffff); // clear all events// clear all events
EDMA_enableChannel(hEdma);EDMA_enableChannel(hEdma);
EDMA_RSET (EER, 0x4);EDMA_RSET (EER, 0x4); // set the timer 1 event enable bit// set the timer 1 event enable bit
EDMA_RSET (CIPR, 0xffff);EDMA_RSET (CIPR, 0xffff);
EDMA_RSET (CIER, 0x4);EDMA_RSET (CIER, 0x4); // make the timer 1 event generate // make the timer 1 event generate
// an EDMA_INT interrupt// an EDMA_INT interrupt
An example CCS project is included in:An example CCS project is included in: Code\Chapter 05 - EDMA\Edma_Inout_StaticcfgCode\Chapter 05 - EDMA\Edma_Inout_Staticcfg
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004
Chapter 5, Slide 64
Programming the EDMA - DSP/BIOS GUIProgramming the EDMA - DSP/BIOS GUI
(3)(3) DSP/BIOS GUI InterfaceDSP/BIOS GUI Interface With this method the configuration structure is created graphically With this method the configuration structure is created graphically
and the setup code is generated automatically.and the setup code is generated automatically.
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004
Chapter 5, Slide 65
Procedure:Procedure:(1)(1) Create a configuration using the EDMA Create a configuration using the EDMA
configuration manager.configuration manager.
Programming the EDMA - DSP/BIOS GUIProgramming the EDMA - DSP/BIOS GUI
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004
Chapter 5, Slide 66
Programming the EDMA - DSP/BIOS GUIProgramming the EDMA - DSP/BIOS GUI
Procedure:Procedure:(2)(2) Right click and select “Properties”, see the figure below, and then Right click and select “Properties”, see the figure below, and then
select “Advanced” and fill all parameters as shown below.select “Advanced” and fill all parameters as shown below.
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004
Chapter 5, Slide 67
Programming the EDMA - DSP/BIOS GUIProgramming the EDMA - DSP/BIOS GUI
Procedure:Procedure:(3)(3) If you are using symbolic parameters such as “in_data” you need to If you are using symbolic parameters such as “in_data” you need to
declare it in the “CSL Extern Declaration”, see below figure.declare it in the “CSL Extern Declaration”, see below figure.
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004
Chapter 5, Slide 68
Programming the EDMA - DSP/BIOS GUIProgramming the EDMA - DSP/BIOS GUI
Procedure:Procedure:(4)(4) A file is then generated that contains the configuration code. The file A file is then generated that contains the configuration code. The file
generated for this example is shown on the next slide.generated for this example is shown on the next slide.
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004
Chapter 5, Slide 69
Programming the EDMA - DSP/BIOS GUIProgramming the EDMA - DSP/BIOS GUI/* Do *not* directly modify this file. It was *//* Do *not* directly modify this file. It was *//* generated by the Configuration Tool; any *//* generated by the Configuration Tool; any *//* changes risk being overwritten. *//* changes risk being overwritten. */
/* INPUT edma_inout_csl.cdb *//* INPUT edma_inout_csl.cdb */
/* Include Header File *//* Include Header File */#include "edma_inout_cslcfg.h"#include "edma_inout_cslcfg.h"
extern far Uint16 McBSP0_DRR;extern far Uint16 McBSP0_DRR;extern far Uint16 in_data[];extern far Uint16 in_data[];extern far Uint16 BUFF_SZ;extern far Uint16 BUFF_SZ;
/* Config Structures *//* Config Structures */EDMA_Config cfgEdmaPing = {EDMA_Config cfgEdmaPing = { 0x28720002, /* Option */0x28720002, /* Option */ 0x018C0000, /* Source Address - Numeric */0x018C0000, /* Source Address - Numeric */ 0x00000002, /* Transfer Counter */0x00000002, /* Transfer Counter */ (Uint32) in_data, /* Destination Address - Symbolic */(Uint32) in_data, /* Destination Address - Symbolic */ 0x00000004, /* Transfer Index */0x00000004, /* Transfer Index */ 0x000001B0 /* Element Count Reload and Link Address */0x000001B0 /* Element Count Reload and Link Address */};};
/* Handles *//* Handles */
/*/* * ======== CSL_cfgInit() ======== * ======== CSL_cfgInit() ======== */*/void CSL_cfgInit()void CSL_cfgInit(){{}}
Chapter 5Chapter 5
Enhanced Direct Memory Access Enhanced Direct Memory Access (EDMA)(EDMA)
- End -- End -