Chapter 4(Complete)

8/17/2019 Chapter 4(Complete)

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Digital Logic Design

Chapter 4


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Combinational Logic

OutlineCombinational Circuits

AnalysisDesign

Binary Adder / Subtractor Multiplier Comparator Encoder / Decoder Multiplexers / Demultiplexers


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Combinational Circuits

RecallSingle/multiple inputs Single output

Many realistic problems use multiple outputsNamed as combinational circuits

Combinational circuitOutput depends only on input(s


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Combinational Circuits

!"at "appens i# $e add memory to t"e circuit%

Becomes a #eedbac& systemSequential Circuits


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Combinational Circuit

AnalysisDetermine t"e #unction o# circuit'nstead o# de eloping t"e circuit based on t"e #unction

Circuit analysisDetermine t"e output #unctions as algebraic expressionsDetermine t"e trut" table o# t"e outputs

!"at is t"e output #unction o# t"is circuit%


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AnalysisAnalysis steps)* +abel all gate outputs $it" symbols,* Determine Boolean #unction at t"e output o# eac" gate-* Express #unctions in terms o# input ariables . simpli#y


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AnalysisAnalysis steps)* +abel all gate outputs $it" symbols,* Determine Boolean #unction at t"e output o# eac" gate-* Express #unctions in terms o# input ariables . simpli#y


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Combinational Circuit Analysis

Substitution

y x y x y x

y y y x y x x x y x y y x x

xy y xy x yT xT

yT xT T T F

yT T

xT T

xyT

⊕=′+′=

′+′+′+′=

′+′+′+′=

′+′=+=

′′′=′=

′=

′=

′=

)()(

)()(

))()(()()(

)(

)(

11

1132

13

12

1


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Combinational Circuit Analysis:Exampl

!"at are t"e outputs ) and , o# t"e #ollo$ing circuit%

0ere

T 2 = ABC T 1 = A+B+C

F 2 = AB + AC + BC

T 3 = F 2 ’ T 1F 1 = T 3 + T 2


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Combinational Circuit Analysis:Exampl

Analysis by trut" table


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Combinational Circuit " sign

Design procedure)* Determine t"e number o# inputs and outputs,* Assign symbols-* Deri e t"e trut" table1* Obtain simpli#ied #unctions #or eac" output2* Dra$ t"e logic diagram

3rut" tables4 input and output columns

Multiple met"ods to sol eBoolean algebra5 map met"ods5 computer aided solution

'ssues to consider Number o# gates6ate inputs7ropagation delayNumber o# interconnections


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Combinational Circuit " sign:Exampl

Design a circuit t"at con erts a BCD digit to Excess8-code


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Design a circuit t"at con erts a BCD digit to Excess8-code

Step )4 'nputs and Outputs'nput4 BCD digit

1 inputs4 A5 B5 C5 D

Output4 Excess8- digit1 outputs4 $5 x5 y5 9

Step ,4 3rut" table


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Step -4 Minimi9e output #unctions


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Step -4 Minimi9e output #unctions


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Step 14 Simpli#icationz = D’ y = CD+C’D’ = CD+(C+D)’

x = B’C+B’D+BC’D’ = B’(C+D)+BC’D’ = B’(C+D)+B(C+D)’ w = A+BC+BD

= A+B(C+D)

Step 24 Circuit Diagram


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Combinational Circuit " sign:ExamplStep 24 Circuit Diagram


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#inary A$$ rs

Addition is important #unction in computer system

!"at does an adder do% Add binary digits6enerate carry i# necessaryConsider carry #rom pre ious computation

Binary adders operate bit8$ise A ):8bit adder uses ): one8bit adders

Binary adders come in t$o #la ors0al# adder adds t$o bits and generates result and carry

ull adder considers carry input in addition to "al# adder 3$o "al# adders ma&e one #ull adder


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#inary %al& A$$ r

SpecificationDesign a circuit t"at adds t$o bits and generates t"e sum and a carry

Input / Output


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#inary %al& A$$ r


Input/Output

3$o inputs4 x, y 3$o output4 S (sum 5 C (carry

Functionality


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#inary %al& A$$ r


Input/Output

3$o inputs4 x, y 3$o output4 S (sum 5 C (carry

Functionality


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#inary %al& A$$ r


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#inary %al& A$$ r


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'ull A$$ r

0al# adder $or&s only #or a single bit!"en multiple bits are in ol ed5 carry bits s"ould be consideredSolution ull adder

Specifications A circuit t"at adds t"ree bits andgenerates sum and carry

Input/output

3"ree inputs4 x5 y5 C in3$o outputs4 S (Sum 5 C out (Carry

Truth table


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'ull A$$ r

0al# adder $or&s only #or a single bit!"en multiple bits are in ol ed5 carry bits s"ould be consideredSolution ull adder

Specifications A circuit t"at adds t"ree bits andgenerates sum and carry

Input/output

3"ree inputs4 x5 y5 C in3$o outputs4 S (Sum 5 C out (Carry

Truth table


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'ull A$$ r

Deri e and minimi9e Boolean expressions


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'ull A$$ r

Deri e and minimi9e Boolean expressions

xyC y x yC xC xyC C y x xyC C y xC y xC y xS

inininout

ininininin

+⊕=++=

⊕⊕=+′′+′′+′′=

)(


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'ull A$$ r

Circuit


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'ull A$$ r &rom %al& A$$ rs

0o$ can t$o "al# adders ma&e a #ull adder%

Obser ations3"ree inputs x5 y5 9 can be added in t$o steps

x+y+z = (x+y) + z

!"at about t"e carry%Carry can occur $"en adding x+y and $"en adding 9

ull adder4 S ; x ⊕ y ⊕ z , C = xy + (x ⊕ y)z


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'ull A$$ r &rom %al& A$$ rs


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#inary n(bit A$$ r

0o$ can $e build an n8bit adder #rom #ull adders%One adder #or eac" bit ( n totalConnect carry to next adder


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)ippl Carry A$$ r

0o$ long does it ta&e to complete an addition%Carry needs to propagate t"roug" circuit > a problem

Speed o# addition is criticalundamental arit"metic operation

0o$ can $e speed up addition%Determine carries a"ead o# time (carry loo&8a"ead


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Carry(Loo*a+ a$ A$$ r

Recallor t"e design o# t"e parallel adder to $or&5 t"e signal must propagate

t"roug" t"e gates be#ore t"e correct output sum is a ailableTotal propagation time = propagation delay of atypical gate x the number of gates

+et


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ull adder4 S i ; A i ⊕Bi ⊕C i , C i+1 = A i .B i + (A i ⊕Bi ).C i Create new signals

G i ; A i .B i carry generate #or stage i

P i = A i⊕ B i carry propagate #or stage i

ull adder e=uations expressed in terms o# G i and P i S i = P i⊕ C i C i+1 = G i + P i C i


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ull adder #unctionality can be expressedrecursi ely

S i = P i⊕ C i

C i+1 = G i + Pi C i

Carry o# eac" stageC = in!"# $a%%y

C 1 = G + P C C 2 = G 1 + P 1C 1 = G 1 + P 1 (G + P C ) = G 1 + P 1G + P 1P C C 3 = G 2 + P 2 C 2 = & = G 2 + P 2 G 1 + P 2 P 1G + P 2 P 1P C C ' = G 3 + P 3G 2 + P 3P 2 G 1 + P 3P 2 P 1G + P 3P 2 P 1P C


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4(bit A$$ r ,it+ CarryLoo*a+ a$

Complete adder Same number o# stages#or eac" bit

Dra$bac&%'ncreasing complexity o#loo&a"ead logic #or morebits


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-ubtraction

0o$ can $e per#orm subtraction%Subtract one number #rom anot"er

Do $e need subtractors% Actually notSubtraction can be done using adders

* = . (,


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-ubtraction

0o$ to ta&e )


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-ubtraction

Same circuit #or Adder and subtractor Can $e do somet"ing %?es

@OR gate x ⊕ ; x (use #or Addition x ⊕ ) ; x’ (use #or Subtraction


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#inary -ubtractor

Adder/Subtractor circuit


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./ r0o,

n8bit addition can generate ( n+1 8bit number Called o er#lo$Needs to be detected by computer system

0o$ can $e detect o er#lo$ in addition%

End carry

Also necessary #or signed numbers or subtractionMost signi#icant bit indicates sign

'# carry into sign position and out o# sign position di##er5 t"en o er#lo$Result $ould be correct $it" extra positionCan be detected by @OR gateCan be used as input carry #or next adder circuit


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./ r0o, Con$itions

O er#lo$ conditions3"ere is no o er#lo$ i# signs are di##erent ( ! s + neg 5 or neg + ! s

O er#lo$ can "appen only $"en bot" numbers "a e same sign5 and'# carry in# sign position and "# o# sign position di##er

Example4 ,


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#C" A$$ r

Add t$o decimal numbers( > .( > .() ; >) don


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#C" A$$ r rut+ abl


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#C" A$$ r rut+ abl


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#C" A$$ r

'# C;)5 need to add : to t"e binary sum0o$ to implement%

Need anot"er adder


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#C" A$$ r


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#C" A$$ r


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ultipli r

7roduct is ) $"en bot" inputs are ) AND gate

,8bit multiplier


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ultipli r

Circuit diagram


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ultipli r

18bit x -8bit multiplier F;-5 G;1

0o$ many AND gatesF x G gates

0o$ many adders(F8) G8bit adders

0o$ many output bitsF . G bits


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agnitu$ Comparator

Need to compare t$o numbers4 A and B AHB5 AIB5 A;B

0o$ can $e determine t"at t$o numbers are e=ual%E=ual i# e ery digit is e=ual

A 3 A 2 A 1 A = B 3 B2 B1 B i# and only i# A 3 = B 3 and A 2 = B 2 and A 1 = B 1 and A =B

!"ic" gate%@NOR (E=ui alence

!"at about A B and A - B %


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agnitu$ Comparator

Case )4 A H B+oo& at most signi#icant bit $"ere A and B di##er

'# A = 1 and B = 5 t"en A - B'# not5 t"en A B

unctionality ( 18bits )'# di##erence in #irst digit4 A - B- <

'# di##erence in second digit4 x-A , B , <Conditional t"at A - ; B - (x - ;) i# 4 A - ;B -

Similar #or all ot"er digits

or A H B(A H B = A - B-


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agnitu$ Comparator

Case ,4 A I Bs$ap A and B #or A - B

unctionality

(A = B) = x 3 x 2 x 1 x (A - B) = A 3B3’+ x 3 A 2 B2 ’ +

x 3 x 2 A 1B1’ + x 3 x 2 x 1 A B ’ (A B) = A 3’B3+ x 3 A 2 ’B2 +

x 3 x 2 A 1’B1 + x 3 x 2 x 1 A ’B

Can be extended to arbitrarynumber o# bits


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.t+ r Arit+m tic #loc*s

Encoders (Enc

Decoders (Dec

Multiplexers (Mux

De8multiplexers (DeMux

3ri8state logic


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oti/ation AL " sign

A+J > Arit"metic and +ogic Jnit Add5 Subtract5 AND5 OR


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oti/ation C " sign

'nstruction Management


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" co$ r

Selects one output based on a binary inputCon erts n8bit code into 2 n outputs5 only one being acti e#or any combination o# inputsSelects output x i# input is binary representation o# x

ApplicationsBinary8to8octal decoder Memory address selection

Selection o# any &ind


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" co$ r: Circuit

!"en is output c"osen%'# x’ y’ z’

!"en is output ) c"osen%'# x’ y’ z

Circuit #or line decoder Se=uence o# mintermsCombine ariables tominterms

$ $ $


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A$/anc $ " co$ r

Sometimes5 you need to acti ate circuitsReason4 3a&e output only $"en re=uiredSolution4 Jse enable pins

Decoder $it" enable6enerates output only $"en acti e8lo$ enable is "ig"

Example4,8to818line decoder $it" enableNAND implementation

$ $ $


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A$/anc $ " co$ r

Enable bit allo$s construction o# large decoders usingsmaller onesExample4 Construct a 18to8): decoder only using -8to8Kdecoders

Acti e8"ig" enable

Can $e use t"is circuitto construct a 28to8-,decoder%

NO Absence o# enable

$ l


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" co$ rs: Exampl

Design a #ull adder using a -8to8K8line decoder 3rut" table

E $


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Enco$ rs

3ranslates 2 n input lines into n output lines'nput4 2 n linesOutput4 n bitsOutput is binary coding o# input t"at is )

3rut" table (n;- (positi e polarityNote4 only one input is allo$ed to be acti e

E $


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Enco$ rs

x ; D 1 . D 2 . D : . D Ly ; D , . D - . D : . D L9 ; D ) . D - . D 2 . D L Can you see any problem "ere%

0o$ many OR gates are re=uired%

E $ bl


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Enco$ rs: robl ms

Only one input can be acti e at a timeSimultaneous acti e inputs result in unde#ined output

!"en all inputs are 9eroE=ual to t"e case $"en D A is )

Example'# D- and D: are acti e simultaneously5 $"at is t"eoutput%)))

0o$ can $e sol e t"is problem%!"at s"ould t"e output be i# multiple lines are acti e%Di##erent solutions4

Any one (random6i e priority to lo$er or "ig"er lines'ndicate in alid input (re=uires extra bit5 /ali0 i# V

x ; D1. D2 .D: . DLy ; D,

. D- .D: . DL9 ; D). D- .D2 . DL

i i E $


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riority Enco$ r

Simple encoder5 $it" additional #unctionality'# multiple inputs are )5 gi e priority to one o# t"em

Example4 18to8) priority encoder $it" priority gi en to one bit

!"ic" bit "as t"e "ig"est priority%D-

i i E $


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riority Enco$ r

alid bit = D + D 1 + D 2 + D 3

i i E $


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riority Enco$ r

Circuit diagram

x = D 2 + D 3y = D 3 + D 1D2 ’

= D + D 1 + D 2 + D 3

lti l


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ultipl x r

Selects #rom ) o# many inputs and directs it to t"e output

Input, n lines

Output) line

Selection may be controlled by select lines

lti l


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ultipl x r

E a!ple,8to8) MJ@

0o$ to design%18to8) MJ@Selection code directs input

4(t (1


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4(to(1

!"at are t"e alues o# ?%

lti l


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ultipl x r

A MJ@ only selects one bit(output

0o$ to select multiple bits(outputs %E a!ple" !"at i# you $ant toc"oose one o# t$o 18bitnumbers%

Solution4 Jse multiple MJ@

uadruple ,8to8) line MJ@

Enable bit sets output to i# )


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s s &or #ool n


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s s &or #ool an'unctions

Example(x5y59 ; Σ ()5,5:5L

3rut" table

s s &or #ool an


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s s &or #ool an


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Example(x5y59 ; Σ ()5-515))5),5)-5)15)2

s s &or #ool an


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s s &or #ool an


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E a!ple"Design a #ull adder using MJ@es

ExpressionsS(x5y59 ; ()5,515L P C(x5y59 ; (-525:5L

s s &or #ool an


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" multipl x r "


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multipl x r

Recei es in#ormation #rom ) input and directs it to one o#2 n possible outputs

'nputData bitn selection lines

Output, n lines

Can be ac"ie ed by decoder circuit $it" enable D acti elo$

Enable D acts as data bit ( disablen code lines act as selection

+r ( tat ri(stat at s


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+r (-tat ri(stat at s

!"at is t"e trut" table #or F %

3"e t$o gates $ill try to dri e F at t"e same timeNot a good idea to $ire t"eir outputs

Sometimes it is necessary to disconnect a gate

3"ree state4 or ) Boolean alue0ig" impedance 5 state

0ig" impedance acts as i# gate $ere disconnected

ultipl x r it+ ri(stat


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ultipl x r ,it+ ri(statat s,8to8) MJ@

18to8) MJ@ $it" Enable

robl ms


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robl ms

robl ms


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robl ms

robl ms


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robl ms

robl ms


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robl ms

robl ms


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robl ms

robl ms


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robl ms

Chapter 4(Complete)

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Transcript of Chapter 4(Complete)