Chapter 4 (Part I) - SUNY New Paltzbai/EGC442/Comp_arch_chp4_5th(1).pdf · Chapter 4 —The...

Chapter 4 — The Processor EGC442 Introduction to Computer Architecture

Division of Engineering Programs, SUNY – New Paltz 1

The Processor

Chapter 4(Part I)

Baback IzadiDivision of Engineering [email protected]

SUNY – New PaltzElect. & Comp. Eng.

SUNY – New PaltzElect. & Comp. Eng. 2

Introduction

CPU performance factors Instruction count Determined by ISA and compiler

CPI and Cycle time Determined by CPU hardware

We will examine two MIPS implementations A simplified version A more realistic pipelined version

Simple subset, shows most aspects Memory reference: lw, sw Arithmetic/logical: add, sub, and, or, slt Control transfer: beq, j

§4.1 Introduction




SUNY – New PaltzElect. & Comp. Eng. 3EGC432 SUNY

New Paltz

3

Two types of functional units: Elements that operate on data values (combinational) ALU

Elements that contain state (sequential) Registers and memory

Abstract / Simplified View

Registers

Register #

Data

Register #

Data

memory

Address

Data

Register #

PC Instruction ALU

Instruction

memory

Address



Instruction Execution PC instruction memory, fetch instruction

Register numbers register file, read registers Depending on instruction class Use ALU to calculate Arithmetic result

Memory address for load/store

Branch target address

Access data memory for load/store

PC target address or PC + 4

Registers

Register #

Data

Register #

Data

memory

Address

Data

Register #

PC Instruction ALU

Instruction

memory

Address





More Detailed CPU Overview



Multiplexers Can’t just join

wires together Use multiplexers





Control



Logic Design Basics

Information encoded in binary Low voltage = 0, High voltage = 1 One wire per bit Multi-bit data encoded on multi-wire buses

Combinational element Operate on data Output is a function of input

State (sequential) elements Store information





Combinational Elements

AND-gate Y = A & B

AB

Y

I0I1

YMux

S

Multiplexer Y = S ? I1 : I0

A

B

Y+

A

B

YALU

F

Adder Y = A + B

Arithmetic/Logic Unit Y = F(A, B)



Sequential Elements Register: stores data in a circuit Uses a clock signal to determine when to update the stored value Edge-triggered: update when Clk changes from 0 to 1

D

Clk

QClk

D

Q





Sequential Elements Register with write control Only updates on clock edge when write control input is 1 Used when stored value is required later

D

Clk

Q

Write

Write

D

Q

Clk



Clocking Methodology Combinational logic transforms data during clock cycles Between clock edges Input from state elements, output to state element Longest delay determines clock period





Building a Datapath

Datapath Elements that process data and addresses in the CPU Registers, ALUs, mux’s, memories, …

We will build a MIPS datapath incrementally Refining the overview design

§4.3 Building a D

atapath



Abstraction

Make sure you understand the abstractions!

Sometimes it is easy to think you do, when you don’t

Mux

C

Select

32

32

32

B

A

Mux

Select

B31

A31

C31

Mux

B30

A30

C30

Mux

B0

A0

C0

......





Register File

Read operation using D flip-flops and MUX’s

Read registernumber 1 Read

data 1Read registernumber 2

Readdata 2

Writeregister

WriteWritedata

Register file

Readregisternumber1

Register0

Register1

.. .

Registern–2

Registern–1

Mux

Readregisternumber2

Mux

Readdata1

Readdata2

What is the function of “Mux” above?



Register File – Read and Write

M u

x

Register 0

Register 1

Register n – 1

Register n

M

u x

Read data 1

Read data 2

Read register number 1

Read register number 2

Read registernumber 1 Read

data 1Read registernumber 2

Readdata 2

Writeregister

WriteWritedata

Register file

n-to-1decoder

Register0

Register1

Registern– 1C

C

D

DRegistern

C

C

D

D

0

1

n– 1

n

Write

Write Register

Write Data

How many registers can we read and write at the same time?

Does this support MIPS instructions requirements?





Building the Datapath Include the functional units we need for each instruction

Use multiplexors to stitch them together

ALU Control:000 AND001 OR010 add110 subtract111 set-on-less-than

A LU control

RegW rite

Reg is te rsW riteregister

Readdata 1

Readdata 2

Readregister 1

Readregister 2

W rited ata

ALUresu lt

ALU

Data

Data

R eg is ter

num bers

a . Registers b. A LU

Zero

5

5

5 3

PC

Instruction

memory

Instructionaddress

Instruction

a. Instruction memory b. Program counter

Add Sum

c. Adder

16 32Sign

extend

b. Sign-extension unit

MemRead

MemWrite

Data memory

Write data

Read data

a. Data memory unit

Address



Instruction Fetch

32-bit register

Increment by 4 for next instruction





R-Format Instructions Read two register operands

Perform arithmetic/logical operation

Write register result

ALU control

R eg W rite

R egistersW riteregister

R e add ata 1

R e add ata 2

R e adregister 1

R e adregister 2

W rited ata

ALUresult

ALU

D ata

D ata

R egisternum bers

a . R egisters b. ALU

Z e ro5

5

5 3



R-Format Instructions Read two register operands

Perform arithmetic/logical operation

Write register result

ALU control

R egW rite

R egiste rsW ritere gister

R e addata 1

R e addata 2

R e adre gister 1

R e adre gister 2

W ritedata

ALUresult

ALU

Ze ro

3

Instruction





Load/Store Instructionslw $t1, offset_value($t2) or sw $t1, offset_value ($t2) Read register operands Calculate address using 16-bit offset Use ALU, but sign-extend offset

Load: Read memory and update register Store: Write register value to memory



Datapath for lw and sw Insturctions

lw $t1, offset_value($t2) or sw $t1, offset_value ($t2) Compute memory address Sign extend 16 bit to 32 bit

16 32

Registers

W rite

register

W rite

data

Read

data 1

Read

data 2

Read

register 1

Read

register 2

ALU operation3

RegW rite

MemRead

M emW rite

ALU

result

Z ero

ALU

D ata

memory

Address

W rite

da ta

Rea

data

Sign

extend

Instruction





Branch Instructions

beq $t1, $t2, offset Read register operands

Compare operands Use ALU to compare registers,

Use ALU to affect Z flag If not equal, next PC <= PC +4 (Already calculated by instruction

fetch)

If equal, Calculate target address Sign-extend displacement Shift left 2 places (word displacement) Add to PC + 4

Instruction

16 32

Add ALUresult

Registers

WriteregisterWritedata

Readdata 1

Readdata 2

Readregister 1Readregister 2

Shiftleft 2

ALU operation3

RegWrite

ZeroALU

Signextend

PC + 4

Branch control

Next instruction address



Branch InstructionsJust

re-routes wires

Sign-bit wire replicated





Composing the Elements

First-cut data path does an instruction in one clock cycle Each datapath element can only do one function at a time Hence, we need separate instruction and data memories

Use multiplexers where alternate data sources are used for different instructions



R-Type/Load/Store Datapath





Full Datapath



28

• R-Type Instruction

op rs rt rd shamt funct

rd: destination

•Load and Store Instructions

op rs rt 16 bit offset

rt: destination

•Branch Instruction


rt: destination

Three Instruction Classes





Completed Data Path

MemtoRegPC

Instructionmemory

Readaddress

Instruction[31–0]

Instruction [20–16]


Add

4

16 32Instruction [15–0]

0

0Mux

0

1

Add ALUresult

Mux

0

1

RegistersWriteregister

Writedata

Readdata 1

Readdata 2

Readregister 1

Readregister 2

Signextend

Shiftleft 2

Mux

1

ALUresult

Zero

Datamemory

Writedata

Readdata

Mux

1


ALUAddress

RegWrite

ALUSrc

MemRead

RegDst

MemWrite

PCSrc

ALU Control



The Main Control Unit Control signals derived from instruction

0 rs rt rd shamt funct

31:26 5:025:21 20:16 15:11 10:6

35 or 43 rs rt address

31:26 25:21 20:16 15:0

4 rs rt address

31:26 25:21 20:16 15:0

R-type

Load/Store

Branch

opcode always read

read, except for load

write for R-type

and load

sign-extend and add





Datapath With Control



R-Type Instruction





Load Instruction



Branch-on-Equal Instruction





Control

Using the op-code from the instruction, the control issues signals to:

Selecting the operations to perform (ALU, read/write, etc.)

Controlling the flow of data (multiplexer inputs)

ALU's operation based on instruction type and function code

Example: what should the ALU do with the instruction

add $8, $17, $18

000000 10001 10010 01000 00000 100000

op rs rt rd shamt funct



Control

Example: what should the ALU do with the instruction

lw $1, 100($2)

35 2 1 100


Why is the ALU code for subtract is 110 and not 011?





Must describe hardware to compute 3-bit ALU control input Given instruction type

00 = lw, sw01 = beq, 11 = arithmetic

Function code for arithmetic

ALU Control

ALUOp Funct field OperationALUOp1 ALUOp0 F5 F4 F3 F2 F1 F0

0 0 X X X X X X 010 add0 1 X X X X X X 110 sub1 1 (X) X X 0 0 0 0 010 add1 1 (X) X X 0 0 1 0 110 sub1 1 (X) X X 0 1 0 0 000 and1 1 (X) X X 0 1 0 1 001 or1 1 (X) X X 1 0 1 0 111 slt

ALU Control:000 AND001 OR010 add110 subtract111 set-on-less-than

ALUOp

computed from instruction type



ALU Control

Operation2

Operation1

Operation0

Operation

ALUOp1

F3

F2

F1

F0

F (5–0)

ALUOp0

ALUOp

ALUcontrol blockMuli-level decoding can reduce size of control unit and increase its speed.

ALUOp Funct field OperationALUOp1 ALUOp0 F5 F4 F3 F2 F1 F0 2 1 0

0 0 X X X X X X 010 add0 1 X X X X X X 110 sub1 0 X X 0 0 0 0 010 add1 0 X X 0 0 1 0 110 sub1 0 X X 0 1 0 0 000 and1 0 X X 0 1 0 1 001 or1 0 X X 1 0 1 0 111 slt

Inputs Outputs





A Simple Control

P C

Instru ction

me mory

Readaddress

Ins truc tion[31– 0 ]

Instruction [2 0– 16]


A dd

In struction [5– 0]

4

16 3 2Instruction [1 5– 0]

0

0Mux

0

1

AddALU

resu lt

Mux

0

1

Regis tersW ritereg ister

W rited a ta

Readda ta 1

Readda ta 2

R ea dreg ister 1

R ea dreg ister 2

Sign

extend

S hift

le ft 2

Mux

1

ALUresult

Zero

Da ta

m em o ryW ritedata

Readdata

Mux

1


A LU

co ntrol

A LU

Ad dress

RegWrite

ALUSrc

ALUop

MemRead

MemtoReg

RegDst

MemWrite

PCSrc



Control

Instruction Opcode RegDst ALUSrcMemto-

RegReg

WriteMem Read

Mem Write Branch ALUOp1ALUOp0

R-format 00 0000 1 0 0 1 0 0 0 1 0lw 10 0011 0 1 1 1 1 0 0 0 0sw 10 1011 X 1 X 0 0 1 0 0 0beq 00 0100 X 0 X 0 0 0 1 0 1

PC

Instruction memory

Read address

Instruction [31– 0]



Add


MemtoReg

ALUOp

MemWrite

RegWrite

MemRead

BranchRegDst

ALUSrc


4

16 32Instruction [15– 0]

0

0M u x

0

1

Control

Add ALU result

M u x

0

1

RegistersWrite register

Write data

Read data 1

Read data 2

Read register 1

Read register 2

Sign extend

Shift left 2

M u x

1

ALU result

Zero

Data memory

Write data

Read data

M u x

1


ALU control

ALUAddress





Single Cycle Control

Simple combinational logic

Operation2

Operation1

Operation0

Operation

ALUOp1

F3

F2

F1

F0

F (5–0)

ALUOp0

ALUOp

ALUcontrol block

R-format Iw sw beq

Op0Op1Op2Op3

Op4Op5

Inputs

Outputs

RegDst

ALUSrc

MemtoReg

RegWrite

MemRead

MemWrite

Branch

ALUOp1

ALUOpO



All of the logic is combinational

We wait for everything to settle down, and the right thing

to be done

ALU might not produce “right answer” right away

we use write signals along with clock to determine when to write

Cycle time determined by length of the longest path

Our Simple Control Structure

Clock

Combinational logicContent

of PCContent

of PC





Single Cycle Implementation

Calculate cycle time assuming negligible delays except: memory (200ps), ALU and adders (200ps), register file access (100ps)

MemtoReg

MemRead

MemWrite

ALUSrc

RegDst

PC

Instructionmemory

Readaddress

Instruction[31–0]

Instruction[20–16]


Add

Instruction[5–0]

RegWrite

4

16 32Instruction[15–0]

0Registers

WriteregisterWritedata

Writedata

Readdata 1

Readdata 2

Readregister1Readregister2

Signextend

ALUresult

Zero

Datamemory

Address Readdata M

ux

1

0

Mux

1

Mux

1

0

Mux

1


Shiftleft2

PCSrc

ALU

Add ALUresult

ALUOp

0

ALUcontrol



Single Cycle Implementation Calculate cycle time assuming negligible delays except: memory (2ns), ALU and adders (2ns), register file access (1ns)

M e m to R e g

M e m R e a d

M e m W r i te

A L U O p

A L U S rc

R e g D s t

P C

I n s t ru c t io n m e m o ry

R e a d a d d re s s

In s tru c t io n [3 1 – 0 ]

In s tr u c t io n [2 0 – 1 6 ]

In s tr u c t io n [2 5 – 2 1 ]

A d d

In s tru c t io n [5 – 0 ]

R e g W r i te

4

1 6 3 2In s tr u c t io n [1 5 – 0 ]

0R e g is t e rs

W r ite re g is te rW r ite d a ta

W r i te d a ta

R e a d d a ta 1

R e a d d a ta 2

R e a d re g is te r 1R e a d re g is te r 2

S ig n e x te n d

A L U re s u l t

Z e r o

D a ta m e m o ry

A d d re s s R e a d d a ta

M u x

1

0

M u x

1

0

M u x

1

0

M u x

1

In s tr u c t io n [1 5 – 1 1 ]

A L U c o n t ro l

S h i f t l e f t 2

P C S rc

A L U

A d d A L U re s u lt

InstructionInstr.

MemoryRegister

ReadALU Op.

Data Memory

Reg. Write Total

R-format 200ps 100ps 200ps 0 100ps 600pslw 200ps 100ps 200ps 200ps 100ps 800pssw 200ps 100ps 200ps 200ps 700psbeq 200ps 100ps 200ps 500ps





Implementing Jumps

Jump uses word address

Update PC with concatenation of Top 4 bits of old PC 26-bit jump address 00

Need an extra control signal decoded from opcode

2 address

31:26 25:0

Jump



Datapath With Jumps Added





Performance Issues

Longest delay determines clock period Critical path: load instruction

Instruction memory register file ALU data memory register file

Not feasible to vary period for different instructions

Violates design principle Making the common case fast

We will improve performance by pipelining

Chapter 4 (Part I) - SUNY New Paltzbai/EGC442/Comp_arch_chp4_5th(1).pdf · Chapter 4 —The...

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Transcript of Chapter 4 (Part I) - SUNY New Paltzbai/EGC442/Comp_arch_chp4_5th(1).pdf · Chapter 4 —The...