CHAPTER 4 Combinational Logic Design – Design Procedure, Encoders/Decoders (Sections 4.3 – 4.4)

CHAPTER 4CHAPTER 4

Combinational Logic Design – Combinational Logic Design – Design Procedure, Encoders/Decoders Design Procedure, Encoders/Decoders

(Sections 4.3 – 4.4)(Sections 4.3 – 4.4)

DecodersDecoders

A combinational circuit that converts binary A combinational circuit that converts binary information from information from nn coded inputs to a coded inputs to a maximum 2maximum 2n n coded outputs coded outputs n-to- n-to- 22nn decoderdecoder

n-to-mn-to-m decoder, decoder, m m ≤ ≤ 22nn Examples: BCD-to-7-segment decoder, where Examples: BCD-to-7-segment decoder, where

n=4n=4 and and m=10 m=10

Decoders (cont.)Decoders (cont.)


Y0=(G’B’A’)’=G+B+A

Y1=(G’B’A)’=G+B+A’

Y2=(G’BA’)’=G+B’+A

Y3=(G’BA)’=G+B’+A’

74XX139 decoder


Y0=(G’B’A’)’=G+B+A

Y1=(G’B’A)’=G+B+A’

Y2=(G’BA’)’=G+B’+A

Y3=(G’BA)’=G+B’+A’

3-3-to-8 Decoder (cont.)to-8 Decoder (cont.)

Three inputs, AThree inputs, A00, A, A11, A, A22, are decoded into eight , are decoded into eight outputs, Youtputs, Y0 0 through Ythrough Y77

Each output YEach output Yii represents one of the minterms represents one of the minterms of the 3 input variables.of the 3 input variables.

YYii = 1 when the binary number A = 1 when the binary number A22AA11AA00 = = ii Shorthand: YShorthand: Yii = m = mii

The output variables are The output variables are mutually exclusivemutually exclusive; ; exactly one output has the value 1 at any time, exactly one output has the value 1 at any time, and the other seven are 0.and the other seven are 0.

Implementing Boolean functions Implementing Boolean functions using decodersusing decoders

Y0’=(C’B’A’)’=m0’

Y1’=(C’B’A)’=m1’

Y2’=(C’BA’)’=m2’

Y3’=(C’BA)’=m3’

Y4’=(CB’A’)’=m4’

Y5’=(CB’A)’=m5’

Y6’=(CBA’)’=m6’

Y7’=(CBA)’=m7’


E.g. use 74XX138,3-to-8 decoder to implement E.g. use 74XX138,3-to-8 decoder to implement boolean functionsboolean functions

Y1=A’B’+AC+A’C’

Y2=A’C+AC’

Y3=B’C+BC’


Y1=A’B’+AC+A’C’=m0+m1+m2+m5+m7

= (m0’m1’m2’m5’m7’)’

Y2=A’C+AC’= m1+m3+m4+m6

= (m1’m3’m4’m6’)’

Y3=B’C+BC’=m1+m2+m5+m6

= (m1’m2’m5’m6’)’


Y1= (m0’m1’m2’m5’m7’)’

Y2= (m1’m3’m4’m6’)’

Y3= (m1’m2’m5’m6’)’

0

1

2

3456

7

C

B

A

1

BIN/OCT74LS138

&EN

Y1

Y2

Y3


Y1=A’B’+AC+A’C’=m0+m1+m2+m5+m7

=∑(0,1,2,5,7)

=∏(3,4,6)=M3M4M6=m3’m4’m6’

Y2=A’C+AC’= m1+m3+m4+m6

=m0’m2’m5’m7’

Y3=B’C+BC’=m1+m2+m5+m6

=m0’m3’m4’m7’


0

1

2

3456

7

C

B

A

1

BIN/OCT74LS138

&EN

Y1

Y2

Y3

Y1=m3’m4’m6’

Y2=m0’m2’m5’m7’

Y3=m0’m3’m4’m7’


e.g. X=f(a,b,c)=∑(0,3,5,6,7)e.g. X=f(a,b,c)=∑(0,3,5,6,7)

=a’b’c’+ab+bc+ac=a’b’c’+ab+bc+ac 0

1

2

3456

7

C

B

A

1

BIN/OCT74LS138

&EN

X.L

0

1

2

3456

7

C

B

A

1

BIN/OCT74LS138

&EN

X.L

Here is another example:Here is another example:Recall full adder equations, and let X, Y, Recall full adder equations, and let X, Y, and Z be the inputs:and Z be the inputs: S(X,Y,Z) = S(X,Y,Z) = m(1,2,4,7) m(1,2,4,7) CC (X,Y,Z) = (X,Y,Z) = m(3, 5, 6, 7).m(3, 5, 6, 7).

Since there are 3 inputs and a total of 8 Since there are 3 inputs and a total of 8 minterms, we need a 3-to-8 decoder.minterms, we need a 3-to-8 decoder.


Implementing a Binary Adder Using a Decoder

S(X,Y,Z) = Σm(1,2,4,7)

C(X,Y,Z) = Σm(3,5,6,7)

Exe. Using decoders realize functionsExe. Using decoders realize functions

A=f(x,y,z)=∏(0,1,3,5)A=f(x,y,z)=∏(0,1,3,5)

G=f(x,y,z)=∑(0,1,2,4,5,6,7)G=f(x,y,z)=∑(0,1,2,4,5,6,7)



A=f(x,y,z)=∏(0,1,3,5)A=f(x,y,z)=∏(0,1,3,5)


G=f(x,y,z)=∑(0,1,2,4,5,6,7)

=∏(3)

Decoder ExpansionsDecoder Expansions

Larger decoders can be constructed using a Larger decoders can be constructed using a number of smaller ones.number of smaller ones.

HIERARCHICAL design!HIERARCHICAL design! Example:Example:

A 6-to-64 decoder can be designed using four A 6-to-64 decoder can be designed using four 4-to-16 and one 2-to-4 decoders. How? (Hint: 4-to-16 and one 2-to-4 decoders. How? (Hint: Use the 2-to-4 decoder to generate the enable Use the 2-to-4 decoder to generate the enable signals to the four 4-to-16 decoders).signals to the four 4-to-16 decoders).


Two 74XX138 decoders forming a single 4-to-16 decoder(P131)


A 5-to-32 decoder using one 2-to-4 and four 3-to-8 decoder ICs(P132)


E.g. Using two E.g. Using two 74XX138 decoders to 74XX138 decoders to realize a four-variable realize a four-variable multiple output multiple output function(P133)function(P133)

P=f(w,x,y,z)=∑(1,4,8,13)

Q=f(w,x,y,z)=∑(2,7,13,14)

EncodersEncoders

An encoder is a digital circuit that performs An encoder is a digital circuit that performs the inverse operation of a decoder. An the inverse operation of a decoder. An encoder has 2encoder has 2nn input lines and input lines and nn output lines. output lines.

The output lines generate the binary equivalent The output lines generate the binary equivalent of the input line whose value is 1.of the input line whose value is 1.

Encoders (cont.)Encoders (cont.)

Encoder ExampleEncoder Example Example: 8-to-3 binary encoder (octal-to-binary)Example: 8-to-3 binary encoder (octal-to-binary)

A0 = D1 + D3 + D5 + D7

A1 = D2 + D3 + D6 + D7

A2 = D4 + D5 + D6 + D7

Encoder Example (cont.)Encoder Example (cont.)

Priority EncodersPriority Encoders

Multiple asserted inputs are allowed; one has Multiple asserted inputs are allowed; one has priority over all others.priority over all others.

Example: 4-to-2 Priority EncoderExample: 4-to-2 Priority EncoderTruth TableTruth Table

8-8-to-3 Priority Encoderto-3 Priority Encoder

A priority encoder

Uses of priority encoders (cont.)Uses of priority encoders (cont.)

HomeworkHomework

P178: 17.3, 17.4, 17.7, 17.8P178: 17.3, 17.4, 17.7, 17.8

CHAPTER 4 Combinational Logic Design – Design Procedure, Encoders/Decoders (Sections 4.3 – 4.4)

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Transcript of CHAPTER 4 Combinational Logic Design – Design Procedure, Encoders/Decoders (Sections 4.3 – 4.4)