CHAPTER 3 PRINCIPLES AND ANALYSES OF CONTROL...
Transcript of CHAPTER 3 PRINCIPLES AND ANALYSES OF CONTROL...
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CHAPTER 3
PRINCIPLES AND ANALYSES OF CONTROL
STRATEGIES FOR THE DSTATCOM
3.1 INTRODUCTION
The Indian economy has been growing at a fast pace since the
beginning of this millennium. Foreign direct investments in India by many
leading multinational organizations, especially in automobile manufacturing
and information technology, have resulted in an accelerated need for
additional power. Hence, there is a need for rapid growth of the power
generation sector. However, due to constraints in the availability of fuel and
environmental concerns, the power generation sector has not kept pace with
other industrial sectors. One way of increasing the power availability is by
reducing the high losses in the existing power transmission and distribution
systems. In addition, there is a demand for high quality power from customers
for custom power devices. Compensation for reactive power and unbalance in
the power distribution system are key factors in improving the power quality
to the end user. Excessive reactive power in the system increases feeder losses
and reduces the active power flow capability of the distribution system
whereas unbalance affects the operation of generators and transformers in the
system.
A Distribution STATic COMpensator (DSTATCOM), a custom
power device, connected in shunt with the load, compensates for the reactive
power and unbalance caused by various loads in the distribution system. The
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performance of the DSTATCOM depends on the control algorithm used for
extracting the reference current components. In this chapter, the working
principle of a DSTATCOM is explained and its mathematical model is
derived. The control techniques for voltage regulation, power factor
improvement and compensation of unbalanced systems, for a DSTATCOM,
are described.
3.2 WORKING PRINCIPLES
A DSTATCOM is a shunt compensation device that provides an
effective solution for reactive power compensation and voltage regulation. It
comprises of a Voltage Source Converter (VSC), a DC capacitor, a coupling
inductor or coupling transformer and a controller, as shown in Figure 3.1.
Figure 3.1 Basic structure of a DSTATCOM
The DSTATCOM, connected to the grid through the coupling
inductor at the point of common coupling (PCC), is controlled in such a way
that it exchanges only reactive power with the grid. This is achieved by
injecting the current in quadrature with the grid voltage. If the magnitude of
the DSTATCOM voltage is greater than the grid voltage ( > ), the
DSTATCOM supplies reactive power to the grid, as shown in Figure 3.2a,
VSC
Sensitive Load
Interface Distribution
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and the DSTATCOM is operating in the capacitive mode. If the grid voltage
is greater than the DSTATCOM voltage ( > ), the DSTATCOM
absorbs reactive power from the grid, as shown in Figure 3.2b, and the
DSTATCOM is operating in the inductive mode. If the grid voltage and
the DSTATCOM voltage are of the same magnitude ( = ), there is no
exchange of reactive power between the grid and the DSTATCOM, as shown
in Figure 3.2c, and the DSTATCOM is operating in the floating state.
Figure 3.2 DSTATCOM operating modes
In addition, the DSTATCOM can be operated to exchange real
power with the grid by controlling the phase angle of the DSTATCOM’s
output voltage. In this thesis, the DSTATCOM operates in the reactive power
compensation mode only. In this mode, the DSTATCOM operates in such a
way that there is no phase angle difference between the DSTATCOM output
voltages and the grid voltages. Hence, the DSTATCOM neither supplies nor
absorbs real power.
3.3 MATHEMATICAL MODELLING OF A DSTATCOM
In the literature, the state space modeling of a DSTATCOM is
carried out in the synchronous reference frame (Bowes & Lai 1997, Mehdi &
Mahmud 2007 and Masand et al 2008). Figure 3.3 shows the simplified single
line diagram of a DSTATCOM. It consists of a DC link capacitor, an IGBT
based VSC, a filter and a voltage source to represent the grid voltage. The
a. Capacitive mode b. Inductive mode c. Floating state
Vc
IC
IC
Vs Vc
Vs
Vs
Vc
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DSTATCOM is connected through a filter circuit to the grid at the point of
common coupling (PCC).
Figure 3.3 Simplified single-line diagram of the DSTATCOM
The three-phase instantaneous voltages at the PCC are given by
Equations (3.1) to (3.3).
vsa= 23
Vs sin t (3.1)
vsb= 23
Vs sin t -3
(3.2)
vsc= 23
Vs sin t+3
(3.3)
These three-phase voltages can be expressed in the matrix form as
Equation (3.4).
vsavsbvsc
= 23
Vs
sin tsin t
3
sin t+3
(3.4)
The relationship between the PCC voltages, the inverter output
voltages and currents are obtained by writing the KVL equation for the Figure
3.3 and are given by Equations (3.5) to (3.7).
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Rfia+Lfdiadt
= vsa vca (3.5)
Rfib+Lfdibdt
= vsb vcb (3.6)
Rfic+Lfdicdt
= vsc vcc (3.7)
Equations (3.5) to (3.7) can be written in the matrix form as Equation (3.8).
ddt
iaibic
=Rf/Lf 0 00 Rf/Lf 00 0 Rf/Lf
iaibic
+ 1Lf
vsa vcavsb vcbvsc vcc
(3.8)
Equations (3.5) to (3.7) describe the system differential equations in
the abc reference frame. To control the current injected by the VSC, the
transformation of these equations to the synchronous reference frame is
required. The Park’s transformation is used for transforming from the abc
reference frame to the synchronous qd0 reference frame. As the system is
assumed a balanced, only d and q components exist. The transformed results
in the dq frame are given by Equations (3.9) and (3.10).
Rfid+Lfdiddt
= vsd m Vdccos +Lf iq (3.9)
Rfiq+Lfdiqdt
= vsq+m Vdcsin f id (3.10)
Equation (3.11) is the matrix form representation of Equations (3.9)
and (3.10).
ddt
idiq =
Rf/LfRf/Lf
idiq + 1
Lf
vsd vcdvsq+vcq
(3.11)
Neglecting the voltage harmonics produced by the direct and the
quadrature axes voltages, we get Equations (3.12) and (3.13).
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vcd=mVdccos (3.12)
vcq=mVdcsin (3.13)
According to the power balance theory, the instantaneous power at
the AC terminals of the inverter is equal to the instantaneous power at the DC
terminals of the inverter. Equation (3.14) gives the power balance equation.
vdcidc=32
vcdid+vcqiq (3.14)
Equation (3.15) gives the current in the DC side of the
DSTATCOM.
idc=32
m idcos +iqsin = C dVdc
dt (3.15)
From Equations (3.11) to (3.15), the DSTATCOM’s state space
mathematical model can be written as Equation (3.16)
ddt
idiq
Vdc
=Aidiq
Vdc
1Lf
vsd00
(3.16)
where A is given by,
A=
Rf/LfmLf
cos
Rf/LfmLf
sin
32
mC
cos32
mC
sin 0
Since the d and q axes are not stationary, they follow the trajectory
of the voltage vector (Masand et al 2008). In the synchronous rotating frame
= and = 0. Hence, considering these conditions, Equations (3.17)
and (3.18) give the instantaneous active and reactive powers.
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p= 32
vsdid+vsqiq = 32
vsdid = 32vsid (3.17)
q= 32
vsqid vsdiq = 32
vsdid = 32
vsiq (3.18)
By observing the right hand side (RHS) of Equations (3.17) and
(3.18), the performance of the DSTATCOM can be controlled by controlling
the active and reactive components of currents, namely and (Giroux et
al 2001, Voraphonpiput & Chatratana 2005, Elnady & Salama 2005 and Wen
et al 2007). The control algorithm developed in the synchronous reference
frame should control the d or the q component of the current to attain the
control objective.
3.4 DSTATCOM CONTROLLER PRINCIPLES
The use of power electronics based apparatus in electrical power
systems, at various voltage levels, is becoming increasingly widespread due to
the rapid progress of power electronic technology. The STATCOM is one
such apparatus that can potentially be used in the context of flexible AC
transmission systems (FACTS) at the transmission level (Garica-Gonzalez &
Garcia-Cerrada 2000, Sen Sarma et al 2000 and Rao et al 2000). The
Distribution STATCOM (DSTATCOM) is a custom power device working on
the STATCOM principle at the distribution level. This device can also be used
at the end users’ electrical installations (Sen Sarma et al 2001, Woo et al 2001
and Molavi et al 2012). Potential applications at the distribution level include
voltage regulation, power factor correction, load balancing, and harmonic
filtering.
This chapter gives an overview of the DSTATCOM control
principles for different modes of operation. The DSTATCOM has a voltage
source converter (VSC) at its core that can be used for different application by
appropriate control algorithms. The DSTATCOM is simulated for voltage
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regulation application using the PI controlled SPWM algorithm and the
SVPWM algorithm. In this simulation study, a two-level VSC is used to
realize the DSTATCOM. The bus voltage is regulated either by absorbing or
by supplying reactive power to the bus. The performance of the DSTATCOM
is studied for the SPWM and the SVPWM algorithms for voltage regulation
application.
Figure 3.4 represents the distribution system where the
DSTATCOM is connected in shunt to the system through a star-delta
transformer at the PCC. The distribution bus is represented by a Thevinin’s
equivalent voltage G and a Thevinin’s equivalent impedance and is connected
to the distribution line. Three different loads are connected to the system
through a transformer at bus B4. The required voltage at the PCC is 1 pu as
per the grid requirement (IEEE standard 519, 1992). The voltage profile at the
PCC is affected by rapid changes in the load. The voltage at the PCC is
maintained at 1 pu by appropriate control of the DSTATCOM. To mitigate
the effects of the voltage sag or swell, a synchronous frame based PI
controller is used to control a two-level VSC. The system is simulated in
MATLAB using Simulink power system blockset.
The DSTATCOM consists of a VSC unit, a DC capacitor and a
coupling inductor or transformers. The VSC in the DSTATCOM converts the
voltage across the capacitor into a set of three-phase voltages. These voltages
are in phase with the AC system voltage and the DSTATCOM is coupled
with the AC distribution system through the leakage reactance of the coupling
transformer.
The variations of the load and the source voltage also affect the bus
voltages, which in turn affect sensitive loads connected to the bus. The
performance of the DSTATCOM for the regulation of bus voltage due to the
source voltage variation using SPWM method is described in the literature
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(Saccomando 2000, Rao et al 2000, Giroux et al 2001 and Singh et al 2004).
A PI controller can be used in the cascade control mode to regulate the AC
bus voltages and the DC capacitor voltage. The VSC based DSTATCOM,
connected in shunt with the AC system, can be used for voltage regulation or
power factor correction or elimination of current harmonics (Miller 1982,
Miller et al 2000 and Muyeen et al 2009).
Figure 3.4 Schematic of a DSTATCOM
The cascade controller for the voltage regulation application is
shown in Figure 3.5. For voltage regulation, two voltages are controlled in the
DSTATCOM. One is the AC voltage of the power system at the bus, where
the DSTATCOM is connected, and the other is the DC link voltage across the
capacitor. Both the regulators are of the proportional integral (PI) type. The
output current from the VSC is converted into the d-axis and the q-axis
components using the Park’s transformation technique.
Distribution Line
FeederLine
Y
Y
VSC
C
LOAD1
LOAD2
LOAD3
G
PCC
DSTATCOM
B3 B2 B1 B4
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Figure 3.5 Block diagram for the complete control of the DSTATCOM
The error or the difference between _ and is regulated
through a PI controller to get _ . The _ is obtained by regulating the
error due to _ (pu) and (pu) signals by another PI controller.
These reference currents are then regulated by comparing the d and q
components of currents with their respective components of reference current
in another set of PI regulators, whose outputs are the d-axis and q-axis control
voltages for the DSTATCOM. The voltage magnitude and phase angle are
computed from and , as given in Equations (3.16) and (3.17). The
computed voltage magnitude and phase angle are used to generate the three-
phase sinusoidal reference signals, without the use of inverse Park’s
transformation, to reduce the computation time, as given in Equations
(3.18) to (3.20).
= | | ( + )
= | | +
= | | + +
PWM module (OR)SVPWM module
abc dq | |
| |
PI
PI
PI
abc
|V|= Vd2+Vq
2
= tan-1 Vq
Vd
| |
+
_
+_
_
+
_
PCC
sin / cos
, ,
VSC
PLL
CT
PT
, ,
Pulses (P1 – P6)
Y
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|V|= Vd2+Vq
2 (3.16)
= tan-1 Vq
Vd (3.17)
Va= |V| sin( t + ) (3.18)
Vb= |V| sin t-3
(3.19)
Vc= |V| sin t +3
(3.20)
These reference signals are compared with a sawtooth wave to
generate the SPWM signals in the SPWM module. With the same reference
signal, the switching pulses are generated by the SVPWM algorithm in the
SVPWM module. The performance of the DSTATCOM is studied for the
voltage regulation application using the SPWM and the SVPWM switching
strategies. The principles of the SVPWM switching strategy are explained in
the section 3.5.
3.5 SPACE VECTOR PWM PRINCIPLES
The SVPWM method is an advanced, computation intensive PWM
technique and the literature says that it is the best among all the PWM
techniques, for digital implementation, in variable frequency drive
applications (Jin-Woo Jung 2005, Iqbal et al 2006, Iqbal et al 2010 and Zhang
et al 2010). The SVPWM method considers the interaction of the phases and
optimizes the harmonic content of the three-phase isolated neutral load. The
principle of the SVPWM is explained with respect to an inverter unit of the
DSTATCOM as a standalone VSC supplied by a DC voltage source , as
shown in Figure 3.6. The three-phase bridge inverter has eight permissible
switching states in which six are active states and two are zero states. When
the voltage is impressed across the load, the inverter is in active state (V1 to
V6) and when the load terminals are shorted through the lower or upper
switches, the inverter is in the zero state (V0 or V7).
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Figure 3.6 Three-phase voltage source inverter
The relationship between the switching variable vectors [S1 S2 S3]T
and the line-to-line voltage vectors [VAB VBC VCA]T is given by
Equation (3.21).
VABVBCVCA
=Vdc
1 -1 00 1 -1-1 0 1
S1S2S2
(3.21)
In addition, the relationship between the switching variable vector
[S1 S2 S3]T and the phase voltage vector [VA VB VC]T is given by Equation
(3.22).
VAVBVC
= Vdc
3
2 -1 -1-1 2 -1-1 -1 2
S1S2S3
(3.22)
For the three-phase voltage source inverter, eight combinations of
ON and OFF patterns are possible for the three upper power switches. The
ON and OFF states of the lower power switches are opposite to that of the
upper one. From Equations (3.21) and (3.22), the eight switching vectors, the
output phase voltages, and the output line-to-line voltages in terms of the DC-
link voltage Vdc are given in Table 3.1.
VDC+
VCA
VB
VC
S1 S2 S3
S1* S2
*S3
*
IA
IB
IC
VDC-
Sp
Sn
M
AC MOTOR
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Table 3.1 Summary of the inverter switching states and the corresponding phase and the line voltages
Voltage Vectors
Vn( S1S2S3)
Phase Voltages (Line to neutral voltages)
Line to Line voltages
VA VB VC VAB VBC VCA
V0 (000) 0 0 0 0 0 0
V1 (100) Vdc Vdc Vdc Vdc 0 -Vdc
V2 (110) Vdc Vdc Vdc 0 Vdc -Vdc
V3 (010) Vdc Vdc Vdc -Vdc Vdc 0
V4 (011) Vdc Vdc Vdc -Vdc 0 Vdc
V5 (001) Vdc Vdc Vdc 0 -Vdc Vdc
V6 (101) Vdc Vdc Vdc Vdc -Vdc 0
V7 (111) 0 0 0 0 0 0
It has been proved in the literature that the SVPWM technique
generates less total harmonic distortion (THD) in the output voltages and /or
output currents when applied to three-phase AC motor. The SPWM method
compares the sinusoidal reference signal with a triangular carrier signal to
generate the switching pulses to control the inverter output voltage. Figure 3.7
depicts the loci of the maximum linear control voltages in the SPWM and the
SVPWM techniques. The maximum amplitude of the reference vector in the
SVPWM technique is equal to the radius of the inner circle of the hexagon
whose radius is 3/2 or 0.866 times the amplitude of the active vectors.
However, the maximum amplitude of the reference vector in the SPWM
technique is only 0.5 times of the amplitude of the active vectors. Hence, the
THD of the output current is lower in the SVPWM technique as compared to
the SPWM technique.
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Figure 3.7 Comparison of the locus of the maximum linear control voltages in the SPWM and the SVPWM techniques
For implementing the SVPWM algorithm in the DSTATCOM, the voltages in the abc reference frame are transformed into the stationary reference frame, using the relationship given in Equation (3.23)
fdq0=Kfabc (3.23)
where,
K=23
1-12
-12
03
2- 32
12
12
12
, fdq0= fd fq f0T, fabc= fa fb fc
T
13
23
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and f represents either voltage, current or flux.
Because of this transformation, six non-zero switching vectors and
two zero switching vectors are possible. The six non-zero active vectors (V1 -
V6) form the axes of a hexagonal; the angle between any two adjacent non-
zero vector is 60°, as depicted in Figure 3.8. Binary numbers on the corner of
the hexagon indicate the switching state of the inverter branch. Here, 1
implies the upper switch in the branch being ON and 0 refers to the lower
switch of the branch being ON. The most significant bit is for branch A, the
least significant bit is for branch C and the middle bit is for branch B. The
same transformation can be applied to the desired output voltage to get the
desired reference voltage vector Vref in the d-q plane.
Figure 3.8 Basic switching vectors and sectors
Vref
T1
T2
d- axis
q- axis
V0
V7
V1 (100)
V3 (010) V2 (110)
V4 (011)
V5 (001) V6 (101)
S1
S2
S3
S4
S5
S6
(2/3, 0)
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3.6 IMPLEMENTATION OF THE SVPWM
The SVPWM is implemented as follows:
1. Determining Vd, Vq, Vref and angle .
2. Determining the time durations T1, T2, and T0.
3. Determining the switching time for each switch.
3.6.1 Determining Vd , Vq , Vref and Angle
Figure 3.9 shows the relationship between the reference voltages in
the abc coordinates and the dq coordinates. The values of Vd and Vq are
calculated using Equations (3.24) and (3.25).
Vd=Van12
Vbn12
Vcn (3.24)
Vq= 32
Vbn3
2Vcn (3.25)
Equations (3.24) and (3.25) can be written in matrix form as
Equation (3.26).
VdVq
=1 - 1
2- 1
2
0 32
- 32
VanVbnVcn
(3.26)
From Figure 3.9, Vref and are calculated using Equations (3.27) and (3.28).
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Figure 3.9 Voltage space vector and its components
|Vref|= Vd2+Vq
2 (3.27)
= tan-1 Vq
Vd= t=2 ft (3.28)
3.6.2 Determining the Time Durations T1, T2, T0
The switching time duration for each sector can be calculated using
the two adjacent active vectors and the one zero vector corresponding to that
sector.
d-axis
q-axis
a
b
c
VrefVq
Vd
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Figure 3.10 Reference vector from the adjacent vectors in sector 1
The switching times T1, T2 and T0 for sector 1 is shown
Figure 3.10, where T1 is the time for which the active vector V1 is ON, T2 is
the time for which the active vector V2 is ON, and T0 is the time for which the
zero vector (V0 or V7) is ON and TS is the switching time period. These
switching times T1, T2 and T0 are calculated for Sector 1 using the
Equation (3.29).
VrefTS
0 = V1T1
0 dt+ V2T1+ T2
T1dt+ V0
TST1+ T2
(3.29)
Equation (3.29) is written in a simplified form as Equation (3.30).
TS Vref = (T1 V1+T2 V2) (3.30)
Hence, the switching times T1, T2 and T0 for Sector 1 are given by
Equations (3.31) to (3.33)
T2
TS V2
O
V2
Vref
V1
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T1=TS a sin ( 3 )
sin ( 3) (3.31)
T2=TS a sin ( )sin ( 3)
(3.32)
T0=TS (T1+T2) (3.33)
where, 0 60, Ts = 1fs and a = |Vref|
23Vdc
.
The switching times for any sector can be generalized and are
given by Equations (3.34) to (3.36)
T1= 3Ts|Vref|Vdc
sin3
(3.34)
T2= 3TS|Vref|Vdc
sin - n-13
(3.35)
T0=TS T1 T2 (3.36)
where, n can be any sector from 1 to 6.
3.6.3 Determining the Switching Time for Each Switch
In order to obtain the fixed switching frequency and the optimum
harmonic performance from the SVPWM, each branch of the VSC should
change its state only once in a switching period. This can be achieved by
applying a zero vector followed by adjacent active vectors for half the
switching period. The next half of the switching period is the mirror image of
the first half. The total switching period is divided into 7 parts. The zero
vector V0 is applied first for time T0/4 followed by the application of active
vector V1 for time T1/2 and V2 for time T2/2. Then V0 is applied for time T0/2
followed by application of V2 for time T2/2 and V1 for time T1/2. Finally, V0 is
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applied for time T0/4. Figure 3.11 shows the branch voltage for one switching
period for sector I. Similarly, the branch voltages in other sectors are
obtained.
Figure 3.11 SVPWM switching patterns in sector 1
3.7 SIMULATION RESULTS
The PI controlled PWM and SVPWM control algorithms are
simulated for different cases, in MATLAB Simulink environment, for a
±3 kVA DSTATCOM at 25 kV voltage rating. Table 3.2 shows the
simulation parameters of the DSTATCOM system.
S1
S2
S3
V8 V1V2V7V2V1V8
0
0
0
0
0
0
T0/4T2/2T1/2T0/4 T0/2 T2/2 T1/2
2Ts
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Table 3.2 Simulation parameters of the DSTATCOM system for SPWM and SVPWM switching techniques
DSTATCOM (kVA) ±3 kVA
Bus B1 voltage 25 kV
Load bus voltage 600 V
Fundamental frequency 50 Hz
Carrier frequency 1.35 kHz
Transformer on load side 25000 V/ 600 V
Transformer on DSTATCOM side 2.5 kV/ 25 kV
DC capacitance 10000 F
Average DC voltage 2400 V
Load 1 (P–jQ) 2086 kW j2718 kVAR
Load 2 (P+jQ) 2086 kW+ j4077 kVAR
3.7.1 Case 1: When the DSTATCOM is not present in the system
The performance of the power system is studied for the capacitive
and the inductive loads without including the DSTATCOM in the system. The
distribution part of the power system is represented by a Thevenin’s
equivalent voltage source and short circuit impedance. Figure 3.12 shows this
source connected to the bus B1. Feeder lines are connected between the buses
B1 and B2 and the buses B2 and B3. At the bus B3, two different loads are
connected through a 25 kV/ 600 V transformers. By varying the load, the
voltage at bus B3 is studied when the DSTATCOM is not connected to the
system at that bus. The variation of the load creates a voltage sag or swell in
the bus B3 depending upon the type of load. This voltage sag or swell will
affect the operation of some other sensitive loads in the system. Figure 3.12
shows the MATLAB simulation diagram of DSTATCOM. Figure 3.13 shows
the Simulink diagram for the SPWM and the SVPWM implementations.
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Figure 3.12 DSTATCOM simulation using MATLAB/ Simulink blockset
The source is connected at the bus B1 and the load is connected at
the bus B3. The voltage variation in bus B3 is observed by varying the loads.
In this simulation, voltage variations at buses B1 and B3 are observed, as
shown in Figure 3.14a. It is seen that initially the voltages at buses B1 and B3
are at 1 p.u. until time t = 0.02 s.
Figure 3.13 Simulink diagram for the PWM and the SVPWM techniques
When the RC load is connected to the system at time t = 0.02 s, the
voltage at buses B1 and B3 increase by 8% , resulting in the bus voltages
becoming 1.08 p.u. This is because of the capacitive nature of the load, which
requires active power of 2086 kW and supplies reactive power of 2718 kVAR
to the grid. At time t = 0.2 s, the RC load is removed and the RL load is
included, which requires the same amount of active power but 4077 kVAR of
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reactive power. The source is capable of supplying the full active power and
only a part of the reactive power. Due to the insufficient reactive power
supplied by the source to the load, the voltage at bus B3 decreases by 4 %
resulting in the bus voltage becoming 0.96 p.u., from time t = 0.2 s to time
t = 0.3 s, as shown in Figure 3.14a. At t = 0.3 s, both the loads are connected
to the system.
(a)
(b)
Figure 3.14 Without DSTATCOM (a) Variations of the bus voltage and (b) Variations of the active and reactive powers
The total active power required is the sum of the two active powers
and the reactive power required is the difference of the inductive reactive
power (QL) and capacitive reactive power (QC). Here, QL QC =
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.50.9
0.95
1
1.05
1.1
1.15Bus Voltage Variation
Time (s)
VB3
VB1
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5-4
-2
0
2
4
6
8
Time (S)
Variation of PQ
Q
P
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1359 kVAR (inductive) is the reactive power required by the load. This
results in the reduction of voltage at bus B3 by 2% resulting in the bus voltage
of 0.98 p.u. Hence, the bus voltage at bus B3 is not regulated at 1 p.u. for
load variations.
3.7.2 Case 2: Performance of the DSTATCOM for the PWM and the
SVPWM control algorithms
Figures 3.15 shows the variation of bus voltage and the variation of
real and reactive power variation when DSTATCOM is present in the system.
The performance of the DSTATCOM is studied for the voltage regulation
application using the control signals generated by the SPWM and the
SVPWM methods. The results of these methods are given in Figures 3.16 and
3.17 respectively. It is found that in the SPWM method, the THD of the VSC
current is 2.67%, as shown in Figure 3.16a. In addition, the shunt current
injected from DSTATCOM is controlled. To inject the required reactive
power, the q component of the current is controlled to follow the reference ,
current. Thus, Iq follows Iq_ref, as shown in Figure 3.16b and the
corresponding reactive power variation is shown in Figure 3.16c. From t = 0 s
to 0.2 s, the RC load is connected to the system, the reactive power Q = 3
MVAR is absorbed by the DSTATCOM. From t = 0.2 s to 0.3 s, the RL load
is connected to the system, that requires reactive power. During this period,
the reactive power of 2.3 MVAR is supplied by the DSTATCOM. After
t = 0.3 s, the reactive power of 1.05 MVAR is supplied by DSTATCOM to
regulate the bus voltage. Positive sign of Q in Figure 3.16c indicates
absorption of reactive power by DSTATCOM and negative sign of Q
indicates the supply of reactive power by the DSTATCOM. It should be noted
that in the voltage regulation process there is no variation in the real power P.
The capacitor voltage needs to be maintained constant at 2400 V to keep the
real power supplied from DSTATCOM to zero in the ideal case, but in
62
practice, it supplies the switching losses. However, there are some variations
in the capacitor voltage at t = 0.2 s and t = 0.3 s, as shown in Figure 3.16d.
In the SVPWM algorithm, the capacitor voltage is maintained
constant at 2400 V as shown in Figure 3.17d. The output current has THD of
1.92%, which is lower than the SPWM method, as shown in Figure 3.17a.
The variation of Iq and Iq_ref for SVPWM algorithm is shown in Figure 3.17b
and the corresponding variation of real and reactive powers are shown in
Figure 3.17c.
(a)
(b)
Figure 3.15 With DSTATCOM (a) Variation of the bus voltage (b) Variation of the real and the reactive powers
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5-4
-2
0
2
4
6
8
Time (S)
Variation of PQ
Q
P
63
(a) Output current and its THD
(b) Variation of Iq and Iq_ref
Figure 3.16 (Continued)
0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5-1.5
-1
-0.5
0
0.5
1
Time(s)
Iq Iq ref
IqIq ref
64
(c) Variation of P and Q
(d) Variation of the DC bus voltage
Figure 3.16 Variation of the DSTATCOM parameters for the SPWM algorithm
0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5-3
-2
-1
0
1
2
3
4
Time(s)
P Q (Mw Mva)
PQ
0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.52000
2100
2200
2300
2400
2500
2600
Time(s)
Vdc
(V)
Dc Bus Voltage(V)
65
(a) THD of the output current
(b) Variation of Iq and Iq_ref
Figure 3.17 (Continued)
0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5-1.5
-1
-0.5
0
0.5
1Iq Iqref
Time (s)
IqIqref
66
(c) Variation of P and Q
(d) Variation of the DC bus voltage
Figure 3.17 Variation of the DSTATCOM parameters for the SVPWM
Algorithm
0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5-3
-2
-1
0
1
2
3
4
Time (s)
P Q (Mw, Mva)
PQ
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.50
500
1000
1500
2000
2500
3000
3500
4000
Time (s)
DC Bus voltage
67
3.8 SUMMARY
The DSTATCOM is simulated in the MATLAB-Simulink
environment. The performance of DSTATCOM was studied for the SPWM
and the SVPWM switching algorithms for the load variation. It was observed
that both the algorithms work very well for reactive power compensation and
bus voltage regulation of the DSTATCOM. The output current has lower
THD in the SVPWM algorithm (1.92%) when compared to the SPWM
algorithm (2.67%). The DC bus voltage regulation is much better in the
SVPWM algorithm compared to the SPWM algorithm. The DC bus voltage is
controlled in SPWM and SVPWM methods. In SPWM method the DC bus
voltage is affected by the load variation at time t=0.2s and at time t=0.3s,
whereas in SVPWM method the variation of the load is not affecting the DC
bus voltage. Hence the DC bus voltage remains constant at the load varying
points in SVPWM method. The SVPWM is more effective in DC bus voltage
regulation as it applies the different switching vectors for each sector. The
SVPWM algorithm has lower switching loss as compared to the SPWM
algorithm, as only one switch changes its state at a time.