Chapter 3 (part 2) Basic Logic Gates 1 1. 3-7 The Inverter Used to complement (invert) a digital...

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Chapter 3 (part 2) Basic Logic Gates 1 1

Transcript of Chapter 3 (part 2) Basic Logic Gates 1 1. 3-7 The Inverter Used to complement (invert) a digital...

Page 1: Chapter 3 (part 2) Basic Logic Gates 1 1. 3-7 The Inverter Used to complement (invert) a digital signal –When A = 1, X = 0 –When A = 0, X = 1 Timing analysis.

Chapter 3 (part 2)

Basic Logic Gates

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Page 2: Chapter 3 (part 2) Basic Logic Gates 1 1. 3-7 The Inverter Used to complement (invert) a digital signal –When A = 1, X = 0 –When A = 0, X = 1 Timing analysis.

3-7 The Inverter

• Used to complement (invert) a digital signal– When A = 1, X = 0

– When A = 0, X = 1

• Timing analysis

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Page 3: Chapter 3 (part 2) Basic Logic Gates 1 1. 3-7 The Inverter Used to complement (invert) a digital signal –When A = 1, X = 0 –When A = 0, X = 1 Timing analysis.

Truth table and Boolean equations for the Inverter

• Truth Table • Boolean Equation:

X = A• Inversion bar

– Used to signify the complement

• Inverter is also called as NOT gate

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Page 4: Chapter 3 (part 2) Basic Logic Gates 1 1. 3-7 The Inverter Used to complement (invert) a digital signal –When A = 1, X = 0 –When A = 0, X = 1 Timing analysis.

3-8 The NAND Gate

• Same as the AND gate except that its output is inverted– If A = 1 and B = 1, X = 0

– If A = 0 or B = 0, A = 1

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Page 5: Chapter 3 (part 2) Basic Logic Gates 1 1. 3-7 The Inverter Used to complement (invert) a digital signal –When A = 1, X = 0 –When A = 0, X = 1 Timing analysis.

I/O of a 7400 quad NAND IC

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Page 6: Chapter 3 (part 2) Basic Logic Gates 1 1. 3-7 The Inverter Used to complement (invert) a digital signal –When A = 1, X = 0 –When A = 0, X = 1 Timing analysis.

Truth table and Boolean equations for the NAND Gate

• Boolean Equation: X = AB

• Multiple inputs - the output is always HIGH unless all inputs go HIGH

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Page 7: Chapter 3 (part 2) Basic Logic Gates 1 1. 3-7 The Inverter Used to complement (invert) a digital signal –When A = 1, X = 0 –When A = 0, X = 1 Timing analysis.

Symbols for three- and eight-input NAND gates

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Page 8: Chapter 3 (part 2) Basic Logic Gates 1 1. 3-7 The Inverter Used to complement (invert) a digital signal –When A = 1, X = 0 –When A = 0, X = 1 Timing analysis.

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Page 9: Chapter 3 (part 2) Basic Logic Gates 1 1. 3-7 The Inverter Used to complement (invert) a digital signal –When A = 1, X = 0 –When A = 0, X = 1 Timing analysis.

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Page 10: Chapter 3 (part 2) Basic Logic Gates 1 1. 3-7 The Inverter Used to complement (invert) a digital signal –When A = 1, X = 0 –When A = 0, X = 1 Timing analysis.

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Page 11: Chapter 3 (part 2) Basic Logic Gates 1 1. 3-7 The Inverter Used to complement (invert) a digital signal –When A = 1, X = 0 –When A = 0, X = 1 Timing analysis.

3-9 The NOR Gate

• Same as the OR gate except that its output is inverted– If A = 1 or B = 1, X = 0

– If A = 0 and B = 0, X = 1

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Page 12: Chapter 3 (part 2) Basic Logic Gates 1 1. 3-7 The Inverter Used to complement (invert) a digital signal –When A = 1, X = 0 –When A = 0, X = 1 Timing analysis.

I/O of a 7402 quad NOR IC

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Page 13: Chapter 3 (part 2) Basic Logic Gates 1 1. 3-7 The Inverter Used to complement (invert) a digital signal –When A = 1, X = 0 –When A = 0, X = 1 Timing analysis.

Truth Table and Boolean equation for The NOR Gate

• Truth Table• Boolean Equation: X = A + B

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Page 14: Chapter 3 (part 2) Basic Logic Gates 1 1. 3-7 The Inverter Used to complement (invert) a digital signal –When A = 1, X = 0 –When A = 0, X = 1 Timing analysis.

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Page 15: Chapter 3 (part 2) Basic Logic Gates 1 1. 3-7 The Inverter Used to complement (invert) a digital signal –When A = 1, X = 0 –When A = 0, X = 1 Timing analysis.

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Page 16: Chapter 3 (part 2) Basic Logic Gates 1 1. 3-7 The Inverter Used to complement (invert) a digital signal –When A = 1, X = 0 –When A = 0, X = 1 Timing analysis.

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Page 17: Chapter 3 (part 2) Basic Logic Gates 1 1. 3-7 The Inverter Used to complement (invert) a digital signal –When A = 1, X = 0 –When A = 0, X = 1 Timing analysis.

3-10 Logic Gate Waveform Generation

A popular generalPurpose Repetitive waveform generator

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Page 18: Chapter 3 (part 2) Basic Logic Gates 1 1. 3-7 The Inverter Used to complement (invert) a digital signal –When A = 1, X = 0 –When A = 0, X = 1 Timing analysis.

Figure 3.44 Generating a 3-ms HIGH pulse using an AND gate and a Johnson shift counter.

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Page 19: Chapter 3 (part 2) Basic Logic Gates 1 1. 3-7 The Inverter Used to complement (invert) a digital signal –When A = 1, X = 0 –When A = 0, X = 1 Timing analysis.

Example 3-13 Which Johnson counter outputs will you connect to an AND gate to get a 1ms HIGH-level output from 4 to 5ms?

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Page 20: Chapter 3 (part 2) Basic Logic Gates 1 1. 3-7 The Inverter Used to complement (invert) a digital signal –When A = 1, X = 0 –When A = 0, X = 1 Timing analysis.

Example 3-14 Which Johnson counter outputs must be connect to a three-input AND gate to enable just the Cp#4 pulse only to be output?

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Page 21: Chapter 3 (part 2) Basic Logic Gates 1 1. 3-7 The Inverter Used to complement (invert) a digital signal –When A = 1, X = 0 –When A = 0, X = 1 Timing analysis.

Example 3-15 Sketch the output waveform resulting from inputting the Johnson counter outputs shown:

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Page 22: Chapter 3 (part 2) Basic Logic Gates 1 1. 3-7 The Inverter Used to complement (invert) a digital signal –When A = 1, X = 0 –When A = 0, X = 1 Timing analysis.

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Page 24: Chapter 3 (part 2) Basic Logic Gates 1 1. 3-7 The Inverter Used to complement (invert) a digital signal –When A = 1, X = 0 –When A = 0, X = 1 Timing analysis.

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Page 26: Chapter 3 (part 2) Basic Logic Gates 1 1. 3-7 The Inverter Used to complement (invert) a digital signal –When A = 1, X = 0 –When A = 0, X = 1 Timing analysis.

Figure 3.60 7404 TTL and 4049 CMOS inverter pin configurations.

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Page 27: Chapter 3 (part 2) Basic Logic Gates 1 1. 3-7 The Inverter Used to complement (invert) a digital signal –When A = 1, X = 0 –When A = 0, X = 1 Timing analysis.

Figure 3.61 (a) 7402 TTL NOR and 4001 CMOS NOR pin configurations; (b) 7400 TTL NAND and 4011 CMOS NAND pin configurations.

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3-12 IEEE/IEC Standard Logic Symbols

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Page 31: Chapter 3 (part 2) Basic Logic Gates 1 1. 3-7 The Inverter Used to complement (invert) a digital signal –When A = 1, X = 0 –When A = 0, X = 1 Timing analysis.

Summary

• The AND gate requires that all inputs are HIGH in order to get a HIGH output.

• The OR gate outputs a HIGH if any of its inputs are HIGH.

• An effective way to measure the precise timing relationships of digital waveforms is with an oscilloscope or a logic analyzer.

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Page 32: Chapter 3 (part 2) Basic Logic Gates 1 1. 3-7 The Inverter Used to complement (invert) a digital signal –When A = 1, X = 0 –When A = 0, X = 1 Timing analysis.

Summary

• Beside providing the basic logic functions, AND and OR gates can also be used to enable or disable a signal to pass from one point to another.

• There are several integrated circuits available in both TTL and CMOS that provide the basic logic functions.

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Page 33: Chapter 3 (part 2) Basic Logic Gates 1 1. 3-7 The Inverter Used to complement (invert) a digital signal –When A = 1, X = 0 –When A = 0, X = 1 Timing analysis.

Summary

• Two important troubleshooting tools are the logic pulser and the logic probe. The pulser is used to inject pulses into a circuit under test. The probe reads the level at a point in a circuit to determine is it is HIGH, LOW, or floating.

• An inverter provides an output that is the complement of its input.

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Page 34: Chapter 3 (part 2) Basic Logic Gates 1 1. 3-7 The Inverter Used to complement (invert) a digital signal –When A = 1, X = 0 –When A = 0, X = 1 Timing analysis.

Summary

• A NAND gate outputs a LOW when all of its inputs are HIGH.

• A NOR gate outputs a HIGH when all of its inputs are LOW.

• Specialized waveforms can be created by using a repetitive waveform generator and the basic gates.

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