38

CHAPTER 3

DESIGN AND IMPLEMENTATION OF ZVS HIGH GAIN

SELF BOOST DC-DC CONVERTER

3.1 INTRODUCTION

The voltage boosting technique is a popular method that is widely

applied in electronic circuit design. The voltage boost technique opens a good

way to improve circuit characteristics. This chapter presents the analysis,

design and implementation of zero voltage switched high gain self boost DC-

DC converter for wide range of loads with lower switching losses and

increased efficiency. To improve the power packing density, a simple control

method using dSpic microcontroller is used. The soft switched boost

converter has advantages including a high output voltage with less ripples.

The performance of this converter is experimented for different loads and also

for different duty cycles. The results reveal that the ZVS is achieved in all

aspects and the switching losses are reduced. Ultimately, the efficiency of the

converter is improved to 90% at k = 0.6.

3.2 PRINCIPLE OF OPERATION OF THE ZVS HIGH GAIN

SELF BOOST DC-DC CONVERTER

It consists of a switch S with resonating components Cr and Lr,

inductors L1, L2, diodes D, D1, capacitors C, C1, C0 and the load resistance R.

The circuit diagram of ZVS high gain self boost DC-DC converter is shown

in Figure 3.1. The switch is driven by a PWM signal with conduction duty

39

ratio k and repeating switching frequency fs. The input voltage and current are

Vin and Iin and output voltage and current are V0 and I0 respectively. The

voltage transfer gain is M = V0/Vin .

To analyze the steady-state behaviour of the converter operating in

continuous conduction mode, the following assumptions are made:

1. Semiconductor switches are ideal, i.e., no forward voltage

drop in the on state, no leakage current in the off state and no

time delay at both turn-on and turn-off.

2. Reactive elements in the circuit are ideal.

3. Inductors L1 and L2 are larger than resonating inductor Lr.

4. The output capacitor C0, inductor L2 and the load R are

constant sink of output current I0.

The switch repeating period is Ts = 1/fs, so that the switch-on period

is kTs and switch-off period is (1 k)Ts. In this circuit, the load resistance,

R = V0/I0; the combined inductor L = L1L2/(L1 + L2); the normalized load

ZN = R/fsL. The converter consists of a positive voltage pump, a low-pass

filter L2-C0, and there is only one capacitor C1 and one diode D1 more, as a

booster which is added into the circuit. Capacitor C1 functions to lift the

capacitor voltage VC by Vin.

When switch S is on, the instantaneous source current is i1 = iL1 +

iL2 + iC1. Inductor L1 absorbs energy from the source. In the mean time

inductor L2 absorbs energy from source and capacitor C. Both the currents iL1

and iL2 increase, and C1 is charged to vC1 = V1. When switch S is off, current

iL1 flows through capacitor C1 and diode D to charge capacitor C. Inductor L1

transfers its stored energy to capacitor C. In the mean time, current iL2 flows

40

through the (C0 R) circuit, capacitor C1 and diode D, to keep itself

continuous. Both the currents iL1 and iL2 decrease.

To analyze the steady-state behaviour of the converter, each

switching cycle is divided into four modes of operation. IM, iLr and vCr are

defined as magnetizing current, resonant inductor current and resonant

capacitor voltage respectively.

Figure 3.1 Circuit diagram of ZVS high gain self boost DC-DC converter

3.2.1 Modes of Operation

3.2.1.1 Mode 1: Interval T1 = (t0 - t1)

When switch S is turned off at t = t0, the capacitor voltage vCr(t)

increases linearly with the slope IM /Cr. The equivalent circuit diagram of this

mode is shown in Figure 3.2a.This is the voltage rising interval and as the

resonant capacitor voltage vCr(t) is less than the input voltage Vin, the diodes

D1 and D will be in on state. The resonant capacitor voltage vCr(t) and

inductor current iLr(t) are given by

r

MCr C

tItv )( (3.1)

41

MLr Iti )( (3.2)

At t= t1 , vCr(t) = Vin , the duration of this mode is given by

M

rin

ICVT1 (3.3)

3.2.1.2 Mode 2: Interval T2 = (t1 - t2 )

During this mode, as the switch S remains off, the elements Lr and

Cr form a series resonant circuit and resonate with each other. This is the

resonance interval as shown in Figure 3.3. Therefore, the current iLr starts

decreasing. The diode D is in the conducting state and the diode D1 is in the

off state. The equivalent circuit diagram of this mode is shown in

Figure 3.2b. Current iL1 flows through capacitor C1 and diode D to charge

capacitor C. Inductor L1 transfers its stored energy to capacitor C. In the mean

time, current iL2 flows through the (C0 R) circuit, capacitor C1 and diode D,

to keep itself continuous. Both the currents iL1 and iL2 decrease. The variations

of currents are very small, so that iL1 = IL1 and iL2 = IL2 and it is given as

1

121 L

tVII inLL

(3.4)

The capacitor current is given as

1tCVI C

C (3.5)

When the capacitor voltage vcr(t) > Vin, Lr and Cr starts resonating. This

interval is called as resonance interval. The capacitor voltage waveform is a

42

sinusoidal function. It reaches its peak value VCr(peak) and then it decreases to

zero at time t = t2.

The state equations are given as

dtdvCti Cr

rLr )( (3.5a)

dtdiLtvV Lr

rCrin )( (3.5b)

The solutions of the state equations with the initial conditions

vCr(t1) = Vin and iLr(t1) = IM will give the resonant capacitor voltage and

resonant inductor current for t > t1.

tIZVtv rMinCr sin)( 1 (3.6)

tIti rMLr cos)( (3.7)

where r

r

CLZ1 and

rrr CL

1

As the current through Lr starts decreasing, it causes an increase in

the voltage across Cr. At t = t1', the current iLr reaches zero and vCr reaches the

peak value as shown in the Figure 2.3

The peak value of the resonant capacitor voltage is given as

MinpeakCrCr IZVVtv 1)(1 )'( (3.8)

43

The resonant inductor current at t = t1' is given as

0)'( 1tiLr (3.8a)

During the period t1 1 Cr back

to Lr decreasing vCr from its peak value to Vin and current iLr reaches the

negative peak IM.

For t > t1 , the solutions of the equations 3.5a and 3.5b with the

initial conditions vCr(t1 in and iLr(t1 -IM are given by

tIZVtv rMinCr sin)"( 11 (3.8b)

tIti rMLr cos)"( 1 (3.8c)

At t = t2, the voltage vCr(t) reaches zero, to achieve zero-voltage condition for

switch S

0)( 2tvCr (3.9)

cos)( 2 MLr Iti (3.10)

where 0

1sinZI

VM

in (3.11)

Time duration for this mode is given by

r

ttT )()( 122 (3.12)

44

3.2.1.3 Mode 3: Interval T3 = (t2 - t3)

At time t=t2, the switch S is switched on at zero voltage condition.

The resonant inductor current starts increasing linearly with the slope

Vin/(Lr+L1). This is the linear recovery interval.

The equivalent circuit diagram of this mode is shown in

Figure 3.2c. Since, load current I0 is a constant current, the current iLr(t)

increases linearly from IM to IM at t = t3 .Since the diode Dr does not

allow the resonant voltage vCr(t) to become negative, vCr(t) remains zero. The

diode D1 becomes forward biased and starts conducting. The duration of this

mode is given by,

in

rM

VLLIT )()cos1( 1

3 (3.14)

3.2.1.4 Mode 4: Interval T4= (t3 - t4)

During this period the current through the load is due to the source

voltage Vin. The diode D is blocked till t = t4, this is the normal switch on

interval as shown in Figure 3.3. The output current I0 is equal to the output

inductor current iL2. The source current iin = iL1+ iL2 + iC1.The equivalent

circuit diagram of this mode is shown in Figure 3.2d. During this mode iLr(t)

remains constant at IM. This mode continues until the switch S is opened at

t = t4 and the cycle repeats. The duration of this mode is given by

)( 3214 TTTTT s (3.15)

45

(a) Mode 1

(b) Mode 2

(c) Mode 3

Figure 3.2 (Continued)

46

(d) Mode 4

Figure 3.2 Equivalent circuit of ZVS high gain self boost DC-DC converter topological modes of a switching cycle (a) Mode 1 t0 t t1 (b) Mode 2 t1 t t2

(c) Mode 3 t2 t t3 (d) Mode 4 t3 t t4

Figure 3.3 Theoretical waveforms of ZVS of high gain self boost DC-DC converter

47

3.3 ANALYSIS OF THE ZVS OF HIGH GAIN SELF BOOST

DC-DC CONVERTER

Assuming that the output power is equal to the input power

ininoooin IVIVorPP )( (3.16)

In an ideal condition, from the conservation of energy theory, over

a switching period, the input energy Ein is equal to the output energy E0 and

they can be described by the following equation:

2

0 0

14

)()(T

T

inininin dttidttiVE (3.17)

where T1 and T2 are the time intervals of modes 1 and 4 respectively.

In the integral Equation 3.17, upper limits T1/2 and T4 are used

since energy is transferred from source to the load for half of T1 interval and

complete T4 interval respectively.

Since the input current iin(t) is equal to IM during the first and fourth interval,

4

1

2TTIVE Minin (3.17a)

The output energy over one cycle is obtained by evaluating the

following equation

soo

T

o TIVdtVtiEs

00

0 )( (3.18)

48

Then, the DC voltage conversion ratio is defined as

32

1

21 TTTT

II

TVVM s

o

M

sin

o (3.19)

By substituting the values of Td1 Td3, Equation 3.19 is modified

and expressed in terms of circuit parameters as

sin

rM

r

ss

M

rin

o

M fV

LLIf

ffICV

IIM ))(cos1(

2)(

21 11

(3.20)

Resonant frequencyrr

r CLf

21

(3.21)

Normalized switching frequency r

sns f

ff (3.22)

Characteristic impedance r

r

CLZ1 (3.23)

Normalized load resistance o

N ZRR (3.24)

Equation 3.20 gives two solutions of M, out of which, the

maximum value Mmax is considered in the design. It is observed that, M is a

function of R and fs. The value of M can be regulated by varying fs.

Current iL1 increases in switch-on period kTs, and decreases in

switch-off period (1 k)Ts. The corresponding voltages applied across L1 are

Vin and (VC Vin) respectively.

49

)()1( inCsins VVTkVTk (3.25)

Hence, the capacitor voltage is given as

)1( kVV in

C (3.26)

Current iL2 increases in switch-on period kTs, and decreases in

switch-off period (1 k)Ts. The corresponding voltages applied across L2 are

(Vin + VC VO) and (VO Vin).

)()1()( 00 insCins VVTkVVVTk (3.27)

Hence, the output voltage and current are given as

)1( kVV in

o (3.28)

ino IkI )1( (3.29)

Therefore, the voltage transfer gain in continuous conduction mode is given

as

)1(1

kVVM

in

os (3.30)

Therefore, the peak to peak variation in inductor currents are given as

11 L

VTki insL (3.31)

50

22 L

VTki insL (3.32)

When switch is off, the change in freewheeling diode current is given as

LVTkki os

D)1(

(3.33)

The peak to peak variation of capacitor voltage VC is given as

CITkkV ins

C)1(

(3.34)

The charge on capacitor C1 increases during switch-on, and

decreases during switch-off period (1 k)Ts by the current (IL1 + IL2).

Therefore, its peak to peak variation is

CITV os

C1 (3.35)

3.4 DESIGN AND SIMULATION OF THE ZVS OF HIGH GAIN

SELF BOOST DC-DC CONVERTER

The high gain self boost ZVS DC-DC converter shown in

Figure 3.1 is designed with the following parameters:

Vin = 10 V, Lr Cr L1 = L2 = 1 mH, C C1

C0 I0 = 0.4 A 0.7 A , V0 = 16V 30V, fs = 40 kHz, fr =102 kHz

and R = k= 0.6.

The converter is simulated using the MATLAB/Simulink software

with the designed parameters. The simulated waveforms of gate pulse,

51

resonant capacitor voltage and resonant inductor current are shown in

Figure 3.4. It is observed from the results that the switch S is turned on, when

the voltage across the resonant capacitor becomes zero, thereby reducing the

switching losses. The simulated waveforms agree closely with the theoretical

resonant waveforms shown in Figure 3.3. The output voltage and load current

of the converter under open-loop operation for duty cycle k = 0.6 is shown in

Figure 3.5a.

(sec)Time

Figure 3.4 Simulated waveforms of (i) Resonating capacitor voltage

- 50 volts/div Vs time(sec) (ii) Resonating inductor current

5 amps/div Vs time(sec) (iii) Gate pulse signal 0.5

volts/div Vs time(sec)

Vcr

Vpulse

ILr

(i)

(ii)

(iii)

52

Figure 3.5a (i) Output voltage (V0) - 10 volts/div Vs time (sec) (ii) Output

current (I0) 0.2 amps/div Vs time (sec)

The characteristics of voltage conversion ratio M verus normalized

switching frequency fns for various normalized load RN is shown in

Figure 3.5b. At nominal operating condition, RN = 6.61, the voltage

conversion ratio M is 2.6 for normalized switching frequency fns=0.392. When

RN is suddenly changed from 6.71 to 4.9, M is decreased from 2.6 to 2.5. In

order to maintain M at 2.6, the normalized switching frequency has to be

varied from 0.392 to 0.362. Similarly, when the load is varied from 6.71 to

10.32, M is increased from 2.6 to 2.7. In order to maintain M at 2.6, the

normalized switching frequency has to be varied from 0.392 to 0.435. It is

found that the variation of M with fns is approximately linear and M is

sensitive to the load variations.

VO

IO

(sec)Time

(i)

(ii)

53

Figure 3.5b Characteristics of normalized switching frequency (fns) Vs

Voltage conversion ratio (M)

3.4 EXPERIMENTAL VERIFICATION OF ZVS HIGH GAIN

SELF BOOST DC-DC CONVERTER

To verify the design, a ZVS high gain self boost DC-DC converter

is implemented with the designed parameters. The inductors used are made of

ferrite air core and the capacitors used are made of plain polyester and

electrolyte type. The diode FR107 used in the circuit is a fast recovery diode

with high reliability. The power MOSFET IRF540N is used as a active switch

which is dynamic and can carry high current at high frequency with simple

drive requirement. The triggering pulse at 40 kHz with variable duty cycle is

0

0.5

1

1.5

2

2.5

3

0.333 0.352 0.372 0.392 0.411 0.431 0.45

Volta

ge C

onve

rsio

n R

atio

(M)

Normalised Switching Frequency (fns)

4.9

6.71

10.32

RN

54

generated using dSpic30F4011 controller and it is fed to the driver circuit

which consists of operational amplifiers (OpAmp4584), opto-coupler

(6N137), diodes (FR107), driver IC IR2110 with the capacitors and

resistors. The pulse isolation circuit and driver circuit is shown in Figure 3.6a

and 3.6b respectively. The experimental setup is shown in Figure 3.7. The

performance of the circuit is studied for different load conditions and duty

cycles.

55

56

57

Figure 3.7 Photograph of experimental setup of self boost ZVS DC-DC

converter

The open loop experimental waveforms are shown in Figures 3.12

to 3.15. It is observed that the switch S is turned on when the resonant

capacitor voltage becomes zero to ensure ZVS condition. The practical

waveforms obtained resemble the simulated waveforms as shown in

Figures 3.4 and 3.5a. The discrepancy observed between the simulation and

experimental waveforms may be due to parasitics.

For the switching frequency fs = 40 kHz, duty cycle k = 0.6 and

Vin = 10 V, the variation of output voltage V0 for different load conditions are

given in Table 3.1. The same is also graphically shown in Figure 3.8.

58

Table 3.1 Variation of output voltage for different loads

RO Iin (A) VO (V) IO (A)

22 2.85 24 1.04

38 2.05 25 0.73

52 1.50 26 0.52

80 1.11 27 0.36

92 0.88 28 0.27

Figure 3.8 Output voltage (Vo) Vs Load resistance (R)

For the switching frequency fs = 40 kHz, Vin = 10 V and R

the variation of output voltage V0, gain (Ms) and %efficiency for different

duty cycles at constant load for soft switching and hard switching are given in

Tables 3.2a and 3.2b respectively. The same are graphically shown in the

Figures 3.9, 3.10 and 3.11 respectively. It is inferred that higher output

voltage and efficiency are obtained with soft switching compared to hard

switching.

22

23

24

25

26

27

28

29

22 38 52 80 92

Out

put V

olta

ge(V

0)

Load resistance(R)

59

Table 3.2a Variation of output voltage, gain and efficiency for different

duty cycles Soft switching

Duty Cycle (k)

Iin (A) VO (V) IO (A) ME

0.5 1.21 22.0 0.42 2.2 76.36

0.53 1.32 23.0 0.47 2.3 81.89

0.56 1.44 24.0 0.5 2.4 83.33

0.6 1.50 26.0 0.52 2.6 90.13

0.63 1.87 27.0 0.58 2.7 83.74

0.66 2.11 28.0 0.62 2.8 82.27

0.7 2.40 30.0 0.65 3.0 81.25

Table 3.2b Variation of output voltage, gain and efficiency for different

duty cycles Hard switching

Duty Cycle (k)

Iin (A) VO (V) IO (A) ME

0.5 1.26 20.5 0.39 2.05 63.4

0.53 1.38 21.4 0.45 2.14 69.7

0.56 1.51 22.7 0.47 2.27 70.6

0.6 1.60 24.5 0.5 2.45 71.6

0.63 1.90 25.8 0.53 2.58 71.9

0.66 2.15 26.6 0.58 2.66 71.7

0.7 2.45 27.7 0.61 2.77 68.9

60

Figure 3.9 Output voltage(Vo) Vs Duty cycle (k)

Figure 3.10 Output voltage(V0) Vs Gain(Ms)

0

5

10

15

20

25

30

35

0.5 0.53 0.56 0.6 0.63 0.66 0.7

Out

put V

olta

ge(V

0)

Duty Cycle(k)

Soft Switching

Hard Switching

0

0.5

1

1.5

2

2.5

3

3.5

20.5 21.4 22.7 24.5 25.8 26.6 27.7

Gai

n (M

s)

Output voltage (V0)

Soft Switching

Hard Switching

61

Figure 3.11 Output Power (Po

Figure 3.12 Gate pulse generated using microcontroller

X- -axis: 5 volts/div

0

10

20

30

40

50

60

70

80

90

100

0 5 10 15 20 25

% E

ffic

ienc

y

Output Power (P0)

Soft Switching

Hard Switching

62

Figure 3.13 Resonant capacitor voltage

X- -axis: 5 Volts/div

Figure 3.14 Resonant inductor current

X- -axis: 500mA/div

63

Figure 3.15 Output voltage (24V)

X- -axis: 5 Volts/div

3.5 CONCLUSION

In this chapter, a new ZVS high gain self boost DC-DC converter is

analyzed, designed, simulated and implemented. The simulated and practical

waveforms obtained agree with the theoretical waveforms for different loads

and duty cycles. ZVS technique effectively reduces the switching losses and

increases the efficiency of this DC-DC converter. The converter efficiency is

found to be 90% at k=0.6. The proposed converter with high power density

and simple structure can be used in electronic circuits design.