Chapter 3 Basic Processing Unit.

Chapter 3

Basic Processing Unit

Chapter Objectives

• How a processor executes instructions• Internal functional units and how they are

connected• Hardware for generating internal control

signals• The micro programming approach• Micro program organization

Fundamental Concepts• Processor fetches one instruction at a time, and performs

the operation specified.• Instructions are fetched from successive memory locations

until a branch or a jump instruction is encountered.• Processor keeps track of the address of the memory

location containing the next instruction to be fetched using Program Counter (PC).

• After fetching an instruction, the contents of the PC are updated to point to the next instruction in the sequence.

• A branch instruction may load a different value into the PC• Instruction Register (IR) is another key register in the

processor.

Executing an Instruction• Fetch the contents of the memory location

pointed to by the PC. The contents of this location are loaded into the IR (fetch phase).

IR [[PC]]• Assuming that the memory is byte

addressable, increment the contents of the PC by 4 (fetch phase). PC [PC] + 4

• Carry out the actions specified by the instruction in the IR (execution phase).

• ALU and all the registers are interconnected via a single common bus.• The data and address lines of the

external memory bus connected to the internal processor bus via the memory data register, MDR, and the memory address register, MAR respectively.• Register MDR has two inputs and two

outputs.• Data may be loaded into MDR either

from the memory bus or from the internal processor bus.• The data stored in MDR may be placed

on either bus.• The input of MAR is connected to the

internal bus, and its output is connected to the external bus.• The control lines of the memory bus are

connected to the instruction decoder and control logic.

• The control unit is responsible for issuing the signals that control the operation of all the units inside the processor and for interacting with the memory bus.

• The MUX selects either the output of register Y or a constant value 4 to be provided as input A of the ALU.

• The constant 4 is used to increment the contents of the program counter.

7

Performing an arithmetic operation

Add the contents of registers R1 and R2 and place the result in R3. That is: R3 = R1 + R2

Step 1: Place the contents of register R1 into the Y register in the first clock cycle.

Step 2: Place the contents of register R2 onto the bus in the second clock cycle. (Both inputs to the ALU are now valid)

Step 3: Select register Y, and assert the ALU command F=A+B.

Step 4: In the third clock cycle, Z register has latched the output of the ALU.

Thus the contents of the Z register can be copied into register R3.

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Performing an arithmetic operation (contd..)

IR

TEMP

R1

R n 1-( )

Z

busMemory

Addresslines

MAR

linesData

MDR

PC

Carry-in

Y

ALU

Add

XOR

SubcontrolALU

lines

A B

MUXSelect

Constant 4

Instructiondecoder andcontrol logic

ControlSignals

Clock cycle 1:R1out, Yin

R2

R3

9


IR

TEMP

R1

R n 1-( )

Z

busMemory

Addresslines

MAR

linesData

MDR

PC

Carry-in

Y

ALU

Add=1

XOR

SubcontrolALU

lines

A B

MUXSelectY

Constant 4


ControlSignals

Clock cycle 2:R2out, SelectY, Add, Zin

R2

R3

10


IR

TEMP

R1

R n 1-( )

Z

busMemory

Addresslines

MAR

linesData

MDR

PC

Carry-in

Y

ALU

Add

XOR

SubcontrolALU

lines

A B

MUXSelectY

Constant 4


ControlSignals

Clock cycle 3:Zout, R3in

R2

R3

Clock cycle 4:R3 has the sum.

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Clock Cycle 1:

R1out, Yin (Y=R1)

Clock Cycle 2:

R2out, SelectY, Add, Zin (Z = R1+R2)

Clock Cycle 3:

Zout, R3in (R3=Z)

Instruction Execution

Register Transfers• Instruction execution involves a

sequence of steps in which data are transferred from one register to another.• For each register two control signals

are used to place the contents of that register on the bus or to load the data on the bus into register. (see figure)• The input and output of register Riin

and Riout is set to 1, the data on the bus are loaded into Ri.• Similarly, when Riout is set to 1, the

contents of register Ri are placed on the bus.• While Riout is equal to 0, the bus can

be used for transferring data from other registers.

Example

• Suppose we wish to transfer the contents of register R1 to register R4. This can be accomplished as follows.

• Enable the output of registers R1 by setting R1out to 1. This places the contents of R1 on the processor bus.

• Enable the input of register R4 by setting R4in to 1. This loads data from the processor bus into register R4.

• All operations and data transfers within the processor take place within time periods defined by the processor clock.

• The control signals that govern a particular transfer are asserted at the start of the clock cycle.

Input and Output Gating for 1-bit Register

Arithmetic OperationStep 1: The output of register R1 and the input of register Y are enabled, causing the contents of R1 to be transferred over the bus to Y.Step 2: The multiplexer’s select signal is set to Select Y, causing the multiplexer to gate the contents of register Y to input A of the ALU.At the same time, the contents of register R2 are gated onto the bus and, hence, to input B.The function performed by the ALU depends on the signals applied to its control lines.In this case, the ADD line is set to 1, causing the output of the ALU to be the sum of the two numbers at inputs A and B.This sum is loaded into register Z because its input control signal is activated.Step 3: The contents of register Z are transferred to the destination register R3. This last transfer cannot be carried out during step 2, because only one register output can be connected to the bus during any clock cycle.

Performing an Arithmetic or Logic Operation

What is the sequence of operations to add the contents of register R1 to those of R2 and store the result in R3?

1.R1out, Yin2.R2out, SelectY, Add, Zin3.Zout, R3in

All other signals are inactive.

Fetching a word from memory• Processor has to specify the address of the

memory location where this information is stored and request a Read operation.

• Processor transfers the required address to MAR.– Output of MAR is connected to the address lines of the memory bus.

• Processor uses the control lines of the memory bus to indicate that a Read operation is needed.

• Requested information are received from the memory and are stored in MDR.– Transferred from MDR to other registers.

Fetching a word from memory (contd..)• Timing of the internal processor operations

must be coordinated with the response time of memory Read operations.

• Processor completes one internal data transfer in one clock cycle.

• Memory response time for a Read operation is variable and usually longer than one clock cycle.– Processor waits until it receives an indication that the requested Read has been

completed. – Control signal (MFC) is used for this purpose.– MFC is set to 1 by the memory to indicate that the contents of the specified

location have been read and are available on the data lines of the memory bus.

Fetching a word from memory (contd..)MOVE (R1) R2

1. Load the contents of Register R1 into MAR.2. Start a Read operation on the memory bus. 3. Wait for MFC response from the memory.4. Load MDR from the memory bus.5. Load the contents of MDR into Register R2.

Steps can be performedseparately, some may be combined.

Steps 1 and 2 can be combined. - Load R1 to MAR and activate Read control signal simultaneously.Steps 3 and 4 can be combined. - Activate control signal MDRinE while waiting for response from the memory.Last step loads the contents of MDR into Register R2.Memory Read operation takes 3 steps.

Fetching a word from memory (contd..)MOVE (R1) R2: Memory operation takes 3 steps.

Step 1: - Place R1 onto the internal processor bus. - Load the contents of the bus into MAR. - Activate the Read control signal. - R1out, MARin, Read. Step 2: - Wait for MFC from the memory. - Activate the control signal to load data from external bus to MDR. - MDRinE, WMFCStep 3: - Place the contents of MDR onto the internal processor bus. - Load the contents of the bus into Register R2. - MDRoutI, R2in

Storing a word in Memory• Writing a word into a memory location follows a

similar procedure.• The desired address is loaded into MAR.• Then , the data to be written are loaded into MDR,

and a write command is issued.• Example• Executing the instruction• Move R2,(R1) requires the following steps

1.R1out, MARin2.R2out, MDRin, Write3.MDRoutE, WMFC

Execution of a Complete Instruction• Add (R3), R1: adds the contents of a memory location pointed to by R3 to register R1.• Executing this instruction requires the following actions:

1. Fetch the instruction2. Fetch the first operand (the contents of

the memory location pointed to by R3)3. Perform the addition4. Load the result into R1

Control Sequence

1. Write the control sequence to execute Add (R3),R1

Step Action

1. PC out, MAR in, Read, Select4, Add , Zin

2. Zout, PCin, Yin, MDRinE WMFC

3. MDRout, IR in,

4. R3 out, MAR in Read

5. R1 out, Yin, MDRinE WMFC

6. MDRout, Select Y, Add, Zin

7. Zout, R1in, End

2. Write the control sequence to execute Add (R3)+, R1

Step Action



3. MDRout, IR in,

4. R3 out, MAR in, Read, Select4, Add, Z in

5. Z out, R3 in

6. R1 out, Yin, MDRinE, WMFC

7. MDRout, Select Y, Add, Zin

8. Zout, R1in, End

LP Problem

Write the sequence of control steps required for the single bus structure for each of the following instructions.

1.Add the (immediate) number NUM to register R1.2. Add the contents of memory location NUM to register

R1.3. Add the contents of the memory location whose address

is at memory location Num to register R1.Assume that each instruction consists of two words. The first word specifies operation and the addressing mode, and the second word contains the number NUM.

1. Write the control sequence to execute Add #NUM, R1

Step Action



3. MDRout, IR in,

4. IR NUMout , Yin

6. SelectY , R1 out, Add, Zin

8. Zout, R1in, End

2. Write the control sequence to execute Add NUM, R1

Step Action



3. MDRout, IR in,

4. IRNUM out, MAR in, Read

5. MDRinE WMFC

5. MDRout , Yin

6. SelectY, R1 out, Add, Zin

8. Zout, R1in, End

3. Write the control sequence to execute Add (NUM), R1

Step Action


2. Zout, PCin, Yin, MDRinE , WMFC

3. MDRout, IR in,

4. IRNUM out MAR in, Read

5. MDRinE, WMFC

6. MDRout, MAR in, Read

7. MDRinE, WMFC

8. MDRout , Yin,

9. R1 out, SelectY, Add, Zin

10. Zout, R1in, End

Execution of Branch Instructions

• A branch instruction replaces the contents of PC with the branch target address, which is

usually obtained by adding an offset X given in the branch instruction.

• The offset X is usually the difference between the branch target address and the address immediately following the branch instruction.

Control sequence for an unconditional Branch instruction

Multiple-Bus Organization

• Three-bus organization to connect the registers and the ALU of a processor.

• All general-purpose registers are combined into a single block called register file.– Register file has three ports. – Two outputs ports connected to buses A and B,

allowing the contents of two different registers to be accessed simultaneously, and placed on buses A and B.

– Third input port allows the data on bus C to be loaded

into a third register during the same clock cycle. • Inputs to the ALU and outputs from the ALU:

– Buses A and B are used to transfer the source operands to the A and B inputs of the ALU.

– Result is transferred to the destination over bus C.

• ALU can also pass one of its two input operands unmodified if needed:– Control signals for such an operation are R=A or R=B.

• Three bus arrangement obviates the need for Registers Y and Z in the single bus organization.

• Incrementer unit:– Used to increment the PC by 4. – Source for the constant 4 at the ALU multiplexer can be

used to increment other addresses such as the memory addresses in multiple load/store instructions.

Control sequence for an instruction for the three bus organizationInstruction Add R4,R5,R6

Step Action1 PC out, R = B, MAR in, Read, IncPC2 WMFC3 MDRoutB, R = B, IR in4 R4outA, R5outB, SelectA, Add, R6in, EndInstruction Add R4,R5,R6

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Control unit• To execute instructions the processor must

generate the necessary control signals in proper sequence.

• Hardwired control:– Control unit is designed as a finite state machine.– Inflexible but fast.– Appropriate for simpler machines (e.g. RISC machines)

• Microprogrammed control:– Control path is designed hierarchically using principles identical to the CPU

design. – Flexible, but slow.– Appropriate for complex machines (e.g. CISC machines)

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Hardwired controlStep Action

1 PCout , MAR in ,Read,Select4,Add, Zin2 Zout , PCin , Y in , WMFC3 MDRout , IR in

4 R3out , MAR in ,Read

5 R1out , Y in , WMF C6 MDRout ,SelectY,Add, Zin7 Zout , R1in , End

•Each step in this sequence is completed in one clock cycle. •A counter may be used to keep track of the control steps.•Each state or count, of this counter corresponds to one control step.

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Hardwired control (contd..)

• Required control signals are determined by the following information:– Contents of the control step counter.

• Determines which step in the sequence.– Contents of the instruction register.

• Determines the actual instruction– Contents of the condition code flags.

• Used for example in a BRANCH instruction. – External input signals such as MFC.

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Hardwired control (contd..)Control unit organization

CLKClock Control step

IR encoderDecoder/

codes

counter

inputs

Condition

External

Control signals

•Control unit consists ofa decoder/encoder block toaccept the following inputs: - Control step counter. - Instruction Register. - Condition codes - External inputs.•Generates control signals.

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Hardwired control (contd..)

Externalinputs

Encoder

ResetCLKClock

Control signals

counter

Run End

Conditioncodes

decoderInstruction

Step decoder

Control step

IR

T1 T2 Tn

INS 1

INS 2

INSm

Separate signal line for each step

Separate signal line for each instruction Combines inputs to generate

control signals

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Hardwired control (contd..)Control signals such as Zin, PCout, ADD are generated by encoder block

Suppose if Zin is asserted: - During T1 for all instructions. - During T6 for ADD instruction. - During T4 for unconditional BRANCH instruction - ..............

T1

ADDBRANCH

T4 T6

....... 461 BRANCHTADDTTZ in

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Hardwired control (contd..)• Control hardware can be viewed as a state machine:

– Changes state every clock cycle depending on the contents of the instruction register, condition codes, and external inputs.

• Outputs of the state machine are control signals:• Sequence of control signals generated by the machine is

determined by wiring of logic elements, hence the name “hardwired control”.

• Speed of operation is one of the advantages of hardwired control is its speed of operation.

• Disadvantages include:– Little flexibility.– Limited complexity of the instruction set it can implement.

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Microprogrammed control

• Hardwired control generates control signals using:– A control step counter.– Decoder/encode circuit.

• Microprogrammed control:– Control signals are generated by a program similar to machine language

programs.

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Microprogrammed control (contd..)Control Word (CW) is a word whose individual bits represent variouscontrol signals.

Step Action

1 PCout , MAR in ,Read,Select4,Add, Zin2 Zout , PC in , Yin , WMFC3 MDRout , IRin

4 R3out , MAR in ,Read5 R1out , Yin , WMFC6 MDRout ,SelectY,Add, Zin7 Zout , R1in , End

Control Signals:PCout

PCin

MARin

ReadMDRout

IRin

Yin

SelectYSelect4AddZin

Zout

R1out

R1in

R3out

WMFCEnd ......

At every step, some control signals are asserted (=1) and all others are 0.

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Microprogrammed control (contd..)

PCin

PCou

t

MA

Rin

Rea

d

MD

R out

IRin

Yin

Sele

ct

Add Z in

Z out

R1 ou

t

R1 i

n

R3 o

ut

WM

FC

End

01

0

00

0

0

00

0

00

0

1

10

0

00

0

0

10

0

10

0

0

10

0

10

0

0

00

1

00

1

0

00

1

00

0

0

01

0

01

0

0

10

0

00

0

0

10

0

00

1

0

10

0

00

1

0

01

0

00

0

1

00

0

01

0

0

00

0

00

0

1

00

0

10

0

0

01

0

01

0

0

Micro -instruction

12

3

45

6

7

•At every step,a Control Word needs to be generated.•Every instruction will need a sequence of CWs for its execution.•Sequence of CWs for an instruction is the microroutine for the instruction.•Each CW in this microroutine is referred to as a microinstruction.

(SelectY is represented by Select=0, & Select4 by Select=1)

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• Every instruction will have its own microroutine which is made up of microinstructions.

• Microroutine for all instructions in the instruction set of a computer are stored in a special memory called Control Store.

• Recall that the Control Unit generates the control signals:– Sequentially reading the CWs of the corresponding microroutine from the control

store.

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storeControl

generator

Startingaddress

CW

Clock mPC

IR

Basic organization of a microprogrammed control unit.

•Microprogram counter (mPC) is used to read CWs from control store sequentially.•When a new instruction is loaded into IR,Starting address generator generates thestarting address of the microroutine. •This address is loaded into the mPC.mPC is automatically incremented by the clock, so successive microinstructions areread from the control store.

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• Basic organization of the microprogrammed control unit cannot check the status of condition codes or external inputs to determine what should be the next microinstruction.

• Recall that in the hardwired control, this was handled by an appropriate logic function.

• How to handle this in microprogrammed control:– Use conditional branch microinstructions. – These microinstructions, in addition to the branch address also specify which of the

external inputs, condition codes or possibly registers should be checked as a condition for branching.

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Microprogrammed control (contd..)AddressMicroinstruction

0 PCout , MARin ,Read,Select4,Add, Zin1 Zout , PC in , Yin , WMFC2 MDRout , IRin3 Branchtostartingaddressofappropriatemicroroutine. ... .. ... ... .. ... .. ... ... .. ... ... .. ... .. ... ... .. ... .. ... ... .. ... ..25 IfN=0, thenbranchtomicroinstruction026 Offset-field-of-IRout ,SelectY,Add, Zin27 Zout , PC in , End

Fetch BRANCH<0 instruction,microroutine is at address 25.

Branch to address 25.

Test the N bit of the conditioncodes If 0, go to 0 and get new instr. Else execute microinstruction located at 26 and put the branch target address into Register Z. (Microinstruction at location 27).

Address 25 is the output of starting address generator and is loaded into the microprogram counter (mPC).

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Microprogrammed control (contd..)Control Unit with Conditional Branching in the Microprogram

Controlstore

Clock

generator

Starting andbranch address Condition

codes

inputsExternal

CW

IR

mPC

Starting and branch address generator insteadof starting address generator.

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Microprogrammed control (contd..)• Starting and branch address generator accepts as inputs:

– Contents of the Instruction Register (as before).– External inputs

– Condition codes • Generates a new address and loads it into microprogram

counter (mPC) when a microinstruction instructs it do so.• mPC is incremented every time a microinstruction is

fetched except:– New instruction is loaded into IR, mPC is loaded with the starting address of the microroutine for

that instruction.– Branch instruction is encountered and branch condition is satisfied, mPC is loaded with the

branch address.– End instruction is encountered, mPC is loaded with the address of the first CW in the microroutine

for the instruction fetch cycle.

A Complete Processor

Chapter 3 Basic Processing Unit.

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Transcript of Chapter 3 Basic Processing Unit.