Chapter 19 - Simulators and Emulators for Different Abstraction Layers of UHF RFID Systems
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Transcript of Chapter 19 - Simulators and Emulators for Different Abstraction Layers of UHF RFID Systems
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Chapter 19 - Simulators and Emulators for Different Abstraction
Layers of UHF RFID Systems
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Figure 19.1 Abstract overview of simulation/emulation cases
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Figure 19.2 Tag Classes: UHF RFID Tags
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Figure 19.3 Test Components
(b) Interoperability Test Components(a) Conformance Test Components
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Figure 19.4 System level design flow based on the methodology
proposed
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(a) Simulation platform (b) Real-time verification platform
Figure 19.5 Components of implementation of the proposed
methodology
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Figure 19.6 Layers of a framework for UHF RFID system modeling
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Figure 19.7 Hardware layer structure of the framework for
UHF RFID system modeling
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Figure 19.8 Structure of the software layer for UHF RFID system
modeling
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Figure 19.9 Different implementations of a tag
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Figure 19.10 Communication path between major modules
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Figure 19.11 Example of an application specific layout
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Figure 19.12 Simulation Platform for Multi-layer optimization
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(a) Carrier and baseband signals separation in the model - splitting in two components: (i) envelope and (ii) carrier frequency and phase
(b) Separation of frequency and time domain analyses
Figure 19.13 RF to baseband modeling approach
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Figure 19.14 Reader demodulator: phase vs. amplitude
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Figure 19.15 Pre-computing and considering power off times
(a) Pre-computing of Application-layer specifications for system simulation
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(b) Gated data and clock signals represent tag inputs considering power-off times in time-discrete models
Figure 19.15 Pre-computing and considering power off times
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Table 19.1 Simulation and system performance
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Figure 19.16 Cosimulation of the model with physical devices.
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Figure 19.17 Parallel simulation of tags
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Figure 19.18 Complete system of the tag emulator
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Figure 19.19 Oscilloscope screen shot of a correct reader
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Figure 19.20 Structure of a higher class (active) UHF RFID tag
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Figure 19.21 Mapping of the functional blocks on the tag
hardware units
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Figure 19.22 Full baseband tag inventory sequence
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a) Two level simulation set up
Figure 19.23 Lifetime Simulation of higher class tags
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(b) System level simulation - simulation principle
Figure 19.23 Lifetime Simulation of higher class tags
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Table 19.2 Container transport simulation scenario settings
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(b) Container tracking simulation results for two wake-up cycles: 4.8 s (a) and 2.8 s (b) - DPM: dynamic power management, EHD: energy harvesting device
(a) Container surveillance simulation environment setup
Figure 19.24 Logistics - container transport