Chapter 11 BOL Processes

1

BACKEND TECHNOLOGY – Chapter 11

Introduction

• Backend technology: fabrication of interconnects and the dielectrics that electrically isolate them. • Early structures were simple by today's standards.

Oxide

Silicon

Aluminum

N+

Oxide

• More metal interconnect levels increases circuit functionality and speed. • Interconnects are separated into local interconnects (polysilicon, silicides, TiN) and intermediate/ global interconnects (Cu or Al).• Backend processing is becoming more important.• Larger fraction of total structure and processing.• Starting to dominate total speed of circuit.

(From ITRS)SILICON VLSI TECHNOLOGYFundamentals, Practice and ModelingBy Plummer, Deal & Griffin

© 2000 by Prentice HallUpper Saddle River NJ

3

Back-End Technology

Al Cu

silicides

BACK – END TECHNOLOGY

(Back Of Line)

Front – End Technology

Gate & Local interconnects will give delay with scaling global interconnects will delay !

4

METAL 2

METAL 1METAL 1

W VIA

POLYCIDE

W CONTACT

Year of Production 1998 2000 2002 2004 2007 2010 2013 2016 2018

Technology Node (half pitch) 250 nm 180 nm 130 nm 90 nm 65 nm 45 nm 32 nm 22 nm 18 nm

MPU Printed Gate Length 100 nm 70 nm 53 nm 35 nm 25 nm 18 nm 13 nm 10 nm

Min Metal 1 Pitch (nm) 214 152 108 76 54 42

Wiring Levels - Logic 10 11 12 12 14 14

Metal 1 Aspect Ratio (Cu) 1.7 1.7 1.8 1.9 2.0 2.0

Contact Aspect Ratio (DRAM) 15 16 >20 >20 >20 >20

STI Trench Aspect Ratio 4.8 5.9 7.9 10.3 14 16.4

Metal Resistivity (µohm-cm) 3.3, 2.2 2.2 2.2 2.2 2.2 2.2 2.2 2.2 2.2

Interlevel Dielectric Constant 3.9 3.7 3.7 <2.7 <2.4 <2.1 <1.9 <1.7 <1.7

Back-End Technology_ Dimensions

SILICON VLSI TECHNOLOGYFundamentals, Practice and ModelingBy Plummer, Deal & Griffin


5

Interconnects

scaling

larger X-sections, thicker dielectrics

Global inter. delay

usually 200 - 350 mm2

C of adjacent lines

C – line to substrate

RC delay

For min feature size Fmin

3 -5 nsecFmin

AP (Aintercon R & Cdiel

with chip area

•› › ⇑

W

Poly

1 10 100

Fmin = 0.25 μm

τg

10

10

10-10

10-9

10-8

-12

-11

AlW

Poly

1 10 100

Fmin = 0.5 μm

τg

Poly (ρ=500

μΩcm)

WSi2 (ρ

=30 μΩ

cm)

W (ρ=10

μΩcm)

Al (ρ

=3 μΩ

cm)

1 10 100

Fmin = 1 μm

τg

Delay Time (sec)

Chip Area (mm2)

CuτL

τL

τL

WSi2

WSi2

Al

• The speed limitations of interconnects can be estimated fairly simply.

• The time delay (rise time) due to global interconnects is:

Dielectric constant of the oxide Kox

K1 - accounts for the fringing fields

Gate delay

Ex. =3e-6Ωcm, SiO2=3.9, A=100mm2

, Fmin=0.35µm

L=0.75ns (increases with chip A due to R)

Global delay increases



6

Scaling: Contacts & Interconnects

ñrå

Global

Global

Self - alignedSelf - aligned

Self - aligned

50% delay from interconnectsEarlier:15-20%, then 30-40% (delay increases with scaling)

7 SILICON VLSI TECHNOLOGYFundamentals, Practice and ModelingBy Plummer, Deal & Griffin


8

• More sophisticated analysis from the 2003 ITRS interconnect roadmap. • Global interconnects dominate the RC delays.• “In the long term, new design or technology solutions (such as co-planar waveguides, free space RF, optical interconnect) will be needed to overcome the performance limitations of traditional interconnect.” (ITRS)

Historical Development and Basic ConceptsContacts

Oxide

Silicon

Aluminum

N+

Oxide

• Early structures were simple Al/Si contacts.• Highly doped silicon regions are necessary to insure ohmic, low resistance contacts.

€

c = coexp2φB m*s

h ND

⎛

⎝

⎜ ⎜

⎞

⎠

⎟ ⎟

(2)

• Tunneling current through a Schottky barrier depends on the width of the barrier and hence ND. • In practice, ND, NA > 1020 are required.

Delay Due to Metal 1 and Global



9

Aluminum Metallization

high compressive stress in Al during annealing

large

All silicides give self-aligned contacts contact area R

passive

Al contact: SiO2 native reduced good ohmic! Al2O3 forms, very stable adhesion to SiO2

0++CAddSi1%toAl,Sicanprecipitate(450C)p(Si+Al)R(fornlayers)USEBARRIERSINSTEAD→→↑ ⇒ :

Qit

duringannealing@ 450 0C H formation

High SS of Si in Al

0.5% 4500C

High Si diff in Al SPIKES!in local spots

Al - 2-3 µm junctions only!Ti as asacrificedBarrier TiSi2 &TiN (=diffusionbarrier)

Better solution

10

Contacts - Electrical Parameters

thermionic emission

Schottky = rectifying

Tunneling

Surface states in Si pin F-level deep in the E-gap no metal gives B

for n – Si contact resistance & rectifying contact

thermionic emission

Tunneling contact

Thickness of depletion = tunneling layer

2.5 nmresults fromNd=6. 1019 cm-3

contact area

-3-3B-72C-22C1910cm-62C2010cmoex:ö=0.6Vñ=10Ùcm ñ|=5.9.10Ùcm ñ|=6.7.10Ùcm ROLEOFCONCENTRATION

Depends on metal/semiconductor

Rc[Ω]=[Ωcm]/A[cm2]

c|1019cm-3=5.9•10-2Ωcm2

c|1020cm-3=6.7•10-6Ωcm2

c≈10-9Ωcm2 will be needed

Role of concentration

11

Silicides and Polycides

gate

contacts

local interconnects (require a-Si deposition)

SALICIDE PROCESS

sputtering

T (~ 600 0C )C 49 Ti Si2 - high resistive

T ( > 800 0C )C 54 Ti Si2 - low resistive Larger grains

Ti also against electromigration

12

Silicides

Good adhesion

Problems :adhesion stability

stress

large

SILICON CONSUMPTION

striped

CoSi2 does not cause problems with resistivity for very narrow lines

13

• Some front-end models have also been applied to back-end processing.

Silicon

Ti

TiSi2

Si

Si + Ti → TiSi2

Silicon

Ti

TiSi2

Si

Si + Ti → TiSi2

TiNN

N+ Ti → TiN

a) b)

newly 2formed TiSi • Silicide formation is often

modeling using the Deal-Grove linear-parabolic model.

€

xs2

B+

xsB / A

= t+ or

xs =A2

1+ t+

A2 / 4B−1

⎧ ⎨ ⎪

⎩ ⎪

⎫ ⎬ ⎪

⎭ ⎪ (7)

ˇ

-0.8 -0.4 0.0 0.4 0.8 y in microns

-0.4

-0.2

0

0.2

0.4

x in micronsSilicon

Titanium

Polysilicon

Silicon dioxide

Oxide spacer

m€m∂€∂€m∂m∂€m€m∂€∂€m∂m∂€m€m∂€∂€m∂m∂€m€m∂€∂€m∂m∂€m€m∂€∂€m∂m∂€m€m∂€∂€m∂m∂€m€m∂€∂€m∂m∂€m€m∂€∂€m∂m∂€m€m∂€∂€m∂m∂€m€m∂€∂€m∂m∂€m€m∂€∂€m∂m∂€m€m∂€∂€m∂m∂€m€m∂€∂€m∂m∂€m€m∂€∂€m∂m∂€m€m∂€∂€m∂m∂€m€m∂€∂€m∂m∂€m€m∂€∂€m∂m∂€m€m∂€∂€m∂m∂€m€m

x in microns

Silicon

TitaniumTitanium silicideTitaniumnitride

TitaniumsilicideSilicon

dioxide

Pinning point

-0.8 -0.4 0.0 0.4 0.8 y in microns

-0.4

-0.2

0

0.2

0.4

• Simulation of TiSi2 formation using FLOOPS [11.32] on a 0.35 m wide gate structure. Left: before formation anneal step. Right: after formation anneal step: 30 sec at 650˚C in a nitrogen atmosphere

TiSi2 Salicide Formation



14

TiSi2 Salicide FormationSi is the diffuser for

CoSi2

TiSi2

Creep - up

short G - S

Less lateral encroachment

Consumption of Silicon Large :

Ti Si2 = 138 nm from Ti = 55 nmSi consumed = 125 nm

fast diffusion

Linear coefficient = fast reaction

conductive

Growth as in the oxidation process: parabolic and linear

15

Silicide Formation and Scaling of Devices

650 0C/ 30” Ar

@ the top of the oxide spacer

TiN growth:20% of TiSi2 linear growth rate 32.5 nm Ti 44 nm Si

50 nm TiSi2 + 27 nm TiN

Not all Ti consumed

See Deal & Grove

Linear / Parabolic growth

Anneal now in N2

2widegatemμ2µm wide channel

0.35µm wide channel

48 nm TiSi2 from 43 nm SiStress important:

include mechanical parameters

16

For 1 nm of metal (Ti, Co, Ni):TiSi2 - 2.27 nm Si usedCoSi2 - 3.64 nm SiNiSi -1.83 nm Si

18

Electrical Measurements of Contacts

gives overestimation( RC ) of thecontact properties

Low resistance

KELVIN BRIDGE

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Multilevel Metallization

Non – planar surface :

(1) Lithography issues• depth of focus• resist thinning• UV light reflections

(2) Step coverage & filling

Use planarization

FINAL GOAL

FOR ADHESION & DIFFUSION BARRIER

FOR ADHESION

• Early two-level metal structure (early 1980’s). Non-planar topography leads to lithography, deposition, filling issues.• These issues get worse with additional levels of interconnect and required a change in structure.

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Planarization

selective deposition

GOOD PLANARITY BY FILLING VIAS

21

xstepi

xstepf

DOP = 0

DOP = 1

xstepi

xstep= 0f

xstepf

DOP = 0.5

xstepi

Degree of planarization is

€

DOP =1−xstep

f

xstepi (3)

W plug

Oxide

Silicon or Al

TiN

Blanket W

Etchback W

• One early approach to planarization incorporated W plugs and a simple etchback process. (Damascene process.)• SPEEDIE simulation below.

-0.50.00.51.01.52.0

-1.00 1.000.0microns

microns

-2.00 2.00

2.5

Planarization: definition and simulation



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Al or Cu

Metal 1

Silicon

1st Level Dielectric

Deposit thickIMD

Etch via holesand interconnecttrenches

Deposit TiNand thick metal

Etchback(plasma etch or

CMP) metaland TiN

Metal 2

Via

Metal 1

Thin Si3N4layer foretch stop

• More advanced version of the damascene process provides both the via/contact and interconnect levels simultaneously. • In this “dual damascene” process, both the openings in the IMD for the metal interconnect and for the contact or vias underneath are opened, one after the other. • Metal is then deposited into both layers at once followed by a CMP etchback.

• Interconnects have also become multilayer structures.• Shunting the Al helps mitigate electromigration and can provide mechanical strength, better adhesion and barriers in multi-level structures. TiN on top also acts as antireflection coating for lithography.

Al

Ti

Ti

Void in Al line

I

Oxide

Planarization

Planarization Also Helps Against Electromigration



23

Dielectrics

LocalInterconnects

GlobalInterconnects

Vias

ContactsIntermetalDielectric

First LevelDielectric

• Dielectrics electrically and physically separate interconnects from each other and from active regions. • Two types: - First level dielectric - Intermetal dielectric (IMD)

BPSG

• First level dielectric is usually SiO2 “doped” with P or B or both (2-8 wt. %) to enhance reflow properties. • PSG: phosphosilicate glass, reflows at 950-1100˚C• BPSG: borophosphosilicate glass, reflows at 800˚C.• SEM shows BPSG oxide layer after 800˚C reflow step, showing smooth topography over step. • Undoped SiO2 often used above and below PSG or BPSG to prevent corrosion of Al .



24

ILM DIELECTRICS

BPSG used for planarization

25

• Intermetal dielectrics also made primarily of SiO2 today, but cannot do reflow or densification anneals on pure SiO2 because of T limitations.• Two common problems occur, cusping and voids, which can be minimized using appropriate deposition techniques.

Œ

-0.5

0.0

0.5

1.0

1.5

2.0

-1.00 1.000.0microns

-2.00 2.00

2.5

microns

Œ

-0.5

0.0

0.5

1.0

1.5

2.0

-1.00 1.000.0microns

-2.00 2.00

2.5

microns

• SPEEDIE simulations of silicon dioxide depositions over a step for silane deposition (Sc = 0.4) and TEOS deposition (Sc = 0.1) showing less cusping in the latter case.

b) Local planarization

c) Global planarization

Oxide

a) No planarization• However planarization is also usually required today.

Planarization



26

Etchback tohereOxide

Photoresist

Silicon

AlMetal 1

SOG

CVDOxide

ViaAl - Metal 2

Silicon

AlMetal 1

Al - Metal 2

Via SOG

CVDOxide

CVDOxide

SOGSOG

CVDOxide

CVDOxide

AlMetal 1

Via

• One simple process involves planarizing with photoresist and then etching back with no selectivity.

• Spin-on-glass (SOG) is another option: • Fills like liquid photoresist, but becomes SiO2 after bake and cure. • Done with or without etchback (with etchback to prevent poisoned via - no SOG contact with metal). • Can also use low-K SOD’s. (spin-on-dielectrics) • SOG oxides not as good quality as thermal or CVD oxides • Use sandwich layers.

• A final deposition option is HDPCVD (see chapter 9) which provides angle dependent sputtering during deposition which helps to planarize.with etchback

without etchback

Planarization



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Planarization Techniques

Reflow

CMP appears as a dominating method

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Wafer carrierWafer

Polishing pad

Polishing table

Slurry(facing down)

Close-up of wafer/pad interface:

Polishing pad(semi-rigid)

Silicon

Oxideslurry

Deposit thick oxide

Plasma etchback

Locally planarized topography remains

CMP

Globally planarized topography remains

• The most common solution today is CMP which works very well.• It is capable of forming very flat surfaces as shown in the example below.

CMP



29

Al(Cu) - Metal 1TiTiN

TiN

TiN Ti

TiNAl(Cu) - Metal 2

Silicon TiSi2TiN

W

W

N+

Oxide

• Typical modern interconnect structure incorporating all these new features.

• The biggest change that has occurred in the past 5 years is the widespread introduction of Cu, replacing aluminum. • Cu cannot be easily etched since the byproducts, copper halides are not volatile at room temperature.• Electroplating (see text section 9.3.10) plus a damascene process (single or dual) is the obvious solution and is widely used today. • Cu is the dominant material in logic chips today (µp, ASICs), but not in most memory chips.

Copper Interconnects



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Metal 1

Metal 2

W

Field OxideN+

W

Silicon

CVD SiO2BPSG

PECVD SiO2

PECVD SiO2

PECVD SiO2

CVD SiO2

With PECVD oxide/PECVD nitride passivation bilayeron top of final metal level

PECVD SiO2

SOG or SOD

SOG or SOD

• Backend structure showing one possible dielectric multi-structure scheme. Other variations include HDP oxide or the use of CMP.

• Two backend structures. Left: three metal levels and encapsulated BPSG for the first level dielectric; SOG (encapsulated top and bottom with PECVD oxide) and CMP in the intermetal dielectrics. The multilayer metal layers and W plugs are also clearly seen. Right: five metal levels, HDP oxide (with PECVD oxide on top) and CMP in the intermetal dielectrics.

Multilevel Metallization


31

Interconnects And Vias

• Al has historically been the dominant material for interconnects.- low resistivity- adheres well to Si and SiO2

- can reduce other oxides- can be etched and deposited easily

• Problems: -relatively low melting point and soft.-need a higher melting point material for gate electrode and local

interconnect polysilicon. - hillocks and voids easily formed in Al.

Compressive stress in Al

(due to thermalexpansiondifference

between film andsubstrate)

Al hillock

Al Al Grainboundary

Grain

Al film

SiO2 film

Compressive stress in Al

σ σ

Si substrate

• Hillocks and voids form because of stress and diffusion in Al films. Heating places Al under compression causing hillocks. Cooling back down can place Al under tension voids. • Adding a few % Cu stabilizes grain boundaries and minimizes hillock formation.



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Al film

Electron flow

HillockVoid

Cathode Anode

SiO2 film

Al

• A related problem with Al interconnects is “electromigration.” High current density (0.1-0.5 MA/cm2) causes movement of Al atoms in direction of electron flow. • Can cause hillocks and voids, leading to shorts or opens in the circuit. • Adding Cu (0.5-4 weight %) can also inhibit electromigration.• Thus Al is commonly deposited with 1-2 wt % Si and 0.5-4 wt % Cu.

Oxide

Si

Al

N+

OxidePoly Si

2

1

3

TiSi2

TiSi2 TiSi2

• Next development was use of other materials with lower resistivity as local interconnects, like TiN and silicides. • Silicides used to 1. strap polysilicon, 2. Strap junctions, 3. as a local interconnect.

Electromigration



33

Mechanical Properties of Al

protrusion of Al

Al short

Si O2 may crackheating

HEATING :

Large thermal expansion coefficient compressive stress hillock shorts Add Cu Al diffusion by segregating @ the Al grain boundary

COOLING : void formation Cu helps again Al diffusion

agglomeration of Al atoms

Grain boundary diffusion

0.1 – 0.5 mAcm-2

ELECTROMIGRATION --- depends on grain structure & sizeCu helps - 4 wt % (avoid corrosion & etching problems )Si added helps EM but PR

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Electromigration

35

Electromigration

36

Grain Growth

37

THE FUTURE OF BACKEND TECHNOLOGY

L = 0.89RC = 0.89⋅KIKoxεoρL2 1

Hxox+

1

WLS

⎛

⎝ ⎜

⎞

⎠ ⎟• Remember: (1)

• Reduce metal resistivity - use Cu instead of Al.• Aspect ratio - advanced deposition, etching and planarization methods.• Reduce dielectric constant - use low-K materials.

Year of Production 1998 2000 2002 2004 2007 2010 2013 2016 2018

Technology Node (half pitch) 250 nm 180 nm 130 nm 90 nm 65 nm 45 nm 32 nm 22 nm 18 nm

MPU Printed Gate Length 100 nm 70 nm 53 nm 35 nm 25 nm 18 nm 13 nm 10 nm

Min Metal 1 Pitch (nm) 214 152 108 76 54 42

Wiring Levels - Logic 10 11 12 12 14 14

Metal 1 Aspect Ratio (Cu) 1.7 1.7 1.8 1.9 2.0 2.0

Contact Aspect Ratio (DRAM) 15 16 >20 >20 >20 >20

STI Trench Aspect Ratio 4.8 5.9 7.9 10.3 14 16.4

Metal Resistivity (µohm-cm) 3.3, 2.2 2.2 2.2 2.2 2.2 2.2 2.2 2.2 2.2

Interlevel Dielectric Constant 3.9 3.7 3.7 <2.7 <2.4 <2.1 <1.9 <1.7 <1.7



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Material class Material Dielectricconstant

Depositiontechnique

Inorganic SiO2 (including PSGand BPSG)

3.9-5.0 CVD/Thermalox./Bias-

sputtering/HDP

Spin-on-glass (SiO2)(including PSG, BPSG)

3.9-5.0 SOD

Modified SiO2

(e.g. fluorinated SiO2

or hydrogensilsesquioxane - HSQ)

2.8-3.8 CVD/SOD

BN (Si) >2.9 CVDSi3N4 (only used in

multilayer structure)5.8-6.1 CVD

Organic Polyimides 2.9-3.9 SOD/CVDFluorinated polyimides 2.3-2.8 SOD/CVD

Fluoro-polymers 1.8-2.2 SOD/CVDF-doped amorphous C 2.0-2.5 CVD

Inorganic/Org-anic Hybrids

Si-O-C hybridpolymers based on

organo-silsesquioxanes(e.g. MSQ)

2.0-3.8 SOD

Aerogels(Microporous)

Porous SiO2 (with tinyfree space regions)

1.2-1.8 SOD

Air bridge 1.0-1.2

• All of these approaches are beginning to appear in advanced process flows today.

Inter Level Dielectrics



39

Summary of Key Ideas

• Backend processing (interconnects and dielectrics) have taken on increased importance in recent years.

• Interconnect delays now contribute a significant component to overall circuit performance in many applications.

• Early backend structures utilized simple Al to silicon contacts.

• Reliability issues, the need for many levels of interconnect and planarization issues have led to much more complex structures today involving multilayer metals and dielectrics.

• CMP is the most common planarization technique today.

• Copper and low-K dielectrics are now found in some advanced chips and their use will likely be common in the future.

• Beyond these materials changes, interconnect options in the future include architectural (design) approaches to minimizing wire lengths, optical interconnects, electrical repeaters and RF broadcasting. All of these areas will see significant research in the next few years.



Chapter 11 BOL Processes

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