Chapter 10 Interruptsgalia.fc.uaslp.mx/~rmariela/RTDSP/unit5_1.pdf · 2012-02-25 · Introduction...
Transcript of Chapter 10 Interruptsgalia.fc.uaslp.mx/~rmariela/RTDSP/unit5_1.pdf · 2012-02-25 · Introduction...
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Chapter 10Chapter 10InterruptsInterrupts
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Learning ObjectivesLearning Objectives
�� Introduction to interrupts.Introduction to interrupts.�� Types of interrupts and sources.Types of interrupts and sources.
�� Interrupt timeline.Interrupt timeline.�� Handling and processing interrupts Handling and processing interrupts
using C and assembly code.using C and assembly code.
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004Chapter 10, Slide 2
using C and assembly code.using C and assembly code.
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IntroductionIntroduction
�� Interrupts are used to interrupt normal Interrupts are used to interrupt normal program flow so that the CPU can program flow so that the CPU can respond to events.respond to events.
�� The events can occur at anytime.The events can occur at anytime.Program
Inst 1
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004Chapter 10, Slide 3
Inst 1Inst 2
::
Inst nInterrupt occurs here }
Save the contents of theregisters and the context of
the current process
Service the interrupt task
Restore the contents of theregisters and the context of
the current process
Resume the original process
Inst n+1Inst n+2
::
This contains the InterruptService Routine (ISR)
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CPU Interrupts and SourcesCPU Interrupts and SourcesCPU IntCPU Int
RESETRESETNMINMI
reservedreservedreservedreserved
INT4INT4INT5INT5INT6INT6INT7INT7
SourcesSources(HPI)(HPI) DSPINTDSPINT
TINT0TINT0TINT1TINT1
SD_INTSD_INTEXT_INT4EXT_INT4EXT_INT5EXT_INT5EXT_INT6EXT_INT6EXT_INT7EXT_INT7
DescriptionDescriptionHPI InterruptHPI Interrupt
Timer 0Timer 0Timer 1Timer 1
SDRAM RefreshSDRAM RefreshExternal Interrupt 4External Interrupt 4External Interrupt 5External Interrupt 5External Interrupt 6External Interrupt 6External Interrupt 7External Interrupt 7
PPrriioo
HighHigh
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004Chapter 10, Slide 4
INT7INT7INT8INT8INT9INT9
INT10INT10INT11INT11INT12INT12INT13INT13INT14INT14INT15INT15
EXT_INT7EXT_INT7DMA_INT0DMA_INT0DMA_INT1DMA_INT1DMA_INT2DMA_INT2DMA_INT3DMA_INT3
XINT0XINT0RINT0RINT0XINT1XINT1RINT1RINT1
External Interrupt 7External Interrupt 7DMA Channel 0DMA Channel 0DMA Channel 1DMA Channel 1DMA Channel 2DMA Channel 2DMA Channel 3DMA Channel 3
McBSP Channel 0 TXMcBSP Channel 0 TXMcBSP Channel 0 RXMcBSP Channel 0 RXMcBSP Channel 1 TXMcBSP Channel 1 TXMcBSP Channel 1 RXMcBSP Channel 1 RX
oorriittyy
LowLow
Note that there are more sources of interrupt than the CPU can handle.Note that there are more sources of interrupt than the CPU can handle.
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CPU Interrupts and SourcesCPU Interrupts and Sources
RESETRESETRESETRESETRESETRESETRESETRESET
INT4INT4
NMINMI
IACKIACKINUM3INUM3INT5INT5
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004Chapter 10, Slide 5
�� The IACK and INUM pins do not exist The IACK and INUM pins do not exist on the C621x, C671x and C64x devices.on the C621x, C671x and C64x devices.
'C6x'C6xINUM3INUM3INT5INT5
INT6INT6
INT7INT7
INUM2INUM2INUM1INUM1INUM0INUM0
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Interrupt SelectionInterrupt SelectionCPU IntCPU Int
RESETRESETNMINMI
reservedreservedreservedreserved
INT4INT4INT5INT5INT6INT6INT7INT7
SourcesSources(HPI)(HPI) DSPINTDSPINT
TINT0TINT0TINT1TINT1
SD_INTSD_INTEXT_INT4EXT_INT4EXT_INT5EXT_INT5EXT_INT6EXT_INT6EXT_INT7EXT_INT7
DescriptionDescriptionHPI InterruptHPI Interrupt
Timer 0Timer 0Timer 1Timer 1
SDRAM RefreshSDRAM RefreshExternal Interrupt 4External Interrupt 4External Interrupt 5External Interrupt 5External Interrupt 6External Interrupt 6External Interrupt 7External Interrupt 7
PPrriioo
HighHigh
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004Chapter 10, Slide 6
INT7INT7INT8INT8INT9INT9
INT10INT10INT11INT11INT12INT12INT13INT13INT14INT14INT15INT15
EXT_INT7EXT_INT7DMA_INT0DMA_INT0DMA_INT1DMA_INT1DMA_INT2DMA_INT2DMA_INT3DMA_INT3
XINT0XINT0RINT0RINT0XINT1XINT1RINT1RINT1
External Interrupt 7External Interrupt 7DMA Channel 0DMA Channel 0DMA Channel 1DMA Channel 1DMA Channel 2DMA Channel 2DMA Channel 3DMA Channel 3
McBSP Channel 0 TXMcBSP Channel 0 TXMcBSP Channel 0 RXMcBSP Channel 0 RXMcBSP Channel 1 TXMcBSP Channel 1 TXMcBSP Channel 1 RXMcBSP Channel 1 RX
oorriittyy
LowLow
Each source interrupt can be made to trigger a specific CPU interrupt.Each source interrupt can be made to trigger a specific CPU interrupt.
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Interrupt SelectionInterrupt Selection
�� The interrupt source mapping can be The interrupt source mapping can be achieved by initialising the appropriate achieved by initialising the appropriate bitbit--fields of the interrupt multiplexer.fields of the interrupt multiplexer.
�� Each CPU interrupt has a selection Each CPU interrupt has a selection number “INTSEL#” that specifies the number “INTSEL#” that specifies the source.source.
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004Chapter 10, Slide 7
source.source.
Interrupt Multiplexer HighInterrupt Multiplexer High(INT10 - INT15) (address 0x19c0000)
Interrupt Multiplexer LowInterrupt Multiplexer Low(INT4 - INT9) (address 0x19c0004)
26262929INTSEL15INTSEL15
21212424INTSEL14INTSEL14
16161919INTSEL13INTSEL13
10101313INTSEL12INTSEL12
5588INTSEL11INTSEL11
0033INTSEL10INTSEL10
26262929INTSEL9INTSEL9
21212424INTSEL8INTSEL8
16161919INTSEL7INTSEL7
10101313INTSEL6INTSEL6
5588INTSEL5INTSEL5
0033INTSEL4INTSEL4
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Interrupt SelectionInterrupt Selection
�� Example: Mapping EXT_INT5 to CPU Example: Mapping EXT_INT5 to CPU INT12.INT12.
01010101 0x19c00000x19c0000
0x19c00040x19c0004
addressaddress1313 1010
Write 5Write 5decdec = 0101b to INTSEL12 = 0101b to INTSEL12
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004Chapter 10, Slide 8
Interrupt Multiplexer HighInterrupt Multiplexer High(INT10 - INT15) (address 0x19c0000)
Interrupt Multiplexer LowInterrupt Multiplexer Low(INT4 - INT9) (address 0x19c0004)
26262929INTSEL15INTSEL15
21212424INTSEL14INTSEL14
16161919INTSEL13INTSEL13
10101313INTSEL12INTSEL12
5588INTSEL11INTSEL11
0033INTSEL10INTSEL10
26262929INTSEL9INTSEL9
21212424INTSEL8INTSEL8
16161919INTSEL7INTSEL7
10101313INTSEL6INTSEL6
5588INTSEL5INTSEL5
0033INTSEL4INTSEL4
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Interrupt SelectionInterrupt Selection
�� Writing code to initialise INT12 with Writing code to initialise INT12 with 0101b, there are 3 methods:0101b, there are 3 methods:
(1) Using assembly:(1) Using assembly:MVKLMVKL 0x19c0000, A10x19c0000, A1
MVKHMVKH 0x19c0000, A10x19c0000, A1
LDWLDW *A1, A0*A1, A0
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004Chapter 10, Slide 9
(2) Using the Chip Support Library:(2) Using the Chip Support Library:
LDWLDW *A1, A0*A1, A0
CLRCLR A0, 10, 13, A0A0, 10, 13, A0
SETSET A0, 10, 10, A0A0, 10, 10, A0
SETSET A0, 12, 12, A0A0, 12, 12, A0
STWSTW A0, *A1A0, *A1
#include <intr.h>#include <intr.h>
#include <regs.h>#include <regs.h>
IRQ_map (IRQ_EVT_EXTINT5, 12);IRQ_map (IRQ_EVT_EXTINT5, 12);
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(3) Using the GUI interface:(3) Using the GUI interface:�� Open the CDB file.Open the CDB file.�� Select Hardware Interrupt Service Routine Manager.Select Hardware Interrupt Service Routine Manager.�� Select the CPU interrupt 12 (HWI_INT12) and right Select the CPU interrupt 12 (HWI_INT12) and right
click and select properties.click and select properties.�� Select External_Pin_5 as the interrupt source.Select External_Pin_5 as the interrupt source.
Interrupt SelectionInterrupt Selection
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004Chapter 10, Slide 10
�� Select External_Pin_5 as the interrupt source.Select External_Pin_5 as the interrupt source.
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Interrupt TimelineInterrupt TimelineConfigureConfigure
1. Select interrupt sources and map them.1. Select interrupt sources and map them.2. Create interrupt vector table.2. Create interrupt vector table.
EnableEnable3. Enable individual interrupts.3. Enable individual interrupts.4. Enable global interrupt.4. Enable global interrupt.
5. Check for valid signal.5. Check for valid signal.
User User ResponsibilityResponsibility(Initialisation)(Initialisation)
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004Chapter 10, Slide 11
5. Check for valid signal.5. Check for valid signal.
6. Once a valid signal is detected set flag bit.6. Once a valid signal is detected set flag bit.
7. Check if interrupt is enabled, if yes branch to ISR.7. Check if interrupt is enabled, if yes branch to ISR.
8. Write context store routine.8. Write context store routine.9. Write the ISR.9. Write the ISR.10.Write context restore routine.10.Write context restore routine.11.Return to main program.11.Return to main program.
Performed by the Performed by the CPUCPU
User User Responsibility Responsibility (Algorithm)(Algorithm)
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(2) Creating an Interrupt Vector(2) Creating an Interrupt Vector
�� When an interrupt occurs the CPU When an interrupt occurs the CPU automatically recognises the source of automatically recognises the source of the interrupt and jumps to the interrupt the interrupt and jumps to the interrupt vector location.vector location.
�� In this location a program is found In this location a program is found which instructs the processor on the which instructs the processor on the
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004Chapter 10, Slide 12
which instructs the processor on the which instructs the processor on the action(s) to be taken.action(s) to be taken.
�� Each vector location can accommodate Each vector location can accommodate eight instructions which correspond to a eight instructions which correspond to a fetch packet.fetch packet.
�� Such a location is know as the Interrupt Such a location is know as the Interrupt Service Fetch Packet (ISFP) address.Service Fetch Packet (ISFP) address.
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Interrupt service table ( IST )
Interrupt Sources ISFP Addresses
Reset 0x0000
NMI 0x0020
Reserved 0X0040
(2) Creating an Interrupt Vector(2) Creating an Interrupt Vector
�� The following table shows the interrupt The following table shows the interrupt sources and associated ISFP addresses:sources and associated ISFP addresses:
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004Chapter 10, Slide 13
Reserved 0X0060
INT4 0X0080
INT5 0X00A0
INT6 0X00C0
INT7 0X00E0
INT8 0X0100
INT9 0X0120
INT10 0X0140
INT11 0X0160
INT12 0X0180
INT13 0X01A0
INT14 0X01C0
INT15 0X01E0
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(2) Creating an Interrupt Vector(2) Creating an Interrupt Vector
�� Example 1: ISR fits into a single Fetch Example 1: ISR fits into a single Fetch Packet (FP).Packet (FP).
RESET
NMI
Res
0x0000
0x0020
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004Chapter 10, Slide 14
Res
Res
INT4
INT5
INT6
INT15
0x0080
MVKMVKHLDHLDHMVCSTRB IRPNOP 5
return from interrupt afterexecuting the FP
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(2) Creating an Interrupt Vector(2) Creating an Interrupt Vector
�� Example 2: ISR fits into multiple Example 2: ISR fits into multiple successive FP’s (assuming the next successive FP’s (assuming the next interrupts are not used).interrupts are not used).
RESET
NMI
Res
0x0000
0x0020
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004Chapter 10, Slide 15
Res
Res
INT4
INT5
INT6
INT15
0x0080
MVKMVKH
B IRPMVKMVKHZEROSTWLDH
return from interrupt afterexecuting the FP
INT7
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(2) Creating an Interrupt Vector(2) Creating an Interrupt Vector
�� Example 3: ISR is situated outside the Example 3: ISR is situated outside the interrupt vector table.interrupt vector table.
RESET
NMI
Res
0x0000
0x0020
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004Chapter 10, Slide 16
Res
Res
INT4
INT5
INT6
B IRPNOP 5
0x0080
MVKMVKHB ISRLDHMVCSTRSTRZERO
Branch to ISR after executingthe FP
ISR
Return from interrupt afterexecuting the ISR
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(2) Relocating the Vector Table(2) Relocating the Vector Table
�� In general the vector table or the section In general the vector table or the section “vectors” is linked to address zero.“vectors” is linked to address zero.
�� However in many applications there is a However in many applications there is a need to change the location of the vector need to change the location of the vector table.table.
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004Chapter 10, Slide 17
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(2) Relocating the Vector Table (2) Relocating the Vector Table
�� This is due to many factors such as:This is due to many factors such as:�� Moving interrupt vectors to fast memory.Moving interrupt vectors to fast memory.�� Having multiple vector tables for use by Having multiple vector tables for use by
different tasks.different tasks.�� Boot ROM already contained in memory Boot ROM already contained in memory
starting at address 0x0000.starting at address 0x0000.
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004Chapter 10, Slide 18
starting at address 0x0000.starting at address 0x0000.�� Memory starting at location zero is external Memory starting at location zero is external
and hence there will be a need to move the and hence there will be a need to move the vector table to internal memory to avoid bus vector table to internal memory to avoid bus conflict in shared memory system.conflict in shared memory system.
�� In order to relocate the vector table, the In order to relocate the vector table, the Interrupt Service Table Pointer (ISTP) Interrupt Service Table Pointer (ISTP) register should be set up.register should be set up.
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Interrupt service table ( IST )
Interrupt Sources ISFP Addresses
Reset ISTB + 0x0000
NMI ISTB + 0x0020
Reserved ISTB + 0X0040
Reserved ISTB + 0X0060
(2) Relocating the Vector Table(2) Relocating the Vector Table
reservedreservedISTBISTB3131 1010
ISTPISTP
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004Chapter 10, Slide 19
Reserved ISTB + 0X0060
INT4 ISTB + 0X0080
INT5 ISTB + 0X00A0
INT6 ISTB + 0X00C0
INT7 ISTB + 0X00E0
INT8 ISTB + 0X0100
INT9 ISTB + 0X0120
INT10 ISTB + 0X0140
INT11 ISTB + 0X0160
INT12 ISTB + 0X0180
INT13 ISTB + 0X01A0
INT14 ISTB + 0X01C0
INT15 ISTB + 0X01E0
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(2) Relocating the Vector Table(2) Relocating the Vector Table
�� Example: Relocate the ISTP to address Example: Relocate the ISTP to address 0x800.0x800.
(1) The interrupt vector code located between (1) The interrupt vector code located between 0x000 and 0x200 must be copied to the 0x000 and 0x200 must be copied to the location 0x800 and 0x800 + 0x200 (0xA00).location 0x800 and 0x800 + 0x200 (0xA00).
(2) Initialise the ISTP.(2) Initialise the ISTP.
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004Chapter 10, Slide 20
(2) Initialise the ISTP.(2) Initialise the ISTP.
MVKLMVKL 0x800, A00x800, A0
MVKHMVKH 0x800, A00x800, A0
MVCMVC A0, ISTPA0, ISTP
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nmienmie 11rsvrsvrsvrsvIE4IE4IE5IE5IE6IE6IE7IE7IE8IE8IE9IE9IE10IE10IE11IE11IE12IE12IE13IE13IE14IE14IE15IE15
1515 1414 1313 1212 1111 1010 99 88 77 66 55 44 33 22 11 00
3131 1616
ReservedReserved
R, W, +0R, W, +0 R,+1R,+1
(3) Enable Individual Interrupts(3) Enable Individual Interrupts
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004Chapter 10, Slide 21
�� Example: Write some code to enable INT7.Example: Write some code to enable INT7.
�� To enable each int, write “To enable each int, write “11” to IE bit ” to IE bit �� IER bits are NOT affected by the value in global IER bits are NOT affected by the value in global
interrupt enable (GIE)interrupt enable (GIE)
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(3) Enable Individual Interrupts(3) Enable Individual Interrupts
�� Method 1: Using “C” code.Method 1: Using “C” code.#include <c6x.h>#include <c6x.h>
void enable_INT7 (void)void enable_INT7 (void)
{{
IER = IER | 0x040;IER = IER | 0x040;
} }
�� Method 2: Using assembly.Method 2: Using assembly.
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004Chapter 10, Slide 22
_asm_set_INT7_asm_set_INT7
MVC .S2 IER, B0MVC .S2 IER, B0
SET .L2 B0,7, 7, B0SET .L2 B0,7, 7, B0
MVC .S2 B0, IERMVC .S2 B0, IER
�� Method 2: Using assembly.Method 2: Using assembly.
#include <csl.h>#include <csl.h>
#include <csl_irq.h>#include <csl_irq.h>
IRQ_enable (IRQ_EVT_EXTINT7)IRQ_enable (IRQ_EVT_EXTINT7)
�� Method 3: Using the CSL.Method 3: Using the CSL.
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(4) Enable Global Interrupt(4) Enable Global Interrupt
NMINMI
INT15INT15
IERIER CSRCSRGIEGIE
‘C6000‘C6000
CPUCPU
RESETRESET
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004Chapter 10, Slide 23
�� IER allows the enabling or disabling of IER allows the enabling or disabling of interrupts individually.interrupts individually.
�� GIE bit allows the enabling or disabling of GIE bit allows the enabling or disabling of interrupts globally (all at once).interrupts globally (all at once).Note: By disabling the GIE interrupts can be Note: By disabling the GIE interrupts can be prevented from occurring during initialisation.prevented from occurring during initialisation.
GIEGIE
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(4) Enable Global Interrupt(4) Enable Global Interrupt
�� Method 1: Using “C” code.Method 1: Using “C” code.#include <c6x.h>#include <c6x.h>
void enable_GIE (void)void enable_GIE (void)
{{
CSR = CSRIER | 0x1;CSR = CSRIER | 0x1;
} }
�� Method 2: Using assembly.Method 2: Using assembly.
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004Chapter 10, Slide 24
_asm_set_GIE_asm_set_GIE
MVC .S2 CSR, B0MVC .S2 CSR, B0
SET .L2 B0,0, 0, B0SET .L2 B0,0, 0, B0
MVC .S2 B0, CSRMVC .S2 B0, CSR
�� Method 2: Using assembly.Method 2: Using assembly.
#include <csl.h>#include <csl.h>
#include <csl_irq.h>#include <csl_irq.h>
IRQ_globalEnable ()IRQ_globalEnable ()
�� Method 3: Using the CSL.Method 3: Using the CSL.
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(4) Enable Global Interrupt(4) Enable Global InterruptRESET & NMI RESET & NMI
Reset: is not maskable. IER[0] = 1Reset: is not maskable. IER[0] = 1NMI: NMI: once the NMI is enabled it will be non once the NMI is enabled it will be non
maskable.maskable.�� NMIE bit enables the NMI.NMIE bit enables the NMI.
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004Chapter 10, Slide 25
So why have a non maskable interrupt that can So why have a non maskable interrupt that can be masked?be masked?
�� Avoids unwanted NMI interrupts occurring Avoids unwanted NMI interrupts occurring between the time of a reset and the end of between the time of a reset and the end of initialisation.initialisation.
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(4) Enable Global Interrupt(4) Enable Global InterruptRESET & NMI RESET & NMI
So how is the non maskable interrupt made So how is the non maskable interrupt made maskable?maskable?
�� Once the NMI is enabled it cannot be Once the NMI is enabled it cannot be disabled.disabled.
�� Also the NMI must be enabled before any Also the NMI must be enabled before any other interrupt (except reset) can be other interrupt (except reset) can be
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004Chapter 10, Slide 26
�� Also the NMI must be enabled before any Also the NMI must be enabled before any other interrupt (except reset) can be other interrupt (except reset) can be activated.activated.
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(5) Check for a Valid Signal (5) Check for a Valid Signal
INTxINTx
CPU ClockCPU Clock(CLKOUT1)(CLKOUT1)
InterruptInterruptlatchedlatched
InterruptInterruptrecognizedrecognized
Occurrence Occurrence of Interruptof Interrupt
2 cycles minimum2 cycles minimum 2 cycles minimum2 cycles minimum
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004Chapter 10, Slide 27
Conditions for recognition of an external interrupt:Conditions for recognition of an external interrupt:�� The interrupt must be held low for at least 2 cycles then high The interrupt must be held low for at least 2 cycles then high
for at least two cycles.for at least two cycles.
Recognition of the interrupt:Recognition of the interrupt:�� The interrupts are latched on the rising edge of CLKOUT1.The interrupts are latched on the rising edge of CLKOUT1.�� The interrupt is finally recognised by the CPU one cycle after The interrupt is finally recognised by the CPU one cycle after
being latched.being latched.
latchedlatched recognizedrecognizedby CPUby CPU
of Interruptof Interrupt
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(6) Interrupt Flag Register (IFR)(6) Interrupt Flag Register (IFR)
�� When an interrupt is recognised the When an interrupt is recognised the corresponding bit in the IFR is set:corresponding bit in the IFR is set:�� e.g. if INT7 is recognised then IFR[7] bit is e.g. if INT7 is recognised then IFR[7] bit is
set.set.
IERIER CSRCSRGIEGIEIFRIFR
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004Chapter 10, Slide 28
GIEGIE
‘C6000‘C6000
CPUCPU
RESETRESET
GIEGIE
00
00
INT7INT7 00
INT15INT15
INT7INT7 11
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(7) CPU Interrupt Hardware Sequence(7) CPU Interrupt Hardware SequenceWhat does the CPU do when an interrupt is recognised?What does the CPU do when an interrupt is recognised?
CPU ActionCPU Action DescriptionDescription
0 0 →→→→→→→→ IFR (bit)IFR (bit) Clears corresponding interrupt flag bitClears corresponding interrupt flag bit
GIE GIE →→→→→→→→ PGIEPGIE Save previous value of GIESave previous value of GIE
0 0 →→→→→→→→ GIEGIE Disables global interruptsDisables global interrupts
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004Chapter 10, Slide 29
0 0 →→→→→→→→ GIEGIE Disables global interruptsDisables global interrupts
Save next EP addressSave next EP address Save return address in IRP/NRPSave return address in IRP/NRP
Vector (ISTP) Vector (ISTP) →→→→→→→→ PCPC Loads PC with interrupt vector addrLoads PC with interrupt vector addr
1 1 →→→→→→→→ IACK pinIACK pin IACK is assertedIACK is asserted
INUM(0INUM(0--3)3) INUM pins display corresponding intINUM pins display corresponding int
IACK and INUM pins are only available on the C620x and C670x.IACK and INUM pins are only available on the C620x and C670x.
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(7) CPU Interrupt Hardware Sequence(7) CPU Interrupt Hardware Sequence
e.g. if INT7 is recognised and IER[7] is set:e.g. if INT7 is recognised and IER[7] is set:
00
77 003131
IFRIFR 11
00
11 003131
CSRCSR 11 1100
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004Chapter 10, Slide 30
xxxx xxxxxxxx xxxx
0x0000 20000x0000 2000
003131
PCPC 0x0800 00000x0800 0000INT7 INT7 --> 0x0800000 ADD A0, A1, A2> 0x0800000 ADD A0, A1, A2
0x0800004 MPY A2, A6, A70x0800004 MPY A2, A6, A7
0x0000 20040x0000 2004
003131
IRPIRP
'C6x'C6x
IACKIACK
INUM3INUM3
INUM2INUM2
INUM1INUM1
INUM0INUM0
11
00
11
11
11
IACK and INUM pins are IACK and INUM pins are only available on the C620x only available on the C620x and C670x.and C670x.
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(8) Writing the ISR in C(8) Writing the ISR in C
There are two methods of declaring an ISR:There are two methods of declaring an ISR:(1)(1) Traditional method:Traditional method:
interrupt void ISR_name (void);interrupt void ISR_name (void);
main (void)main (void){{......
Notes:Notes:�� You need to use the interrupt You need to use the interrupt
keyword in order to inform keyword in order to inform
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004Chapter 10, Slide 31
}}interrupt void ISR_name (void)interrupt void ISR_name (void){{......
}}
keyword in order to inform keyword in order to inform the compiler that it is an ISR the compiler that it is an ISR and therefore to handle the and therefore to handle the necessary register necessary register preservation and use the IRP preservation and use the IRP for returning from the for returning from the interrupt.interrupt.
�� No arguments can be passed No arguments can be passed to the ISR.to the ISR.
�� No argument can be returned.No argument can be returned.
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(8) Writing the ISR in C(8) Writing the ISR in C
(2) Using the dispatcher in DSP/BIOS:(2) Using the dispatcher in DSP/BIOS:Notes:Notes:�� You do not need to use You do not need to use
the interrupt keyword.the interrupt keyword.�� Interrupt nesting of Interrupt nesting of
interrupt functions interrupt functions written in “C” is written in “C” is
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004Chapter 10, Slide 32
interrupt functions interrupt functions written in “C” is written in “C” is allowed.allowed.
�� You can pass one You can pass one argument.argument.
�� You can specify which You can specify which interrupts can be interrupts can be nested by specifying a nested by specifying a mask.mask.
Insert figureInsert figure
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(8) Writing the ISR in Assembly(8) Writing the ISR in Assembly
�� For maskable interrupts the return from For maskable interrupts the return from interrupt address is always stored in the interrupt address is always stored in the Interrupt Return Pointer (IRP).Interrupt Return Pointer (IRP).
�� For nonFor non--maskable interrupts the address is maskable interrupts the address is stored in the Nonstored in the Non--maskable Return Pointer maskable Return Pointer (NRP).(NRP).
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004Chapter 10, Slide 33
(NRP).(NRP).
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(8) Writing the ISR in Assembly(8) Writing the ISR in Assembly_isr_function_isr_function
stwstw......
ldhldh......
(1) Save any registers used by the ISR on the stack(1) Save any registers used by the ISR on the stack(2) Use the HWI macros, or(2) Use the HWI macros, or(3) Use the hardware interrupt dispatcher(3) Use the hardware interrupt dispatcher
Put you ISR code herePut you ISR code here
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004Chapter 10, Slide 34
ldwldw......
b irpb irpnop 5nop 5
(1) Restore the registers saved on the stack(1) Restore the registers saved on the stack(2) Use the HWI macros, or(2) Use the HWI macros, or(3) Use the HWI dispatcher(3) Use the HWI dispatcher
ReturnReturn(You can also use HWI macros)(You can also use HWI macros)
It is much simpler to use the HWI dispatcher rather than doing It is much simpler to use the HWI dispatcher rather than doing the save and restore of registers by yourself or the HWI_enter the save and restore of registers by yourself or the HWI_enter and HWI_exit macros.and HWI_exit macros.
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Other Related TopicsOther Related Topics
(1)(1) Setting and clearing the Interrupt Flag Setting and clearing the Interrupt Flag Register (IFR):Register (IFR):
�� Why do you need to read or write to the Why do you need to read or write to the IFR?IFR?�� By writing you can simulate an interrupt.By writing you can simulate an interrupt.
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004Chapter 10, Slide 35
�� By reading you can check (poll) if an By reading you can check (poll) if an interrupt has occurred.interrupt has occurred.
�� You cannot directly write to the IFR:You cannot directly write to the IFR:�� To set a bit you have to write to the Interrupt To set a bit you have to write to the Interrupt
Set Register (ISR).Set Register (ISR).�� To clear a bit you have to write to Interrupt To clear a bit you have to write to Interrupt
Clear Register (ICR).Clear Register (ICR).
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Other Related TopicsOther Related Topics
�� Example: Set and clear bits 7 and 8.Example: Set and clear bits 7 and 8.
11
77 003131
A0A0MVKLMVKL 0x0180, A00x0180, A0
MVCMVC A0, ISRA0, ISR11
88
11
77 003131
ISRISR 11
88
77 003131 88
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004Chapter 10, Slide 36
11
77 003131
IFRIFR 11
88
* One cycle later* One cycle later
11
77 003131
A0A0MVKLMVKL 0x0180, A00x0180, A0
MVCMVC A0, ICRA0, ICR11
88
11
77 003131
ICRICR 11
88
00
77 003131
IFRIFR 00
88
* One cycle later* One cycle later
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Other Related TopicsOther Related Topics
(2)(2) Setting the polarity of the External Setting the polarity of the External Interrupts:Interrupts:
�� The External Interrupt Polarity (EXTPOL) The External Interrupt Polarity (EXTPOL) register allows the polarity of the external register allows the polarity of the external interrupt pins to be changed.interrupt pins to be changed.This prevents extra hardware (space and This prevents extra hardware (space and
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004Chapter 10, Slide 37
�� This prevents extra hardware (space and This prevents extra hardware (space and cost) being required if the source has a cost) being required if the source has a different polarity.different polarity.
0x19C0008 0x19C0008 �������� EXTPOLEXTPOL XIP7XIP7
33 003131
XIP6XIP6 XIP5XIP5 XIP4XIP4
22 11
0 = low to high (default)0 = low to high (default)
1 = high to low (inverted)1 = high to low (inverted)
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Other Related TopicsOther Related Topics
There are 3 ways of programming the EXTPOL:There are 3 ways of programming the EXTPOL:
�� Method 1: Using “C” code.Method 1: Using “C” code.* (unsigned volatile int*) _IRQ_EXTPOL_ADDR = 2;* (unsigned volatile int*) _IRQ_EXTPOL_ADDR = 2;
�� Method 2: Using assembly.Method 2: Using assembly.
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004Chapter 10, Slide 38
MVKLMVKL 2, A12, A1
MVKLMVKL 0x19c0008, A00x19c0008, A0
MVKHMVKH 0x19c0008, A00x19c0008, A0
STWSTW A1, *A0A1, *A0
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Other Related TopicsOther Related Topics
There are 3 ways of programming the XIP:There are 3 ways of programming the XIP:�� Method 3: Using the GUI configuration Method 3: Using the GUI configuration
tool.tool.
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004Chapter 10, Slide 39
Note: The XIP only affects interrupts to the Note: The XIP only affects interrupts to the CPU and has no effect on the EDMA CPU and has no effect on the EDMA events.events.
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Programming Interrupt ExamplesProgramming Interrupt Examples
�� Interrupts are programmed in the code in Interrupts are programmed in the code in the following chapters:the following chapters:�� \\CodeCode\\Chapter 14 Chapter 14 -- Finite Impulse Response FiltersFinite Impulse Response Filters�� \\CodeCode\\Chapter 15 Chapter 15 -- Infinite Impulse Response FiltersInfinite Impulse Response Filters�� \\CodeCode\\Chapter 16 Chapter 16 -- Adaptive FiltersAdaptive Filters�� \\CodeCode\\Chapter 17 Chapter 17 -- Goertzel AlgorithmGoertzel Algorithm
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004Chapter 10, Slide 40
�� \\CodeCode\\Chapter 17 Chapter 17 -- Goertzel AlgorithmGoertzel Algorithm�� \\CodeCode\\Chapter 18 Chapter 18 -- Discrete Cosine TransformDiscrete Cosine Transform�� \\CodeCode\\Chapter 19 Chapter 19 -- Fast Fourier TransformFast Fourier Transform
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Chapter 10 Chapter 10 InterruptsInterrupts
-- End End --
Single and Multiple Assignment
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Single and Multiple AssignmentSingle and Multiple Assignment�� Single assignmentSingle assignmentrequires that no registers are requires that no registers are
read which have pending results. read which have pending results. �� Multiple assignmentMultiple assignmentallows multiple values to allows multiple values to
rere--useuse the same register in different time slots the same register in different time slots (sort of register based“TDM”) (sort of register based“TDM”) -- thus reducing thus reducing register pressure.register pressure.
Single AssignmentSingle Assignment::
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004Chapter 10, Slide 42
Single AssignmentSingle Assignment::MVKH .S1 0x02,A1
SA: B .S1 SASA: B .S1 SALDW .D1 *A0,LDW .D1 *A0,A1A1NOP 4NOP 4MPY .M1 MPY .M1 A1A1,A2,A3,A2,A3NOP NOP SHR .S1 A3,15,A3SHR .S1 A3,15,A3ADD .L1 A3,A4,A4ADD .L1 A3,A4,A4
Reads current valueReads current value ---- var(n)var(n)
Uses current value Uses current value ---- var(n)var(n)
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Single and Multiple AssignmentSingle and Multiple Assignment�� Single assignmentSingle assignmentrequires that no registers are requires that no registers are
read which have pending results. read which have pending results. �� Multiple assignmentMultiple assignmentallows multiple values to allows multiple values to
rere--useuse the same register in different time slots the same register in different time slots (sort of register based“TDM”) (sort of register based“TDM”) -- thus reducing thus reducing register pressure.register pressure.
Multiple AssignmentMultiple Assignment::
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004Chapter 10, Slide 43
Multiple AssignmentMultiple Assignment::MVKH .S1 0x02,A1
MA: B .S1 MAMA: B .S1 MALDW .D1 *A0,LDW .D1 *A0,A1A1MPY .M1 MPY .M1 A1A1,A2,A3,A2,A3NOP NOP SHR .S1 A3,15,A3SHR .S1 A3,15,A3ADD .L1 A3,A4,A4ADD .L1 A3,A4,A4
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Single and Multiple AssignmentSingle and Multiple Assignment�� Single assignmentSingle assignmentrequires that no registers are requires that no registers are
read which have pending results. read which have pending results. �� Multiple assignmentMultiple assignmentallows multiple values to allows multiple values to
rere--useuse the same register in different time slots the same register in different time slots (sort of register based“TDM”) (sort of register based“TDM”) -- thus reducing thus reducing register pressure.register pressure.
Single AssignmentSingle Assignment:: Multiple AssignmentMultiple Assignment::
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004Chapter 10, Slide 44
Single AssignmentSingle Assignment::MVKH .S1 0x02,A1
SA: B .S1 SASA: B .S1 SALDW .D1 *A0,LDW .D1 *A0,A1A1NOP 4NOP 4MPY .M1 MPY .M1 A1A1,A2,A3,A2,A3NOP NOP SHR .S1 A3,15,A3SHR .S1 A3,15,A3ADD .L1 A3,A4,A4ADD .L1 A3,A4,A4
Multiple AssignmentMultiple Assignment::MVKH .S1 0x02,A1
MA: B .S1 MAMA: B .S1 MALDW .D1 *A0,LDW .D1 *A0,A1A1MPY .M1 MPY .M1 A1A1,A2,A3,A2,A3NOP NOP SHR .S1 A3,15,A3SHR .S1 A3,15,A3ADD .L1 A3,A4,A4ADD .L1 A3,A4,A4
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Problem with Multiple AssignmentProblem with Multiple Assignment
Multiple AssignmentMultiple Assignment::MVKH .S1 0x02,A1
MA: B .S1 MAMA: B .S1 MALDW .D1 *A0,LDW .D1 *A0,A1A1MPY .M1 MPY .M1 A1A1,A2,A3,A2,A3NOP NOP SHR .S1 A3,15,A3SHR .S1 A3,15,A3ADD .L1 A3,A4,A4ADD .L1 A3,A4,A4
Interrupt occurs hereInterrupt occurs here
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004Chapter 10, Slide 45
ADD .L1 A3,A4,A4ADD .L1 A3,A4,A4
�� If an interrupt occurs at the LDW, this instruction will b e If an interrupt occurs at the LDW, this instruction will b e completed before the MPY is executed. completed before the MPY is executed.
�� Therefore A1 will be loaded by the value pointed by A0 Therefore A1 will be loaded by the value pointed by A0 which will be used by the MPY instruction. which will be used by the MPY instruction.
�� The result is that A1 will NOT be equal to 0x02 as intended.The result is that A1 will NOT be equal to 0x02 as intended.
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Chapter 10 Chapter 10 InterruptsInterrupts
-- End End --