Chapter 1: Further Sequential Logic Systems Synchronous ...

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GCE A level Electronics – Chapter 1: Further Sequential Logic Systems

Chapter 1: Further Sequential Logic Systems

Synchronous counters

Learning Objectives:

At the end of this topic you will be able to:• draw a block diagram showing how D-type flip-flops can be connected to form a

synchronous counter to meet a given specification• draw the state diagram for a synchronous counter given a system specification• explain the significance and cause of stuck states, and describe how they can be avoided

by directing unused states back into the main sequence• manipulate unused (don’t care) states to produce simpler solutions• explain how simultaneous clocking of D-type flip-flops overcomes the limitation of ripple

counters at high counting speed• analyse and design a synchronous counter (up to 3 bits) to obtain the state diagram for the

sequence it produces.

Synchronous counters based on D-type flip-flops differ from ripple counters and dedicated synchronous counter ICs in that:

• they can produce any sequence of output signals (and so are also known as sequence generators), whereas ripple counters can count only up or down in binary

• the clock inputs of all stages of the counter are connected together and so receive clock pulses at exactly the same time (which is why they are called synchronous)

• logic gates generate appropriate signals at the data inputs of each stage.

In ripple counters, the clock signals move through the system, stage by stage, and so it takes time for the last stage to react to a pulse received at the first stage. This causes inaccuracy when the counter is counting at high speed. There is no such problem with the synchronous counter, because all stages receive the clock signal at the same time and so react at the same time.

The following diagram shows a basic 3-bit synchronous counter, constructed from D-type flip-flops:

(The set and reset inputs of the D-types have been omitted to improve the clarity of the diagram.)



Designing a synchronous counter:

The first step is to formalise the required sequence of output states into either:

• a table showing how one set of outputs creates the next input states• a state diagram, or equivalent, showing the progression of output states as a visual representation

of the sequence or

• Boolean expressions, showing the relationships between output and input states in the form of Boolean equations.

These are all different versions of the same information.

Example 1 – A 3-bit up-counter

A synchronous counter can be designed as a ‘normal’ binary up-counter.

It progresses through the sequence shown in the following table:

Step 1:Expand the table to incorporate the inputs needed to create the sequence.

Pulse number

Outputs C (m.s.b.) B A (l.s.b.)

0 0 0 0 1 0 0 1 2 0 1 0 3 0 1 1 4 1 0 0 5 1 0 1 6 1 1 0 7 1 1 1 8 0 0 0 9 0 0 1

etc.

Pulse number

Outputs Inputs generated C (m.s.b.) B A (l.s.b.) DC DB DA

0 0 0 0 0 0 1 1 0 0 1 0 1 0 2 0 1 0 0 1 1 3 0 1 1 1 0 0 4 1 0 0 1 0 1 5 1 0 1 1 1 0 6 1 1 0 1 1 1 7 1 1 1 0 0 0



This means that we need a logic system, attached to the data input DC of the first flip-flop, which:

• uses the signals C = 0, B = 0 and A = 0 to generate an output of logic 0• uses C = 0, B = 0, A = 1 to generate logic 0 again• and so on ...

Inputs DB and DA need their own logic systems to carry out similar tasks.

In this example, it is easiest to start with the DA signal. Compare the DA column and the ‘A’ output column in the table.We do not need much of a logic system. DA is always the opposite of output A.In other words: DA = A

We do not need any logic gates for the DA input, as the third D-type flip-flop has an output, the Q output, which gives us the inverse of output A.

The other two logic systems, for the DB and DC input are more complicated.In general, Karnaugh maps may be needed to sort out the Boolean expressions.

For DB: and so:

DB = B.A + B.A

or, in a single logic gate: DB = B ⊕ A

For DC:

and so the best we get from this map is: DC = C.B + C.B.A + C.B.A

Taking a factor of B from the last two terms gives:

DC = C.B + B.( C.A + C.A)

or: DC = C.B + B.( C ⊕ A )



The circuit diagram for this system is given below.

We can represent the behaviour of this system in a State Diagram:

An important pointWhen the system is powered up, it can start in any of the eight states. However, in this system, no matter where it starts, it then counts up in binary from that point and resets when it reaches 1112. It could be forced to start at 0002 by linking together the Reset inputs of the D-type flip-flops and activating them briefly when the system powers up.

This system is a little unusual in that the required sequence, called the main sequence, includes all possible states. In many cases, some of the possible states are unused. This can cause problems, as shown in the next example.



Example 2 – A LED light chaser The system has three LEDs, A, B and C. Initially, all are turned off. Then, only one LED lights at a time in a sequence that repeats continuously.

Visually, the sequence looks like:

Here is the same specification expressed in the form of a table.

Finally, the same specification shown as a state diagram for the main sequence (but not any unused states).

It assumes that a LED is on when a logic 1 signal is applied, and off when logic 0 is applied.

Unused states:The synchronous counter will drive the three LEDs in the correct sequence. It will have three digital outputs, which means that there are eight (= 23) possible combinations of these outputs. The main sequence uses only four of these – 000, 001, 010 and 100. This means that there are four unused states – 011, 101, 110 and 111.

State number

LEDs C B A

0 Off Off Off 1 Off Off On 2 Off On Off 3 On Off Off



As pointed out earlier, the system can output any of the eight states when it is first switched on. We have to design the counter so that even if, on power-up, it starts in an unused state, it will eventually progress onto the required sequence.

We complete the state diagram by showing how the system will deal with the unused states. One possible solution, but rarely the best, is to link all the unused states to state S0, the 000 state. This is shown in the next diagram:

Suppose that the system starts in an unused state, say state S4, and outputs 011.When the first clock pulse arrives, the system moves to the S0 state, in the main sequence. After that, the next clock pulse moves the system to the S1 state, and after that it continues through, and is locked into, the main sequence.

The full truth table for this solution is:

Notice that the table has two main columns – the current state of the system, and the next state. The headings DC, DB and DA relate to the D-type flip-flops, used to build the synchronous counter.The next task is to determine what logic gates are needed, and with what inputs, to supply the correct signals to the data inputs of the D-types. This is done either by inspection, or by use of Karnaugh maps. In this case, we can do this by inspection.The Boolean expressions linking current inputs and outputs are:

DC = C.B.A

DB = C.B.A

DA = C.B.A

State number

Current state of LEDs Next state of LEDs C B A DC DB DA

Main sequence

0 0 0 0 0 0 1 1 0 0 1 0 1 0 2 0 1 0 1 0 0 3 1 0 0 0 0 0

Unused states

4 0 1 1 0 0 0 5 1 0 1 0 0 0 6 1 1 0 0 0 0 7 1 1 1 0 0 0



The circuit diagram for this system is given below:

The drawback of connecting all unused states to the 000 state is that usually the solution leads to Boolean expressions and logic systems that are more complicated.

While the expressions above are not excessively complicated, the design can be simplified by linking the unused states in a different way (they are unused, so we can do what we like with them as long as they lead into the main sequence). We consider how this can be done later on.

Stuck states:Stuck states are unused states that do not progress into the main sequence.

Careless design of a system can lead to a situation where, on power-up, the system locks in an unused state, and never progresses to the main sequence.The next state diagram shows the same main sequence that was used earlier but with a different, undesira-ble arrangement of unused states:

Now, when you switch on the system, there is a chance that it starts in either state S4 or S5. If so, as the three D-type clock inputs receive pulses, the outputs simply alternate between the 011 and 101 states. They never reach the main sequence. These are known as stuck states.

Remember, these are only a problem on power-up.Provided that the system reaches the main sequence, it continues to cycle around it.



Exercise 1.1

1. Three LEDs are switched on and off in the following sequence:

Draw a state diagram for this system, taking care to avoid stuck states.

2. Here is the state diagram for a synchronous counter.

Complete the table for this counter:

State number

Current state Next state C B A DC DB DA

0 0 0 1 1 2 3 4 5 6 7



Manipulating unused (don’t care) states

Example 1: Process control

In an industrial plant, a liquid is added to a drum and then stirred. After sufficient time, the drum is emptied. The sequence of operations is:

• a pump is switched on to fill a drum• when partly full, a motor rotates it to stir the contents• when full, the pump is switched off• the motor continues to stir for a short time• the motor is then turned off• a valve opens to empty the drum• all devices are switched off and the sequence is repeated.

We can use a synchronous counter to control these devices, providing all the steps last for the same amount of time (which will be the period of the clock signal). Synchronous counters can control a variety of output devices, through suitable interfaces.

To design the counter, first we turn the description of the sequence of events into a truth table for the main sequence. Assume that a logic 1 signal turns a device on and logic 0 turns it off (check that the contents of the table match the description above).

Not all possible combinations are used in the sequence. These unused states are ‘don’t care’ states. They never happen in practice and so it doesn’t matter where they go (as long as they lead into the main sequence).

X = Don’t care

Next, we work what logic gates are needed by looking at the Boolean relationships between outputs and inputs, ignoring the unused states. Once we decide what these relationships are, we use them to determine the fate of the three unused states.

1. Look at the DB column. It is identical to the ‘Pump C’ column. Hence, the relationship: DB = C

2. The DC column has logic 1 entries only in the rows where ‘Motor B’ and ‘Valve A’ are both logic 0. We can specify this relationship as:

DC = B . A3. The DA column has a logic 1 entry only in State 3, which is the only time that ‘Motor B’ = 1 and

‘Pump C’ = 0 in the main sequence. We can specify this relationship as: DA = C . B

State number

Current state Next state Pump C Motor B Valve A DC DB DA

Main Sequence

0 0 0 0 1 0 0 1 1 0 0 1 1 0 2 1 1 0 0 1 0 3 0 1 0 0 0 1 4 0 0 1 0 0 0

Unused States

5 0 1 1 X X X 6 1 0 1 X X X 7 1 1 1 X X X



We obtained these relationships by inspection. It is advisable to check them using Karnaugh maps (we use this approach later, in example 2).

Having the Boolean expressions, we return to the question of the unused states. These Boolean expres-sions apply to both the unused states and the main sequence.

The unused states are: 011, 101 and 111.

Applying the Boolean expressions obtained earlier to these gives:

Be clear about what we have just doneWe first decided on the logic gates needed to produce the main sequence.We then looked at what these gates will do when the system powers up into an unused state.It is vital that these lead into the main sequence i.e. that they are not stuck states.

Including the results for the unused states, the full truth table for the control system is:

The state diagram for this system will identify whether there are any stuck states:

State number


5 0 1 1 0 0 1

State number


6 1 0 1 0 1 0

State number


7 1 1 1 0 1 0

State number


0 0 0 0 1 0 0 1 1 0 0 1 1 0 2 1 1 0 0 1 0 3 0 1 0 0 0 1 4 0 0 1 0 0 0 5 0 1 1 0 0 1 6 1 0 1 0 1 0 7 1 1 1 0 1 0



As you can see, all unused states lead into the main sequence. If the control system powered up in an unused state, it would progress onto the main sequence in the next clock cycle.

However, it does mean that the main sequence can start at any point. In practice, this may be a problem. Where it is important that the sequence always starts in the 000 state, the reset pins of the D-types can be linked to a ‘Start Process’ switch.

The circuit diagram for the solution developed above is:

Example 2:

Another industrial process uses three devices connected to outputs C, B and A of a synchronous counter. The sequence of operations defined in the following table:

There are three unused states, leading to ‘don’t care’ states, marked with an X.

State number


0 0 0 1 0 1 1 1 0 1 1 1 1 0 2 1 1 0 1 1 1 3 1 1 1 1 0 1 4 1 0 1 0 0 1

5 0 0 0 X X X

6 1 0 0 X X X

7 0 1 0 X X X



Here is the Karnaugh map for DC:

Notice that three of the boxes contain ‘don’t care’ states, shown by ‘X’. We can choose to make these either logic 0 or logic 1, in order to make the Boolean algebra and the electronics easier to implement. In this case we will make the ‘don’t care’ state in the top right hand corner into a 1 and make the other two ‘don’t cares’ into 0’s.The map becomes:

giving the relationship: DC = B

In the same way, the Karnaugh map for DB is:

Here, we have converted all the ‘don’t care’ states into logic 1’s to give:

DB = C + A

Finally, here is the Karnaugh map for DA:

In this case we have converted the ‘don’t care’ state in the top right hand corner into logic 0 and the other two into logic 1 to give:

DA = C + B



Then, we apply the Boolean expressions for DA, DB and DC to find the corresponding ‘Next state’ values and check that there are no stuck states.

Now complete the example by drawing the state diagram and circuit diagram for this system:

State diagram

Circuit diagram

When it is important that the sequence starts in a particular state, the ‘Set’ pins of the D-types can be linked to a ‘Start Process’ switch.

For example, to start in state 0 (0,0,1) the ‘Start Process’ switch would trigger the ‘Set’ inputon D-type flip-flop A momentarily.

State number

Current state Next state

C B A DC DB DA 5 0 0 0 0 1 1 6 1 0 0 0 1 1 7 0 1 0 1 1 0



Which method do I use?

Although the first method is more direct, it requires you to spot a Boolean expression from a column of 0’s and 1’s.

The second method takes longer but has a more visual approach.

Choose whichever method works for you.

Example 3: LED light chaser

We return to the first of the LED light chasers, on page 6, to redesign the solution. This time, we make better use of unused states in order to produce a simpler solution.

In the following truth table, the unused, or ‘don’t care’, states are marked with an X.

Karnaugh maps enable us to sort out the Boolean algebra.

Here is the map for DC, showing the ‘don’t care’ states:

State number

Current state of LEDs Next state of LEDs C B A DC DB DA

Main sequence

0 0 0 0 0 0 1 1 0 0 1 0 1 0 2 0 1 0 1 0 0 3 1 0 0 0 0 0

Unused states

4 0 1 1 X X X 5 1 0 1 X X X 6 1 1 0 X X X 7 1 1 1 X X X



We can convert the ‘X’s into 0’s and 1’s to give us a simple solution:

giving the relationship: DC = BFor DB, choosing a different value for the ‘don’t care’ states: gives the relationship: DB = A

Finally, for DA:

Hence DA = C.B.A (or C+B+A);Notice the two options for DA.The second is probably easier to generate. However, either solution is acceptable.The Boolean relationships between inputs and outputs are then:

DC = B

DB = A

DA = C+B+A

These are then the expressions produced earlier, when all unused states were connected directly to S0.The truth table is now:

State Current state of LEDs Next state of LEDs C B A DC DB DA

Main sequence

0 0 0 0 0 0 1 1 0 0 1 0 1 0 2 0 1 0 1 0 0 3 1 0 0 0 0 0

Unused states

4 0 1 1 1 1 0 5 1 0 1 0 1 0 6 1 1 0 1 0 0 7 1 1 1 1 1 0



The resulting state diagram is:

and the circuit diagram:



Investigation 1.1

Set up the following synchronous counter on Circuit Wizard using three CMOS 4013 D-types. Outputs A, B and C are connected to logic indicators.

At the start of the simulation, all three logic indicators should be green (logic 0).(a) Press the clock switch SW1 several times and record your result in the truth table below.

(b) Compare the sequence with that obtained in example 1 on page 9.

(c) Momentarily press the set switch SW2 and comment on what you observe.

(d) Momentarily press switch SW1 and explain what has happened.

State number


0 0 0 0 1 2 3 4



Exercise 1.2

1. A sequence generator is needed to provide signals for a lighting display control system.

The next table gives the main sequence of signals C, B and A.

States 5, 6 and 7 are unused. The states they progress into have been chosen to simplify the system.

(a) Complete the first table to show the inputs DC, DB and DA needed to generate the sequence.

(b) Determine Boolean expressions for DC, DB and DA in terms of outputs C, B and A (simplify the expressions as much as possible, using the rules of Boolean algebra or Karnaugh maps).

DC =

DB =

DA =

(c) Complete the circuit diagram for this system by adding:

• correct clock connections,• appropriate logic gates correctly connected.

State number


0 0 0 0 1 1 1 1 2 0 1 0 3 1 0 1 4 0 1 1

State number C B A DC DB DA

5 0 0 1 0 1 1 6 1 0 0 1 1 1 7 1 1 0 1 1 1



2. Design a synchronous counter that will produce the following ‘light chaser’ effect:

Your design should include:• a truth table and state diagram showing both the main sequence and the unused states;• the circuit diagram.

It should manipulate the unused states to produce the simplest solution.

State diagram:

State number


0 1 2 3 4 5 6 7



Circuit diagram:



3. Design a synchronous counter that will count up in binary from 0002 to 1002, and then, on the next clock pulse, reset to 0002. Your design should include:

• a truth table and state diagram showing both the main sequence and the unused states• the circuit diagram.

It should manipulate the unused states to produce the simplest solution.

State diagram:

State number


0 1 2 3 4 5 6 7



Circuit diagram:



Analysing a synchronous counter:

A synchronous counter can be analysed given either:

• the circuit diagram• the state diagram• the Boolean equation for each input.

Example 1:

Find the sequence produced by the following synchronous counter.

Step 1:

Write down Boolean expressions for inputs DC, DB and DA in terms of outputs C, B and A.

In this case:

DC = C.B.A DB = C DA = C + B

Step 2:

Use these relationships to complete the truth table to show the sequence of output states (unless told otherwise, we start at the ‘000’ state, and see what happens).

State number


0 0 0 0 1 0 0 1 1 0 0 0 1 1 2 0 1 1 0 0 1 3 0 0 1 0 0 0

4 0 1 0 0 0 1

5 1 0 1 0 1 1

6 1 1 0 0 1 1

7 1 1 1 0 1 1



In this case, the ‘000’ state was part of the main sequence.

We know when the main sequence comes to an end because it returns to the first state we looked at. Altogether there are four states in the main sequence, and four unused states.

Step 3:

Check whether any of the unused states are stuck states. To do this, use the truth table to create the state diagram.

We can now see that the system functions without any risk of stuck states.

Example 2:

Here is the circuit diagram for a sequence generator.Find the sequence produced.

Step 1: the Boolean expressions.

By inspecting the circuit diagram, these are:

DC = C

DB = B . A

DA = C ⊕ B



Step 2:

Use these relationships to complete the truth table to show the sequence of output states.

The first four states make up a sequence, presumably the main sequence.States 4, 5, 6 and 7 are, we assume, the unused states.

Now use the truth table to draw the state diagram for this system:

Problem

Only one unused state, state 5, leads into the main sequence. If the system powers up in states 4, 6 or 7, it can never progress into the main sequence. These three are stuck states.

This problem can be overcome by redesigning the circuit for the sequence generator:• firstly replace all the next state outputs in the truth table with X’s (don’t cares)• convert the ‘X’s into 0’s and 1’s to give the simplest solution• draw the state diagram to check that the stuck states have been removed• draw the modified circuit diagram.

It is left to you to confirm that:

DC = C DB = A DA = C. B

and there are no stuck states.

State Current state Next state C B A DC DB DA

0 0 0 0 1 0 0 1 1 0 0 0 0 1 2 0 0 1 1 1 0 3 1 1 0 0 0 0 4 0 1 0 1 0 1 5 1 1 1 0 0 0 6 0 1 1 1 0 1 7 1 0 1 0 1 1



Example 3:

A sequence generator is designed to control three electrical pumps in a chemical plant.

The sequence is governed by the following Boolean equations:

DC = A DB = A ⊕ C DA = B.C Step 1:

The circuit diagram for the sequence generator:

Step 2:

Use these relationships to complete the truth table to show the sequence of output states (again, we start at the ‘000’ state, and see what happens).

(i) The table to show the main sequence produced by the sequence generator.

The main sequence (shown in bold) can be deduced by inspection.In this case, state 0 (0,0,0) is not part of the main sequence. States 6 and 7 are also unused but need to be checked to see which states they lead into. The unused states are shown highlighted in green.

State Current state Next state C B A DC DB DA

0 0 0 0 1 0 0 1 1 0 0 1 1 0 2 1 1 0 1 1 1 3 1 1 1 0 0 1 4 0 0 1 0 1 0 5 0 1 0 1 0 0 6 0 1 1 0 1 0 7 1 0 1 0 0 0



Step 3:

Use the truth table to create the state diagram. A complication – in this case, the used and unused states are not separate.

The state diagram shows that there are no stuck states.



Exercise 1.3

1. Analyse the sequence produced by the following synchronous counter by:

• obtaining the Boolean expressions linking the inputs and outputs• completing the truth table• drawing the state diagram, including the unused states.

(a) Obtain the Boolean expressions linking the inputs and outputs;

DC = DB = DA =

(b) Complete the truth table (hint – there are four states in the main sequence).

State number


0 1 0 0 1 2 3 4 5 6 7



(c) Draw the state diagram, including the unused states.

2. A sequence generator is governed by the following Boolean equations: DA = A

DB = B ⊕ A

DC = B ⊕ A

(a) Complete the circuit diagram for this sequence generator by adding:

• correct clock connections for the three D-type flip-flops• logic gates to provide the required input signals for the D-type flip-flops.



(b) Complete the truth table to show the main sequence of states. (You should find that it contains only four states.)

(c) Identify the four unused states, and for each one, show into which state the unused state will lead.

(d) Hence draw the state diagram for this sequence generator.

State number


0 0 1 0 1 2 3

State number


4 5 6 7



3. (a) Why are synchronous counters more suitable than ripple counters for counting high frequency pulses?

(b) Here is the state diagram for a synchronous counter.

(i) List the states found in the main sequence.

(ii) List all unused states.

(iii) List any stuck states.

(iv) Why is it important to avoid stuck states when designing synchronous counters?



4. The state diagram shows the main sequence of a 3-bit synchronous counter.

There are three unused states, states 5, 6 and 7.

(a) Identify these unused states.

(b) Complete the state diagram by adding these unused states and connecting them so that there are no stuck states.

Unused state

Outputs C B A

5 6 7



5. A student designs a light-chaser effect, based on a synchronous counter, for a model car. Part of the circuit diagram is shown below:

(a) The circuit can be simplified without changing its performance. Explain how to modify the circuit so that the NOT gates are not needed.

……………………………………………………………………………………………..

……………………………………………………………………………………………..

…………………………………………………………………………………………….. (b) Write down Boolean expressions for the inputs DA, DB and DC in terms of the outputs A, B and C.

DA = ……………………………………………….

DB = ……………………………………………….

DC = ……………………………………………….

(c) Use these Boolean expressions to complete the table, showing the main sequence of output states that this system will generate and the unused states.

You should find there are only three states in the main sequence.

State number


0 0 0 0 1 2 3 4 5 6 7



(d) Hence draw the state diagram for this system.

(e) There is a serious defect with the design of this sequence generator.

(i) Explain what this defect is, and why it might cause a problem.

(ii) Redraw the state diagram showing how to overcome this defect, without changing the main sequence.

Chapter 1: Further Sequential Logic Systems Synchronous ...

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