Chapter 1

DESIGNING OF SUBTHRESHOLD VOLTAGE HIGH-K CMOS DEVICES AT THE MINIMUM ENERGY POINT

Chapter 1

INTRODUCTION

1.1 Brief description of the projectGordon Moore, co-founder of Intel, famously stated in 1965 “The amount of

transistors which can be inexpensively placed on an integrated circuit doubles every 18

months." This statement has been dubbed as Moore's law and scaling down of transistors

has been the trend of the industry ever since [1]. We have come a long way since 1971

when the semiconductor manufacturing process was 10µm, now we are adopting 32nm

technology and research is being done to implement 22nm technology and beyond.

Evolving nanometer CMOS technologies provide better functionality, higher performance

and greater levels of integration but suffer from increased subthreshold leakage and

excessive process variation. With the industry and market emphasizing on "performance

per watt" and "performance per joule", there is a growing need for new power and energy

saving techniques for the increased power and energy dissipation caused due to scaling

down of transistors.

The total power (Ptotal) dissipated in a CMOS logic gate consists of static power

(Pstatic) and dynamic power (Pdynamic). While the scaling down of transistors causes a

reduction in dynamic energy per cycle due to reduced capacitances in the circuit, there is

an increase in leakage current of the circuit due to scaling down of the threshold voltage

causing a significant increase in the static power dissipation. The speed of digital circuits

is currently limited by the energy density. Shrinking feature sizes will continue to have

the advantage of higher degree of integration, resulting in lower cost, provided energy

density can be kept in control.

The supply voltage has the strongest influence on all components of power and

energy of a digital CMOS circuit. In 1971, Meindl and Swanson concluded that to obtain

the greatest power saving and the least power-speed product, the circuit must be operated

at the lowest supply voltage practically possible by the design technology [2].

Dept of E & C, NCET, Bengaluru 2012


Another approach has been to examine the energy minimization for circuits

operating in the subthreshold region. Studies have shown subthreshold operations have a

number of advantages, namely, improved gain, noise margin, and greater energy

efficiency at lower frequencies than the standard CMOS. The authors in [3] further

examine solutions for optimum supply voltage (Vdd) and threshold voltage (Vth) to

minimize energy in subthreshold operations of digital circuits. It is shown that there is a

maximum achievable frequency for a given circuit operating in the subthreshold region.

They conclude that the current standard cell libraries also show reduced energy per

operation for a minimum sized device. Dual voltage design in the subthreshold voltage

range has recently been studied and shown to have energy and speed advantages [4-5].

Similarly, subthreshold voltage operation may have advantage in extending the battery

lifetime in portable and mobile electronics [6].

This proposed work examines the 250nm bulk and high-k metal gate technologies.

Aggressive voltage scaling techniques described in previous research [3, 7, 8] was used to

evaluate how a chosen circuit's (32-bit ripple carry adder) power and energy consumption

varies with a change in Vdd. After obtaining the optimum Vdd at which the minimum

energy per cycle occurs, the results were compared for both processes. The performance

of a 32-bit ripple-carry adder circuit was evaluated for the entire range of Vdd over which

it displays a correct functionality. Lowering voltage increases delay, reducing the

maximum clock frequency. The maximum permissible clock rate and the energy per

cycle at that clock rate as two performance criteria.

The same 32-bit ripple carry adder circuit was designed in both 250nm bulk and

high-k technologies in order to compare which technology is better suited for a low power

and higher energy efficient design. The minimum energy per cycle operation occurs at a

subthreshold voltage for both designs. For minimum energy, the bulk technology has a

low performance. However, high-k technology works at a much higher clock. Faster

clock rate reduces the leakage energy making high-k almost twice as energy efficient

compared to bulk.

The increasing attention on power consumption in circuit design has motivated a

significant investigation of the optimum design for minimizing energy or power for a



given performance constraint. Almost all of these efforts have targeted high performance

strong inversion operation.

Emerging applications such as distributed sensor networks or medical applications

have low energy as the primary concern instead of performance, with the eventual goal of

harvesting energy from the environment. Subthreshold operation is ideal for this class of

applications because it allows minimum energy operation for low performance situations.

Developing subthreshold energy model is necessary for determining the optimum Vdd for

a fixed Vth when minimizing energy is the primary concern. The subthreshold energy

model shows the dependence of the minimum energy point on design characteristics and

operating conditions. It also provides an analytical solution for and to minimize energy

for a given frequency in the subthreshold region.

1.2 Advantages and disadvantages of CMOS technology1.2.1 Advantages of CMOS technology

One of the main advantages of CMOS technology, which makes it the most

commonly used technology for digital circuits today, is the fact that it enables

chips that are small in size to have features like high operating speeds and

efficient usage of energy. Besides, they have very low static power supply

drain most of the time.

Only when the transistors are switching between the two states (ON and OFF)

We find a significant level of power drain. Besides, devices using CMOS

Technology also has a high degree of noise immunity.

Two important characteristics of CMOS devices are high noise immunity

and low static power consumption.

1.2.2 Disadvantages of CMOS technology

CMOS devices often lack the current drive capability of BJT’s.

Noise can also be a drawback of CMOS in linear ICs.

CMOS has an advantage in its low level of shot noise, but its 1/F noise is

larger.

The final disadvantage is speed performance and ultra precision for certain

applications.



1.3 Objectives of the project There is a growing concern for increased power and energy dissipation with the

scaling down of transistors. The total power (Ptotal) dissipated in a CMOS logic gate

consists of static power (Pstatic) and dynamic power (Pdynamic).

While the scaling down of transistors causes a reduction in dynamic energy per

cycle due to reduced capacitances in the circuit, there is an increase in leakage current of

the circuit due to scaling down of the Vth causing a significant increase in the static power

dissipation. The speed of digital circuits is currently limited by the energy density.

Shrinking feature sizes will continue to have the advantage of higher degree of

integration, resulting in lower cost, provided energy density can be kept in control.

Another approach has been to examine the energy minimization for circuits

operating in the subthreshold region. Studies have shown subthreshold operations have a

number of advantages, namely, improved gain, noise margin, and greater energy

efficiency at lower frequencies than the standard CMOS technology.

1.4 Problem formulation We have implemented 32 bit ripple carry adder using tool Tanner EDA in 250nm

technology for bulk and high-k technologies. To design 32 bit ripple carry adder, first we

need to design full adder. Full adder can be designed by using INV, NAND, NOR and

XOR circuits. By using four full adders, 4 bit ripple carry adder can be designed. By

using four 4-bit ripple carry adder, 16-bit ripple carry adder can be designed. By using

two 16-bit ripple carry adders, 32-bit ripple carry adder can be designed. In order to find

the minimum energy per cycle, delay and power needs to be calculated.

It was bit challenging to calculate critical path delay. At each voltage step, there is

a change in path delay as well as drawn current. In other words, when voltage is

decreased, there is a decrease in drawn current but an increase in critical path delay.

Hence, to find the minimum energy dissipated by the circuit, the delay and current at each

voltage step needs to be measured.



To calculate the delay at each voltage, the critical path needs to be activated.

Therefore, the following vectors were applied. First, all the inputs (A, B, and Cin) were

initialized to 0. This sets all the sum outputs and the carryout to value 0. In the second

vector, all A inputs (A [0:32]) were set to 1, while keeping all B inputs (B [0:32]) to 0.

All sum outputs thus became 1, but there was no change in the carry signal and there was

no rippling of bits through the carry signals. A third vector then set at C in at 1 to activate

the critical path. As a carry was propagated through all 32 full adders, two critical paths

were simultaneously activated. While the carry bits in all the 32 full adders changed to 1,

sum outputs were simultaneously brought back to 0. The largest time delay out of two

path delays is deemed the critical path delay.

1.5 Proposed system The present work examines the 250nm bulk and high-k technologies. We evaluate

the performance of a 32-bit ripple carry adder circuit for the entire range of supply

voltages over which it displays correct function. Lowering voltage increases delay,

reducing the maximum clock cycle rate. We use the maximum permissible clock rate and

the energy per cycle at that clock rate as two performance criteria. The minimum energy

per cycle operation occurs at the same supply voltage for both bulk and high-k

technologies. For minimum energy, the bulk technology has a very low performance.

However, high-k technology works at a much higher clock. Faster clock rate reduces the

leakage energy making high-k almost twice as energy efficient compared to bulk.

1.6 Methodology1.6.1 High-k CMOS technology

The technology in an Intel chip enabled the fabrication of 45nm microprocessors

in 2007. As elements in the chip were being reduced to 45nm, the gate dielectric began to

lose its insulating (dielectric) quality and exhibited too much leakage. The gate dielectric

is a very thin insulation layer, traditionally made of silicon dioxide, which lies between

the transistor's metal gate electrode and the channel through which the current flows.

Intel's solution to the problem was to combine a hafnium based dielectric layer,

instead of silicon dioxide, with a gate electrode composed of alternative metal materials.



The resulting combination yields a "high dielectric constant," otherwise known as a

"high-k.

1.7 Tools required In this section, the hardware and software tools required to develop the proposed

work are mentioned.

Minimum hardware requirement specification:

Intel Pentium III Processor,

256 MB RAM,

20 GB HDD.

LAN card for LAN connection.

Minimum software requirement specification:

Tanned EDA

T-Spice

S-Edit

L-Edit

LVS

1.8 Literature survey To do the project in a phased manner, it is necessary to conduct the literature

survey. An extensive study has been carried out to understand the concepts, policies, and

implementation mechanisms. In this section, selected important contributions from the

existing system literature are discussed.

In 1961: It is argued that computing machines inevitably involve devices which

perform logical functions that do not have a single valued inverse. This logical

irreversibility is associated with physical irreversibility and requires a minimal heat

generation, per machine cycle, typically of the order of kT for each irreversible function.

This dissipation serves the purpose of standardizing signals and making them independent

of their exact logical history. Two simple, but representative, models of bi-stable devices

is subjected to a more detailed analysis of switching kinetics to yield the relationship

between speed and energy dissipation, and to estimate the effects of errors induced by

thermal fluctuations. The information bearing degrees of freedom of a computer interact



with the thermal reservoir represented by the remaining degrees of freedom. This

interaction plays two roles. First of all, it acts as a sink for the energy dissipation involved

in the computation. This energy dissipation has an unavoidable minimum arising from the

fact that the computer performs irreversible operations. Secondly, the interaction acts as a

source of noise causing errors. In particular thermal fluctuations give a supposedly

switched element a small probability of remaining in its initial state, even after the

switching force has been applied for a long time [9].

In 2005: This paper examines energy minimization for circuits operating in the

subthreshold region. Subthreshold operation is emerging as an energy saving approach to

many energy constrained applications where processor speed is less important. In this

paper, the authors solve equations for total energy to provide an analytical solution for the

optimum Vdd and Vth to minimize energy for a given frequency in subthreshold operation.

We show the dependence of the optimum Vdd for a given technology on design

characteristics and operating conditions. This paper also examines the effect of sizing on

energy consumption for subthreshold circuits. They show that minimum sized devices are

theoretically optimal for reducing energy. A fabricated 0.18µm test chip is used to

compare normal sizing and sizing to minimize operational Vdd and to verify the energy

models. Measurements show that existing standard cell libraries offer a good solution for

minimizing energy in subthreshold circuits [3].

In 2005: Dynamic voltage scaling (DVS) has become a standard approach for

reducing power when performance requirements vary. Voltage dithering was proposed to

provide near optimum DVS power savings with much less overhead. Voltage dithering

refers to operating for different fractions of time at two discrete voltage and frequency

pairs to achieve an intermediate average frequency. Previous implementations apply

voltage dithering to entire chips and require many microseconds to change operating

voltage [7].

In 2008: In the near future, a number of systems will be powered using energy

scavenging technologies, enabling exciting new applications such as medical monitoring,

toxic gas sensors and next generation portable video gadgets. Energy harvesters typically

provide output power in the range of 10-100μW, setting a constraint on the average power



that can be consumed by the load circuitry for self powered operation. This will require

the electronic circuits to operate with utmost energy efficiency while performing the

required functionality. Energy minimization requires a system level approach optimizing

not only the signal processing and interface circuits but also the energy processing

function. A major opportunity to reduce the energy consumption of digital circuits is to

scale supply voltages below 0.5V driving them to subthreshold operation [8].

In 2009: For a decade, low power design has been part of mainstream

semiconductor R&D activities, while ultra low power (ULP) design remained dedicated

to niche markets of particular applications such as sensor networks, Radio Frequency

Identification Devices (RFIDs) and biomedical devices, where speed performances are

not critical. However, today’s 65/45nm CMOS technologies offer so compact circuits and

high device performance that they give the opportunity for the designers to trade Silicon

die area for energy efficiency, while maintaining sufficient speed. As a consequence, ultra

low power design is now an emerging solution for energy efficient mainstream

electronics applications both in the consumer and professional markets [10].

In 2011: This paper investigates subthreshold voltage operation of digital circuits.

The minimum energy per cycle operating point with a single voltage for this mode is

known. The authors further lower the energy per cycle below that point by using dual

subthreshold supplies. They call this the true minimum. Special considerations are used in

the design for eliminating level converters. They give new mixed integer linear programs

(MILP) that automatically and optimally assign gate voltages, avoid the use of level

converters, and determine and hold the minimum critical path delay, while minimizing

the total energy per cycle. Using examples of a 16-bit ripple carry adder and a 4 × 4

multiplier they show energy savings of 23% and 5%, respectively. The latter is a worst

case example because most paths are critical [4].

In 2011: This paper presents a method for minimum energy digital CMOS circuit

design using dual subthreshold supply voltages. Stringent energy budget and moderate

speed requirements of some ultra low power systems may not be best satisfied just by

scaling a single supply voltage. Optimized circuits with dual supply voltages provide an

opportunity to resolve these demands. The delay penalty of a traditional level converter is



unacceptably high when the voltages are in the subthreshold range. In the present work

level converters are not used and special multiple logic level gates are used only when,

after accounting for their cost, they offer advantage. Starting from a lowest per cycle

energy design whose single supply voltage is in the subthreshold range, a new MILP

finds a second lower supply voltage optimally assigned to gates with time slack [5].

In 2011: This paper examines the energy consumption of a digital circuit with

voltage scaling and observes its impact on the energy efficiency of the battery. Further

study of the system with a power source under throughput constraints and the authors

propose a method to find a right size of battery to satisfy given system requirements. For

systems with limit on battery weight or volume, they suggest a right circuit voltage

operating point. Maximizing battery lifetime, expressed in terms of clock cycles, depends

upon a proper choice of the supply voltage and the corresponding clock frequency that the

circuit would support. Analysis of various batteries shows that when no system

performance requirement is specified, the optimum operating supply voltage can be in the

subthreshold range [6].

1.9 Organization of the project report In this section, a brief preview of the organization of this project report is given.

The project report is divided into 7 chapters as mentioned below.

In chapter 1, Introduction, objectives, and proposed systems, methodology, hardware and

software tools required in the project, literature survey and organization profile have been

discussed. The remaining chapters are organized as follows.

Chapter 2 provides study of subthreshold circuits. It includes subthreshold leakage

current, modeling transistor current, detail view of power, energy & frequency,

energy point minimization & CMOS operation.

Chapter 3 Provides study about the high-k CMOS devices, need for high-k

materials, materials & considerations used for high-k CMOS devices, use in

industry, brief history of high-k dielectric development, applications.

Chapter 4 provides the study of tool Tanner EDA, types of tools used, procedure

to design schematic circuits, procedure to perform T-spice simulation.



Chapter 5 provides the implementation of ripple carry adder, design of full adder,

implementation of 32-bit ripple carry adder.

Chapter 6 provides the results obtained in this project and the detailed discussions

of these results.

In chapter 7, the summary and conclusion of this project work is addressed. Also

the future work that can be done.

In Appendix A, the detailed description of TANNER EDA 13.00 is given.

In Appendix B, the paper submitted to the conference has been discussed.


Chapter 1

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