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Principles OfPrinciples Of
Digital DesignDigital DesignChapter 1Chapter 1
Introduction
Design RepresentationLevels of AbstractionDesign Tasks and Design ProcessesCAD Tools
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2Copyright © 2004-2005 by Daniel D. Gajski Slides by Philip Pham, University of California, Irvine
Behavioral or functional representationSpecifies the behavior or the function of a design without any implementation information
Structural representationSpecifies the implementation of a design in terms of components and their interconnections
Physical representationSpecifies the physical characteristics of the design
Blueprint for manufacturing
Design RepresentationDesign Representation
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3Copyright © 2004-2005 by Daniel D. Gajski Slides by Philip Pham, University of California, Irvine
Pulse = Seconds = Seconds + 1S display = Seconds
Seconds = 0?
Minutes = 0?
Minutes = Minutes + 1M display = Minutes
Hours = Hours + 1H display = Hours
Clock Process
yes
yes
yes
no
no
no
Alarm Clock Alarm Clock (Behavioral Representation)(Behavioral Representation)
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4Copyright © 2004-2005 by Daniel D. Gajski Slides by Philip Pham, University of California, Irvine
S1 closed?
Minutes = Minutes + 1M display = Minutes
Hours = Hours + 1H display = Hours
Setup Process
S2 closed?S2 closed?
S3 closed? S3 closed?
S4 closed? S4 closed?
Mwakeup = Mwakeup + 1M display = Mwakeup
Hwakeup = Hwakeup + 1H display = Hwakeup
Not possible
yes
yesnoyes
yes
no
yes
no yesyes
no
no
no
no
Alarm Clock Alarm Clock (Behavioral Representation)(Behavioral Representation)
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5Copyright © 2004-2005 by Daniel D. Gajski Slides by Philip Pham, University of California, Irvine
Minutes = Mwakeup?
Buzz = 1
Alarm Process
Hours = Hwakeup?
S5 closed?
yesno
yesno
no yes
Alarm Clock Alarm Clock (Behavioral Representation)(Behavioral Representation)
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6Copyright © 2004-2005 by Daniel D. Gajski Slides by Philip Pham, University of California, Irvine
Alarm Clock Alarm Clock (Structural Representation)(Structural Representation)
S cnt
H display
M display
S display
M cnt H cnt M reg H reg
Minute comparator
Pulse generator
Oscillator
Hour comparator
1
Sound generator
Pulse
S1(Time set)
S3(M advance)
S4(H advance)
S2(Alarm set)
S5(Alarm on)
S2
S2
S3 S4
Buzz
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7Copyright © 2004-2005 by Daniel D. Gajski Slides by Philip Pham, University of California, Irvine
Alarm Clock Alarm Clock (Pulse Wave)(Pulse Wave)
1 second
0
1
(a) Sine wave
(b) Pulse wave
Generated by Oscillator
Generated by Pulse generator
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8Copyright © 2004-2005 by Daniel D. Gajski Slides by Philip Pham, University of California, Irvine
HOURSHOURS MINUTESMINUTES
ALARMALARMTIMESETTIMESET
ALMALM TIMETIME ONON OFFOFF
Front view
PG SGOSC
DS
Sound generatorPulse generatorOscillator
Minuteadvance switch
Batteryholder
Liquiddisplay
Houradvance switch
Setand alarmswitches
Printed circuit board
Alarm Clock Alarm Clock (Physical Representation)(Physical Representation)
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9Copyright © 2004-2005 by Daniel D. Gajski Slides by Philip Pham, University of California, Irvine
Levels of AbstractionLevels of Abstraction
Printed-circuit boards or
multi-chip modules
Processors, controllers,
memories, ASICs, ASIPs
Executable specification,
programsProcessor
MicrochipsAdders, comparators, registers, counters,
register files, queues
Algorithms, flowcharts,
instruction sets, generalized FSM
Register
Modulesor unitsGates, flip-flopsBoolean equations,
finite-state machinesGate
Analog & digitalcells
Transistors,resistors,capacitors
Differential eq., current-voltage
diagramsTransistor
Physical objects
Structural components
Behavioral formsLevels
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10Copyright © 2004-2005 by Daniel D. Gajski Slides by Philip Pham, University of California, Irvine
Top-down
Bottom-up
Meet-in-the-middle
Design MethodologiesDesign Methodologies
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11Copyright © 2004-2005 by Daniel D. Gajski Slides by Philip Pham, University of California, Irvine
Design SpecificationLibrary DevelopmentDesign Synthesis
Design AnalysisProperty verificationConstraint satisfaction for cost, performance, power, testability manufacturing, and other metrics
DocumentationManufacturing
Design ProcessDesign Process
Layout generationSequential synthesisCircuit designArchitecture synthesisLogic synthesisSystem synthesis
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12Copyright © 2004-2005 by Daniel D. Gajski Slides by Philip Pham, University of California, Irvine
Design Capture and ModelingSchematic captureModeling in a hardware-description language
Synthesis ToolsLogic synthesisSequential synthesisBehavioral or high-level synthesisSystem synthesis
Verification and SimulationPhysical Design
PlacementRouting
Testing
CAD ToolsCAD Tools
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13Copyright © 2004-2005 by Daniel D. Gajski Slides by Philip Pham, University of California, Irvine
Typical Design ProcessTypical Design Process
Verification or Simulation
TestingProduct Design
ManufacturingProduct Architecture
DocumentationProduct Specification
Test GenerationProduct Requirements
Physical DesignMarket Analysis
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14Copyright © 2004-2005 by Daniel D. Gajski Slides by Philip Pham, University of California, Irvine
Road Map of Digital DesignRoad Map of Digital DesignTransistors,
resistors,capacitors
Analogcircuitdesign
Analogcomponents
Digitalcircuitdesign
Electronics
Booleanalgebra
Logic gates and flip-flops
Finite-state machine
Logical design techniques
Sequential design techniques
VLSIdesign
Binary system and data
representation
Combinationalcomponents
Storagecomponents
Interfacecomponents
Generalizedfinite-statemachines
Algorithmsynthesis
Processorcomponents
Software design and engineering
Hardware, software, and mechanical codesign
Embedded system design
Computer design
Material covered in book
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15Copyright © 2004-2005 by Daniel D. Gajski Slides by Philip Pham, University of California, Irvine
Chapter SummaryChapter SummaryThree Design Representations
BehavioralStructuralPhysical
Four Levels of AbstractionSystemProcessorRegisterGate
CAD ToolsCapture and ModelingVerification and SimulationSynthesis and AnalysisPlacement and RoutingTest Generation
Road Map