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Electrical and Computer Engineering

ECE Technical Reports

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SUBTHRESHOLD LEAKAGECONTROL BY MULTIPLE CHANNEL

LENGTH CMOS (McCMOS)Mark Johnson Kaushik Roy

Purdue University School of Electrical and Computer Engineering,Purdue University School of Electrical and Computer Engineering,

This paper is posted at Purdue e-Pubs.

http://docs.lib.purdue.edu/ecetr/80


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SUBTHRESHOLDLEAKAGE CONTROL

BYMULTIPLECHANNEL LENGTHCMOS (McCMOS)

TR-ECE 97-11

NOVEMBER1997


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S~b t~h r e sho ldLeakage Control by MultipleChannel Length CMOS (McCMOS)*

Mark Johnson and Kaushik Roy

School of Electrical Engineering

Pu rd ue University

West Lafayette, IN 47907-1285{mcjohnso,kaushik}Qecn.purdue.edu

- -*Th is research was supported in part by ARPA (F33615-95-C-1625), NSF CAREERa w x d (9.501869-MIP), IRM, Rockwell, AT&T/Lucent , and ASSERT program (DAAH04-

96-1-0222).


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Abstract

In sub-micron CMOS design, non-minimum length transistorsoffer the possibility of achieving excellent leakage control with-out th e disadvantages of other known leakage control techniques.

Preliminary analyses indicate t ha t one can expect leakage reduc-

tion by a factor of at least 100 (and possibly orders ofmagnitudehigher) with only modest increases in circuit area and switched

capacitance. This paper briefly reviews related leakage cor~troltechniques, describes the McCMOS technique, and presents :sim-ulation results tha t are indicative of the performance of the tech-

nique.


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Contents

1 Introduction

2 McCMOS Technique

3 Summary


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List ofFigures1 I-V curves for different t ransi stor dimensions . . . . . . . . . . 9

2 Subthreshold character isti c for different trans istor dimensions 10

3 Leakage savings ratios relative to 3u/0.5u transistor . . . . . . 11


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1 Introduction

The most aggressive high performance CMOS designs today require ex-tremely short channel transistors and low supply voltages close to 1V andlower in order to achieve maximum performance while keeping power andheat dissipation down to acceptable levels. A side effect of this progress

has been the unavoidable use of low threshold transistors resulting in vastly

increased leakage currents. Low power supply voltages force us to use low

threshold voltages in order to maintain performances since propagation de-vlay is roughly proportional to r h D ~ ~ , T e for short channel devices. In addi-

tion, short channel lengths naturally lead to low threshold voltage:; that are

also subject to considerable variation due to variations in dopant quanti -

ties. I'vloreover, drain induced barrier lowering (VTHreduction proportionalto IfDs) and dopant variations become more and more pronounced as chan-ne s are shortened. We propose the use of multiple channel lengths as a

means of alleviating the large leakage currents that result from short channel

effects.

We have only been able to identify one previous application of multiplechannel length CMOS design [ I ] , but it was intended for multiple voltageapl>lications not leakage control. The voltages involved were 5V and 3.3V,supply voltages for which low threshold voltages and leakage control are not


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required. Researchers have docunlented other leakage control techniques th atinvolve process nlodifications or use of bias voltages. One very effective ap-proach is the MTCNIOS (Multiple Threshold voltage CMOS) technique de-veloped by Mutoh an d others [8 ,9] . In Mutoh's work, high and low thresholdvoltage devices are achieved by additional processing steps so as to obtaindifferent doping levels in the channel of each transistor. The high threshold

clfvices are placed between the power rails and the remaining lower thresh-old circuitry. When t he high threshold devices are turned off (only during

periods when the circuit is idle), leakage through the affected circuitry is

reduced by orders of magnitude. Mutoh shows that the leakage ol' the highthreshold device is on the order of of the leakage of a same sized lowthreshold device. Other techniques include control of threshold voltage by

means of substrate bias [6, Fj], or by biasing the transistor source terminal [ l o ]to obtain I,kS< 0 and a slight increase in threshold voltage.


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2 McCMOS TechniqueWe propose to use increased channel lengths wherever needed to colntrol leak-age current. The effect of channel length on threshold voltage (and leakage)

has been well documented [7.2] , demonstrating tha t VTHdecreases rapidly asefrective channel length ( LEPF )is reduced. Usually this is viewed as a chal-lenge to overcome in an effort to produce smaller devices. We propose thatthis behavior be exploited, where appropriate, to increase threshold voltage

and lower leakage.

Figures 1 , 2, and 3 present simulation results which demon:;trate thesavings possible when channel lengths are increased. All of t he transistors

indicated were simulated in HSPICE using a BSIM model for a 0 . 5 ~MOSISprocess. T he flat band voltage (VFBO)was adjusted to simulate the effect ofa reduced threshold voltage (approximately 0.25V). Three graph:; are pre-sented. Figure 1 presents IDSvs. VDsgiven IkS= 1..5V. This graph is usedto illustrate th e relative current drive capabilities for the device dimerlsionst o be compared. Figure 2 presents the subthreshold characteristic of each

device. Here we can see the impace of LEFFon the subthresholcll current.Figure 3 presents the IDS of each device divided by the IDS for the refer-ence device (W=3u, L=0.5u). In the region where VGs< I / T H , this graphindicates t he factor of leakage savings (relative to a 3u/0.5u device). We see


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that by increasing channel length alone from 0.511to l u , we obtain a leakagesa,vings ratio on the order of 2.50 while reducing current drive bj. about i.Increasing width to compensate for performance loss still allows 11s a 100

fold leakage improvement. Th e curves for a W = 1221, L = 4tr device show usthat much greater savings are possible if we can tolerate the cost in area and

capacitance. We anticipate much greater savings for smaller technologies onth e order of0 . 2 ~and lower for which the DIBL effect is more severe than at0 . 3 ~ .


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Figure 1: I-V curves for different transistor dimensions

9


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l?igure 2: Subthreshold cha.ra.cteristic for different transistor dimlensions

10


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Leakage Savings Ratio (Idslldsref) vs. Vgs with Vds=l.SV-- ~ ~ -, - - - ~ - - - ~ - -~~ - - - - - - - - - ~-~ -

- Wave--- S+bo 500 21 DO:Al:iratl2x3u -- I

M):Al:iratl2xGu -r - 48 0 -D@Al:iratl4xlZu -- ~p~ ~- 1 ,46 0 1 12d2u

8, . .

440 -

50m 100m 150m 200m 250m 300m 350m 400m 45Om 500m 5 5 0 1 n ~ ~Vollage X (lin) (VOLTS)

-

-

Figure 3: Leakage savings ratios relative to 3u/0.5u transistor


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From these graphs, we propose two design principles to exploit t he channel

length vs. leakage relationship.

In the non-critical path of a circuit we should increase the channel

length of at least one transistor (preferably one with a high probabilit-yof being turned off) in each possible current path between I fDu andground.

In critical paths, apply the same technique but increase transistor width

as necessary to maintain performance.

Clearly there are costs (area and switched capacitance) invo1vr.d in thistechnique, but they are modest in comparison to other known techniques.

Area costs should be no more than MTCMOS which requires th e insertion of

wide leakage control transis tors. Area costs also should be mitigatt:d by thefact that the channel area of any single transistor in the pull down or pull

up pa th of a CMOS gate is a small fraction of t he to tal ga te area. Switchingcapacitance will also increase due to larger gates on some transistors . How-

ever, McCMOS is intended for operating conditions for which leakage power(in the absence of leakage control) can equal or exceed switching power. Un-

der such conditions, leakage power savings should far exceed the increase in

switching power.


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The chief advantage of McCMOS over other leakage control techniques is

simplicity. One merely needs to lengthen t he drawn channel length of selected

tri~nsistors.This can be accomplished with existing CAD tools and existingsingle l/THprocesses. Other techniques require eithe r additional processingsteps or additional bias control circuitry that would not otherwise be neededfoi. CMOS design. Another significant advantage of McCMOS is the abilityto reduce leakage during both active and idle periods of circuit operation.

3 Summary

We propose McCMOS, a technique to control leakage by means of' multipletransistor channel lengths. Our preliminary results show that this technique

offers leakage savings comparable to other more costly technique:; without

requirement for process changes or bias control circuitry. Furthernlore, Mc-CRdOS makes it convenient to control leakage even when a circuit is active. Itis c:xpected tha t th e benefits of this technique will only increase as ininimumfeatu re sizes continue t o shrink.


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[I: Bhattacharyya, ,4. Mann, R. Nowak, E. Piro, R.Springer, J . Springer, S.Wong, D. "Half-micron manufacturable high perforniance CMOS tech-nology applicable for multiple power supply applications.", Int Sym,pVLSI Techno1 Sys Apyl Proc Tech Pap. 1989, p. 321-326.

[2] T. Fjeldly "Threshold Voltage Modeling and th e Subthreshold l tegime ofOperation of Short-Channel M O S F E T ' s " , IEEE Transactions on Elec-tron Devices V . 40, No. 1, Jan. 1993, p.137-145.

[3] M. Horiguchi, T . Sakata, I< . I toh, "Switched-Source Impedance CMOSCircuit for Low Standby Subthreshold Current Giga-Scale LSI's", IEEEJ o ~ ~ r ~ z a lof Solid-State Circuits V. 28, No. 11, Nov. 1993.

[4] T. Kawahara et. al. "Subthreshold Current Reduction for Decoded-Driverby Self-Reverse Biasing", IEEE Jollrrzal of Solid-State Circuits V. 28,No. 11, Nov. 1993, p. 1136-1143

[5] M. Kubo et. al. "A Threshold Voltage Controlling Circuit for Short Chan-

nel MOS Integrated Circuits", IEEE International Solid Statt Ci.rcuitsConference 1976, p.54-.5.5.

[ti] T. Ku r o d a et. al. "A 0.9V 150MHz lOmW 3mm2 2-D Discrete CosineTransform Core Processor with VTariable-Threshold-iroltageScheme": IEEE International Solid State Circuits Conference 1996, p. 1616-167


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['i] Z-H. Liu et . al. "Threshold Voltage Model for Deep-Submicromleter MOS-F ET ' s " , IEEE Transactions on Electron Devices V. 40, No. 1, Jan. 1993,p.86-95.

[I ] S. Mutoh et. al. " l-V Power Supply High-Speed Digit,al Circuit Technol-ogy with Multithreshold-Voltage CMOS", IEEE Jo,urnal of Solid-stateCircuits V. 30, No. 9, Aug. 1995, p.847-853

[9 ] S. Shigematsu et. al. "A l-V high-speed MTCMOS circuit scheme forpower-down applications", IEEESy,mposiumon VLSI Circuit:; Digest ofTechnical Pape,rs 1995, p. 125-126.

[ l o ] T. Yamagata et. al. "Low Voltage Circuit Design Techniques fclr Battery-Operated an d / o r Giga-Scale DRAM'S" , IEEE Journal of Solid-State Cir-cuits V. 30, NO. 1, NOV. 1995, p.1183-118s.

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