Chameli Devi School of Engineering
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CHAMELI DEVI SCHOOL OF ENGINEERING DEPARTMENT OF ELECTRONICS & COMMUNICATION ODD SEMESTER 2014-2015 STUDENT NAME: SEMESTER: VII ECE LABORATORY: VLSI DESIGN LABORATORY CODE: EC-605 ROLL NO.: BATCH: SL. NO. NAME OF THE EXPERIMENT DATE OF CON. DATE OF SUB. SIGNATURE AND REMARKS 1 To draw the Schematic Diagram and layout of 2 input NOR and NAND gate for the given technology, test its functionality and draw the simulation waveform. 2 To draw the Schematic Diagram and layout of Half adder for the given technology, test its functionality and draw the simulation waveform. . 3 To draw the Schematic Diagram and layout of Full adder for the given technology, test its functionality and draw the simulation waveform. 4 To draw the Schematic Diagram and layout of D latch for the given technology, test its functionality and draw the
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Transcript of Chameli Devi School of Engineering
Chameli Devi School of EngineeringDepartment of Electronics & CommunicationODD SEMESTER 2014-2015
Student Name: Semester: VII ECE LABORATORY: VLSI DESIGN LABORATORY CODE: EC-605 Roll No.: BATCH: Sl. No.Name of the ExperimentDate of Con.Date of Sub.Signature andRemarks
1To draw the Schematic Diagram and layout of 2 input NOR and NAND gate for the given technology, test its functionality and draw the simulation waveform.
2To draw the Schematic Diagram and layout of Half adder for the given technology, test its functionality and draw the simulation waveform. .
3To draw the Schematic Diagram and layout of Full adder for the given technology, test its functionality and draw the simulation waveform.
4To draw the Schematic Diagram and layout of D latch for the given technology, test its functionality and draw the simulation waveform.
5To draw the Schematic Diagram and layout of FlipFlop using D latch for the given technology, test its functionality and draw the simulation waveform. .
6To draw the Schematic Diagram and layout of an Encoder for the given technology, test its functionality and draw the simulation waveform.
7To draw the Schematic Diagram and layout of Decoder for the given technology, test its functionality and draw the simulation waveform. .
8To draw the Schematic Diagram and layout of Ripple Counter for the given technology, test its functionality and draw the simulation waveform.
9To draw the Schematic Diagram and layout of Shift register for the given technology, test its functionality and draw the simulation waveform.
10To draw the Schematic Diagram and layout of 4*1 Multiplexer for the given technology, test its functionality and draw the simulation waveform. .
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